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Centos-kernel-stream-9/drivers/gpu/drm/i915/Makefile

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
# SPDX-License-Identifier: GPL-2.0
drm: reorganise drm tree to be more future proof. With the coming of kernel based modesetting and the memory manager stuff, the everything in one directory approach was getting very ugly and starting to be unmanageable. This restructures the drm along the lines of other kernel components. It creates a drivers/gpu/drm directory and moves the hw drivers into subdirectores. It moves the includes into an include/drm, and sets up the unifdef for the userspace headers we should be exporting. Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-05-29 00:09:59 +00:00
#
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
Merge DRM changes from upstream v6.10..v6.11 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.11 RHEL-53570 JIRA: https://issues.redhat.com/browse/RHEL-53570 Conflicts: drivers/gpu/drm/vmwgfx/vmwgfx_msg_x86.h Conflict resolution: diff --cc drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 323c33c9c37aa,c6b669866fed1..349a0ef6fd1fc --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@@ -16,14 -16,10 +16,10 @@@ #include <linux/gpio/consumer.h> #include <linux/delay.h> #include <linux/module.h> -#include <linux/of.h> +#include <linux/of_device.h> #include <linux/regulator/consumer.h> - #define JD9365DA_INIT_CMD_LEN 2 - - struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; - }; + struct jadard; struct jadard_panel_desc { const struct drm_display_mode mode; Commit list: commit 869e54d4d54b1b0ee16c98c2149f5785eea08c02 commit 06e7139a034f26804904368fe4af2ceb70724756 commit 8f21f82d8b7652e11e6800612e34547bffdc7fd2 commit 1cb4db30cf685709584743d8bf8a0db2eac620c9 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commit 94c4aa266111262c96c98f822d1bccc494786fee commit bb7e19bd6cb68e08272e08acb814b9342ad5a43d commit 690e516e9869791bcac00ad5a351d953a928044b commit 135be1dc46c64c454f2828dbb7f239d035f47180 Signed-off-by: Robert Foss <rfoss@redhat.com>
2024-11-21 22:32:33 +00:00
# Enable W=1 warnings not enabled in drm subsystem Makefile
Merge DRM changes from upstream v6.6..v6.7 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.7 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drivers/gpu/drm/amd/amdgpu/psp_v13_0.c drivers/gpu/drm/amd/amdgpu/soc15.c drivers/gpu/drm/amd/amdkfd/kfd_svm.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h drivers/gpu/drm/amd/display/modules/power/power_helpers.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/display/intel_cdclk.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/display/intel_display_device.h drivers/gpu/drm/i915/display/intel_display_power_well.c drivers/gpu/drm/i915/display/intel_display_types.h drivers/gpu/drm/i915/display/intel_psr.c drivers/gpu/drm/i915/gt/intel_ggtt.c drivers/gpu/drm/i915/gt/intel_mocs.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_uvmm.h drivers/gpu/drm/nouveau/nvif/outp.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8e63aacb595b,93cf73d6fa11..23bf36604848 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -32,9 -32,8 +32,7 @@@ #include <linux/slab.h> #include <linux/iommu.h> #include <linux/pci.h> - #include <linux/devcoredump.h> - #include <generated/utsrelease.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> @@@ -4029,10 -4374,19 +4369,14 @@@ void amdgpu_device_fini_sw(struct amdgp kfree(adev->bios); adev->bios = NULL; + + kfree(adev->fru_info); + adev->fru_info = NULL; + - px = amdgpu_device_supports_px(adev_to_drm(adev)); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(adev_to_drm(adev))) { vga_switcheroo_unregister_client(adev->pdev); - - if (px) vga_switcheroo_fini_domain_pm_ops(adev->dev); - + } if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_unregister(adev->pdev); diff --cc drivers/gpu/drm/amd/display/dc/core/dc.c index 8cdf380bf366,5c1185206645..ebc7b005b7d3 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@@ -5285,3 -5518,20 +5518,19 @@@ void dc_set_edp_power(const struct dc * edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn); } + /* + ***************************************************************************** + * dc_get_power_profile_for_dc_state() - extracts power profile from dc state + * + * Called when DM wants to make power policy decisions based on dc_state + * + ***************************************************************************** + */ + struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) + { + struct dc_power_profile profile = { 0 }; + + profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + + return profile; + } - diff --cc drivers/gpu/drm/amd/display/dc/link/link_factory.c index 2c366866f570,7abfc67d10a6..ff7801aa552a --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@@ -367,27 -368,6 +368,30 @@@ static enum transmitter translate_encod } } +static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link) +{ + uint8_t pwrseq_inst = 0xF; ++ struct dc_context *dc_ctx = link->dc->ctx; ++ ++ DC_LOGGER_INIT(dc_ctx->logger); + + switch (link->eng_id) { + case ENGINE_ID_DIGA: + pwrseq_inst = 0; + break; + case ENGINE_ID_DIGB: + pwrseq_inst = 1; + break; + default: + DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", link->eng_id); + ASSERT(false); + break; + } + + return pwrseq_inst; +} + + static void link_destruct(struct dc_link *link) { int i; diff --cc drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 56e4c312cb7a,e1a5ee911dbb..869143b8f090 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@@ -742,11 -817,19 +818,11 @@@ static int smu_late_init(void *handle * handle the switch automatically. Driver involvement * is unnecessary. */ - if (!smu->dc_controlled_by_gpio) { - ret = smu_set_power_source(smu, - adev->pm.ac_power ? SMU_POWER_SOURCE_AC : - SMU_POWER_SOURCE_DC); - if (ret) { - dev_err(adev->dev, "Failed to switch to %s mode!\n", - adev->pm.ac_power ? "AC" : "DC"); - return ret; - } - } + adev->pm.ac_power = power_supply_is_system_supplied() > 0; + smu_set_ac_dc(smu); - if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || - (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) return 0; if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { diff --cc drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index d6336a1e8e43,5748a8581af4..86aa88df6b7a --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@@ -1387,9 -1381,8 +1381,8 @@@ static struct i2c_driver anx78xx_drive .name = "anx7814", .of_match_table = anx78xx_match_table, }, - .probe = anx78xx_i2c_probe, + .probe_new = anx78xx_i2c_probe, .remove = anx78xx_i2c_remove, - .id_table = anx78xx_id, }; module_i2c_driver(anx78xx_driver); diff --cc drivers/gpu/drm/bridge/lvds-codec.c index 67368f23d4aa,991732c4b629..19cccce2acf8 --- a/drivers/gpu/drm/bridge/lvds-codec.c +++ b/drivers/gpu/drm/bridge/lvds-codec.c @@@ -5,9 -5,9 +5,10 @@@ */ #include <linux/gpio/consumer.h> + #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --cc drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 4291798bd70f,824fb3c65742..778da07b7f81 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@@ -12,8 -12,10 +12,10 @@@ #include <linux/component.h> #include <linux/debugfs.h> #include <linux/iopoll.h> + #include <linux/math64.h> + #include <linux/media-bus-format.h> #include <linux/module.h> -#include <linux/platform_device.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index e7083689cf4d,1fd068e6e26c..8a82a7ebaf1e --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -701,20 -737,10 +741,11 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); - /* - * Seamless M/N update may need to update frame timings. - * - * FIXME Should be synchronized with the start of vblank somehow... - */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); - - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) - return; + goto out; if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { diff --cc drivers/gpu/drm/nouveau/nouveau_uvmm.h index ece2ea29e054,a308c59760a5..b11795dd655e --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.h +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.h @@@ -3,8 -3,8 +3,9 @@@ #ifndef __NOUVEAU_UVMM_H__ #define __NOUVEAU_UVMM_H__ - #include <drm/drm_gpuva_mgr.h> +#include <linux/maple_tree.h> + #include <drm/drm_gpuvm.h> + #include "nouveau_drv.h" struct nouveau_uvmm { Commit list: commit efcb492d77c42734aaf24aae02b4973323dc15d0 commit 78f46ecd9be8ec85a177c15d6188e1555657ba86 commit 192948f6a923bedf461b4aa09e70a25cfb8a6041 commit 96413b355a49fd684430a230479bd231d977894f commit 15f389da11257b806da75a070cfa41ca0cc15aae commit cc018c2626745d2e52273f941f9db222101aa11a commit b77d010d82eac31e161833b8e75d2983e3056171 commit 4bed08d99c681f1564e4a633b33d8a6d0446c706 commit b31f784ffff96643fa6dec31b182a3466cf4139e commit 5976a28b344ecb6810882a01b76a320cac21d307 commit 58554dbf0991da6a2847b3159594f6306bff978b commit 95c23e2085f28e2c763ca202fdc37a1392982c16 commit 199cf07ebd2b0d41185ac79b895547d45610b681 commit 637d3fdc109a63ed3d3864b9ffe1ae50ef57d03e commit d19859a042668277d79f8df0165ed75011f11e6d commit f5d8f9c0d8b4bc8ad7e7b23a9f4d116e99202dd3 commit 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commit 11f9eb899ecc8c02b769cf8d2532ba12786a7af7 commit d4b6e7f582e29acac17bcaf7f7771138d72f89d2 commit 2bd7a06a1208aaacb4e7a2a5436c23bce8d70801 commit ee11d2d37f5c05bd7bf5ccc820a58f48423d032b commit 9cdef4f720376ef0fb0febce1ed2377c19e531f9 commit 0cc9e952e6efa1f6f2597a305ea20d4b6ecc7573 commit ff5ab42b7926682080d87993a850a4d4b8d379e0 commit faa21f4c20960fee268bdb0fe977ed0edb6685fe commit 7e725c20fea8914ef1829da777f517ce1a93d388 commit 21f6137c64c65d6808c4a81006956197ca203383 commit 202260f64519e591b5cd99626e441b6559f571a3 commit 21ff3cc851565c01cbc25c64e506fe99c26b51aa commit 43d7e8b0127cc5f77916067431f31b424156cf74 commit f71cee97a644a6dfa3bc0eb69e29a53eab49b98d commit ed9895d8d45af78866acea5f5b42f6041abc9d4a commit 24ab185d9804e48041b370fa9354d6d941ce0a32 commit 34ce62a51e65a8b1fce0eb64dea2719c9429b306 commit 7854ea0e408d7f2e8faaada1773f3ddf9cb538f5 commit a9b9b42b54b2c9251144b3b9d4ebcd83e5f8c230 commit 3108cc03236b54c56e34de01227cdacf764c50a8 commit cf22fc2846cee83061082fa373574d6cdeb4c006 commit 59f6a3d8db2573aba994b95074d8f9911c969bcb commit 4ae3a20102b20d1927737e1a78615386d58e194d commit 9c9dd22ba5d747cceee3d1b1757448b5c48ac705 commit eacabb5462717a52fccbbbba458365a4f5e61f35 commit eb284f4b37817d2038fdfe1a9d51769730ab7b5f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 03:58:11 +00:00
subdir-ccflags-y += $(call cc-option, -Wformat-truncation)
# Enable -Werror in CI and development
drm/i915: Add -Wall -Wextra to our build, set warnings to full Recently W=1 on gcc-7.2 (-Wunused-const-variable) caught a regression that had been lurking for 6 months, so lets try enabling the full set of warnings for CI builds. This means more patches will be rejected early that contain trivial and sometimes not so trivial bugs. However, our code does not yet compile cleanly with W=1, so we have to apply a filter to the set of warnings until we can eliminate the mistakes. It also means that developers will have to be running the full gamut of gcc to ensure that as warnings come and go with gcc updates, we have the CI build prepared. v2: Use fine-grained -Wno overrides. Inside the makefile, we can specify CFLAGS on a per-object level, which allows us to limit the scope of any particular warning override. v3: Place per-file overrides after the main enabling block. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Tomi Sarvela <tomi.p.sarvela@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171024181547.27889-1-chris@chris-wilson.co.uk Acked-by: Jani Nikula <jani.nikula@intel.com>
2017-10-24 18:15:47 +00:00
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
Merge DRM changes from upstream v6.6..v6.7 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.7 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drivers/gpu/drm/amd/amdgpu/psp_v13_0.c drivers/gpu/drm/amd/amdgpu/soc15.c drivers/gpu/drm/amd/amdkfd/kfd_svm.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h drivers/gpu/drm/amd/display/modules/power/power_helpers.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/display/intel_cdclk.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/display/intel_display_device.h drivers/gpu/drm/i915/display/intel_display_power_well.c drivers/gpu/drm/i915/display/intel_display_types.h drivers/gpu/drm/i915/display/intel_psr.c drivers/gpu/drm/i915/gt/intel_ggtt.c drivers/gpu/drm/i915/gt/intel_mocs.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_uvmm.h drivers/gpu/drm/nouveau/nvif/outp.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8e63aacb595b,93cf73d6fa11..23bf36604848 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -32,9 -32,8 +32,7 @@@ #include <linux/slab.h> #include <linux/iommu.h> #include <linux/pci.h> - #include <linux/devcoredump.h> - #include <generated/utsrelease.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> @@@ -4029,10 -4374,19 +4369,14 @@@ void amdgpu_device_fini_sw(struct amdgp kfree(adev->bios); adev->bios = NULL; + + kfree(adev->fru_info); + adev->fru_info = NULL; + - px = amdgpu_device_supports_px(adev_to_drm(adev)); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(adev_to_drm(adev))) { vga_switcheroo_unregister_client(adev->pdev); - - if (px) vga_switcheroo_fini_domain_pm_ops(adev->dev); - + } if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_unregister(adev->pdev); diff --cc drivers/gpu/drm/amd/display/dc/core/dc.c index 8cdf380bf366,5c1185206645..ebc7b005b7d3 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@@ -5285,3 -5518,20 +5518,19 @@@ void dc_set_edp_power(const struct dc * edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn); } + /* + ***************************************************************************** + * dc_get_power_profile_for_dc_state() - extracts power profile from dc state + * + * Called when DM wants to make power policy decisions based on dc_state + * + ***************************************************************************** + */ + struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) + { + struct dc_power_profile profile = { 0 }; + + profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + + return profile; + } - diff --cc drivers/gpu/drm/amd/display/dc/link/link_factory.c index 2c366866f570,7abfc67d10a6..ff7801aa552a --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@@ -367,27 -368,6 +368,30 @@@ static enum transmitter translate_encod } } +static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link) +{ + uint8_t pwrseq_inst = 0xF; ++ struct dc_context *dc_ctx = link->dc->ctx; ++ ++ DC_LOGGER_INIT(dc_ctx->logger); + + switch (link->eng_id) { + case ENGINE_ID_DIGA: + pwrseq_inst = 0; + break; + case ENGINE_ID_DIGB: + pwrseq_inst = 1; + break; + default: + DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", link->eng_id); + ASSERT(false); + break; + } + + return pwrseq_inst; +} + + static void link_destruct(struct dc_link *link) { int i; diff --cc drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 56e4c312cb7a,e1a5ee911dbb..869143b8f090 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@@ -742,11 -817,19 +818,11 @@@ static int smu_late_init(void *handle * handle the switch automatically. Driver involvement * is unnecessary. */ - if (!smu->dc_controlled_by_gpio) { - ret = smu_set_power_source(smu, - adev->pm.ac_power ? SMU_POWER_SOURCE_AC : - SMU_POWER_SOURCE_DC); - if (ret) { - dev_err(adev->dev, "Failed to switch to %s mode!\n", - adev->pm.ac_power ? "AC" : "DC"); - return ret; - } - } + adev->pm.ac_power = power_supply_is_system_supplied() > 0; + smu_set_ac_dc(smu); - if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || - (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) return 0; if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { diff --cc drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index d6336a1e8e43,5748a8581af4..86aa88df6b7a --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@@ -1387,9 -1381,8 +1381,8 @@@ static struct i2c_driver anx78xx_drive .name = "anx7814", .of_match_table = anx78xx_match_table, }, - .probe = anx78xx_i2c_probe, + .probe_new = anx78xx_i2c_probe, .remove = anx78xx_i2c_remove, - .id_table = anx78xx_id, }; module_i2c_driver(anx78xx_driver); diff --cc drivers/gpu/drm/bridge/lvds-codec.c index 67368f23d4aa,991732c4b629..19cccce2acf8 --- a/drivers/gpu/drm/bridge/lvds-codec.c +++ b/drivers/gpu/drm/bridge/lvds-codec.c @@@ -5,9 -5,9 +5,10 @@@ */ #include <linux/gpio/consumer.h> + #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --cc drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 4291798bd70f,824fb3c65742..778da07b7f81 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@@ -12,8 -12,10 +12,10 @@@ #include <linux/component.h> #include <linux/debugfs.h> #include <linux/iopoll.h> + #include <linux/math64.h> + #include <linux/media-bus-format.h> #include <linux/module.h> -#include <linux/platform_device.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index e7083689cf4d,1fd068e6e26c..8a82a7ebaf1e --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -701,20 -737,10 +741,11 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); - /* - * Seamless M/N update may need to update frame timings. - * - * FIXME Should be synchronized with the start of vblank somehow... - */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); - - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) - return; + goto out; if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { diff --cc drivers/gpu/drm/nouveau/nouveau_uvmm.h index ece2ea29e054,a308c59760a5..b11795dd655e --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.h +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.h @@@ -3,8 -3,8 +3,9 @@@ #ifndef __NOUVEAU_UVMM_H__ #define __NOUVEAU_UVMM_H__ - #include <drm/drm_gpuva_mgr.h> +#include <linux/maple_tree.h> + #include <drm/drm_gpuvm.h> + #include "nouveau_drv.h" struct nouveau_uvmm { Commit list: commit efcb492d77c42734aaf24aae02b4973323dc15d0 commit 78f46ecd9be8ec85a177c15d6188e1555657ba86 commit 192948f6a923bedf461b4aa09e70a25cfb8a6041 commit 96413b355a49fd684430a230479bd231d977894f commit 15f389da11257b806da75a070cfa41ca0cc15aae commit cc018c2626745d2e52273f941f9db222101aa11a commit b77d010d82eac31e161833b8e75d2983e3056171 commit 4bed08d99c681f1564e4a633b33d8a6d0446c706 commit b31f784ffff96643fa6dec31b182a3466cf4139e commit 5976a28b344ecb6810882a01b76a320cac21d307 commit 58554dbf0991da6a2847b3159594f6306bff978b commit 95c23e2085f28e2c763ca202fdc37a1392982c16 commit 199cf07ebd2b0d41185ac79b895547d45610b681 commit 637d3fdc109a63ed3d3864b9ffe1ae50ef57d03e commit d19859a042668277d79f8df0165ed75011f11e6d commit f5d8f9c0d8b4bc8ad7e7b23a9f4d116e99202dd3 commit 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commit 11f9eb899ecc8c02b769cf8d2532ba12786a7af7 commit d4b6e7f582e29acac17bcaf7f7771138d72f89d2 commit 2bd7a06a1208aaacb4e7a2a5436c23bce8d70801 commit ee11d2d37f5c05bd7bf5ccc820a58f48423d032b commit 9cdef4f720376ef0fb0febce1ed2377c19e531f9 commit 0cc9e952e6efa1f6f2597a305ea20d4b6ecc7573 commit ff5ab42b7926682080d87993a850a4d4b8d379e0 commit faa21f4c20960fee268bdb0fe977ed0edb6685fe commit 7e725c20fea8914ef1829da777f517ce1a93d388 commit 21f6137c64c65d6808c4a81006956197ca203383 commit 202260f64519e591b5cd99626e441b6559f571a3 commit 21ff3cc851565c01cbc25c64e506fe99c26b51aa commit 43d7e8b0127cc5f77916067431f31b424156cf74 commit f71cee97a644a6dfa3bc0eb69e29a53eab49b98d commit ed9895d8d45af78866acea5f5b42f6041abc9d4a commit 24ab185d9804e48041b370fa9354d6d941ce0a32 commit 34ce62a51e65a8b1fce0eb64dea2719c9429b306 commit 7854ea0e408d7f2e8faaada1773f3ddf9cb538f5 commit a9b9b42b54b2c9251144b3b9d4ebcd83e5f8c230 commit 3108cc03236b54c56e34de01227cdacf764c50a8 commit cf22fc2846cee83061082fa373574d6cdeb4c006 commit 59f6a3d8db2573aba994b95074d8f9911c969bcb commit 4ae3a20102b20d1927737e1a78615386d58e194d commit 9c9dd22ba5d747cceee3d1b1757448b5c48ac705 commit eacabb5462717a52fccbbbba458365a4f5e61f35 commit eb284f4b37817d2038fdfe1a9d51769730ab7b5f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 03:58:11 +00:00
# Support compiling the display code separately for both i915 and xe
# drivers. Define I915 when building i915.
subdir-ccflags-y += -DI915
Revert "kbuild: use $(src) instead of $(srctree)/$(src) for source directory" This reverts commit b1992c3772e69a6fd0e3fc81cd4d2820c8b6eca0. JIRA: https://issues.redhat.com/browse/RHEL-76500 Upstream Status: RHEL-only It's a partial revert, only the changes in drivers/gpu/drm that were backported are reverted. This caused build error, if you try to build with "O=" Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2025-02-04 13:25:39 +00:00
subdir-ccflags-y += -I$(srctree)/$(src)
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
drm/i915: Go OCD on the Makefile Chris suggested to split things up a bit into the different parts of the driver and also sort it all correctly, with the hope that we're trying to organize things a bit better eventually. It should also help newcomers to orient themselves a bit better. v2: - Move intel_pm.c to the core - to make things perfect we should split out the modeset related pm features (psr/fbc) into a separate file. Maybe something Rodrigo can do once the PSR patches have settled. - Split the modesetting sections into core and encoders/outputs. intel_ddi.c is a bit funky since it has core hsw+ support and ddi output support. Whatever. v3: Failed to git add ... v4: Really go ocd, i.e. spelling fix in a comment from Jani. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-07 08:17:21 +00:00
# Please keep these build lists sorted!
# core driver code
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-y += \
i915_config.o \
i915_driver.o \
i915_drm_client.o \
i915_getparam.o \
i915_ioctl.o \
i915_irq.o \
i915_mitigations.o \
i915_module.o \
i915_params.o \
i915_pci.o \
i915_scatterlist.o \
i915_suspend.o \
i915_switcheroo.o \
i915_sysfs.o \
i915_utils.o \
intel_clock_gating.o \
intel_device_info.o \
intel_memory_region.o \
intel_pcode.o \
intel_region_ttm.o \
intel_runtime_pm.o \
intel_sbi.o \
intel_step.o \
intel_uncore.o \
intel_wakeref.o \
vlv_sideband.o \
vlv_suspend.o
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
Merge DRM changes from upstream v6.2..v6.3 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.3 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/display/drm_dp_aux_bus.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/i915_irq.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6ff156cd64ae,54933903bcb8..fe2752ec67f7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -1017,10 -1029,10 +1022,11 @@@ int svm_migrate_init(struct amdgpu_devi r = devm_memremap_pages(adev->dev, pgmap); if (IS_ERR(r)) { pr_err("failed to register HMM device memory\n"); + /* Disable SVM support capability */ pgmap->type = 0; - devm_release_mem_region(adev->dev, res->start, resource_size(res)); + if (pgmap->type == MEMORY_DEVICE_PRIVATE) + devm_release_mem_region(adev->dev, res->start, resource_size(res)); return PTR_ERR(r); } diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index b617b27577ef,d5b5d40ed817..710e51d2377f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -686,8 -683,15 +687,16 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); + /* + * Seamless M/N update may need to update frame timings. + * + * FIXME Should be synchronized with the start of vblank somehow... + */ + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + intel_crtc_update_active_timings(new_crtc_state); + - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; Commit list: commit 7ae2e684854cd955eff8daceff84fea33a1c94be commit 192bb40f030a41ca95c5cff8c9340b725bc7ba8b commit 4b9cc6efeb0684912d518e9953a1d493b2b89a02 commit 3b5130a68df1a513713b027d03125ba11ebc2975 commit 6ebf5caf1fae75634b0564152958ecb433cfa952 commit 201ec1bbca03a0c190962626574f8061a84cc9e7 commit c584f86c6242dff11d3e8f7b1646e5470a132784 commit d82b9a898d52a30adbedd158222f162489db52ac commit 09b350d7b05a62c9a59e201fcad4331ac6ee40c7 commit ef228dbfff70ca5823495d78ddb632abe230ce6f commit f322ed0d76ef0c0f2be99780c2a40ac405411cf5 commit 7aa3d63e1ad56c174536a5aba76d8a54c4c5acb4 commit 8b83e1a455382dc667898a525a93f4eb6716cc41 commit e3ddd2d25533d1cc6f9fea421e4a5f16b60b3434 commit 71feb6f901ecba962177a0a029dc545c91a4b396 commit 7df34a619f59439f38e56d389df02ee7e9e8cc97 commit 834c23e4f798dcdc8af251b3c428ceef94741991 commit 67b5655b2e717b8b681f8acd9cbddd2d687d5d4e commit e746f84b8e813816951b63485134927ed6763a1b commit 9a0a4ec530a7514ccd6061ecdeaf719a03cb34cd commit 25e0e5ae561003817797c23ae3b85cf510be11c5 commit 86c0ef7234a7c517b010fd5ecf1e176127bce521 commit 282e86eaa5d5e032541b5e3c0b9d0a55fe000607 commit 8853750dbad8f5dbf912a9f13b3fea41965634e1 commit f1c87a94a1087a26f41007ee83264033007421b5 commit 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commit f126f41cec1b6fa04c1d06517ec8f3e19908c5f7 commit 3b1f2be527ce04e7d8dce6fad6be16fa59058713 commit 00a4bd000e78a3a898e60bdc13e2852c8044a38c Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-05-02 06:34:23 +00:00
# core peripheral code
i915-y += \
soc/intel_dram.o \
soc/intel_gmch.o \
Merge DRM changes from upstream v6.12..v6.13 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.13 RHEL-75951 JIRA: https://issues.redhat.com/browse/RHEL-75951 Conflicts: drivers/dma-buf/udmabuf.c drivers/gpu/drm/Kconfig drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c drivers/gpu/drm/amd/display/Kconfig drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c drivers/gpu/drm/amd/display/dc/inc/core_types.h drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_syncobj.c drivers/gpu/drm/i915/display/intel_display_trace.h drivers/gpu/drm/i915/i915_trace.h drivers/gpu/drm/i915/i915_utils.h drivers/gpu/drm/panthor/panthor_device.h drivers/gpu/drm/xe/xe_devcoredump.c drivers/gpu/drm/xe/xe_devcoredump_types.h drivers/gpu/drm/xe/xe_guc_log.c drivers/gpu/drm/xe/xe_hw_engine.c drivers/gpu/drm/xe/xe_pci.c drivers/gpu/drm/xe/xe_wa.c drivers/gpu/drm/xe/xe_wa_oob.rules include/drm/intel/xe_pciids.h Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index 7f8cbb07a24f,772fc7625639..7c1f72832160 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -211,15 -209,48 +209,53 @@@ config DRM_DEBUG_MODESET_LOC If in doubt, say "N". + config DRM_CLIENT + bool + depends on DRM + help + Enables support for DRM clients. DRM drivers that need + struct drm_client_dev and its interfaces should select this + option. Drivers that support the default clients should + select DRM_CLIENT_SELECTION instead. + + config DRM_CLIENT_LIB + tristate + depends on DRM + select DRM_KMS_HELPER if DRM_FBDEV_EMULATION + select FB_CORE if DRM_FBDEV_EMULATION + help + This option enables the DRM client library and selects all + modules and components according to the enabled clients. + + config DRM_CLIENT_SELECTION + tristate + depends on DRM + select DRM_CLIENT_LIB if DRM_FBDEV_EMULATION + help + Drivers that support in-kernel DRM clients have to select this + option. + + config DRM_CLIENT_SETUP + bool + depends on DRM_CLIENT_SELECTION + help + Enables the DRM client selection. DRM drivers that support the + default clients should select DRM_CLIENT_SELECTION instead. + + menu "Supported DRM clients" + depends on DRM_CLIENT_SELECTION + config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" - depends on DRM + depends on DRM_CLIENT_SELECTION + select DRM_CLIENT + select DRM_CLIENT_SETUP select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT ++ select FB_SYS_IMAGEBLIT default FB help Choose this option if you have a need for the legacy fbdev diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bd0dab9811d1,cd4fac120834..d73f84c53e76 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -33,11 -35,11 +35,10 @@@ #include <linux/iommu.h> #include <linux/pci.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_event.h> #include <drm/drm_crtc_helper.h> - #include <drm/drm_fb_helper.h> #include <drm/drm_probe_helper.h> #include <drm/amdgpu_drm.h> #include <linux/device.h> @@@ -4494,16 -4584,18 +4617,15 @@@ fence_driver_init if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); - px = amdgpu_device_supports_px(ddev); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(ddev)) { + px = true; vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, px); - - if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + } - if (adev->gmc.xgmi.pending_reset) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --cc drivers/gpu/drm/display/drm_dp_mst_topology.c index f0c6d50d8c33,dc4446d589e7..6bff2d5eb59c --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@@ -4184,10 -4188,10 +4191,21 @@@ static int drm_dp_mst_handle_up_req(str out_put_primary: drm_dp_mst_topology_put_mstb(mst_primary); out_clear_reply: - memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx)); - return 0; + reset_msg_rx_state(&mgr->up_req_recv); + return ret; + } + ++static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) ++{ ++ mutex_lock(&mgr->lock); ++ if (mgr->reset_rx_state) { ++ mgr->reset_rx_state = false; ++ reset_msg_rx_state(&mgr->down_rep_recv); ++ reset_msg_rx_state(&mgr->up_req_recv); ++ } ++ mutex_unlock(&mgr->lock); +} + static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --cc drivers/gpu/drm/drm_syncobj.c index 4fcfc0b9b386,4f2ab8a7b50f..0058689f69fa --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@@ -712,19 -712,17 +712,17 @@@ static int drm_syncobj_fd_to_handle(str int fd, u32 *handle) { struct drm_syncobj *syncobj; - struct fd f = fdget(fd); + CLASS(fd, f)(fd); int ret; - if (!f.file) + if (fd_empty(f)) return -EINVAL; - if (f.file->f_op != &drm_syncobj_file_fops) { - fdput(f); + if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - } /* take a reference to put in the idr */ - syncobj = fd_file(f)->private_data; + syncobj = f.file->private_data; drm_syncobj_get(syncobj); idr_preload(GFP_KERNEL); diff --cc drivers/gpu/drm/hyperv/hyperv_drm_drv.c index 7ef4d7ea5468,e0953777a206..34d8d5ef2a62 --- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c @@@ -7,10 -8,9 +8,10 @@@ #include <linux/hyperv.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/screen_info.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_shmem.h> #include <drm/drm_gem_shmem_helper.h> diff --cc drivers/gpu/drm/i915/display/intel_display_trace.h index fbd3f83df807,9bd8f1e505b0..eeb73303e2e0 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@@ -61,10 -102,14 +102,14 @@@ TRACE_EVENT(intel_pipe_disable ), TP_fast_assign( - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc *it__; - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - for_each_intel_crtc(&dev_priv->drm, it__) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, it__) { __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); } @@@ -90,8 -132,8 +132,8 @@@ TRACE_EVENT(intel_crtc_flip_done ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -114,8 -156,8 +156,8 @@@ TRACE_EVENT(intel_pipe_crc ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); @@@ -141,9 -183,9 +183,9 @@@ TRACE_EVENT(intel_cpu_fifo_underrun ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = pipe; + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -166,9 -208,9 +208,9 @@@ TRACE_EVENT(intel_pch_fifo_underrun TP_fast_assign( enum pipe pipe = pch_transcoder; - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - __entry->pipe = pipe; + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -192,8 -234,12 +234,12 @@@ TRACE_EVENT(intel_memory_cxsr TP_fast_assign( struct intel_crtc *crtc; - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - for_each_intel_crtc(&dev_priv->drm, crtc) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, crtc) { __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); } @@@ -232,8 -276,8 +276,8 @@@ TRACE_EVENT(g4x_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; @@@ -279,8 -323,8 +323,8 @@@ TRACE_EVENT(vlv_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->level = wm->level; @@@ -316,8 -360,8 +360,8 @@@ TRACE_EVENT(vlv_fifo_size ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->sprite0_start = sprite0_start; @@@ -345,9 -389,9 +389,9 @@@ TRACE_EVENT(intel_plane_async_flip ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, __dev_name_kms(plane)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; @@@ -373,9 -417,9 +417,9 @@@ TRACE_EVENT(intel_plane_update_noarm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -404,9 -448,9 +448,9 @@@ TRACE_EVENT(intel_plane_update_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -433,9 -477,9 +477,9 @@@ TRACE_EVENT(intel_plane_disable_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); - __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; ++ __assign_str(name, plane->base.name); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -458,11 -502,12 +502,12 @@@ TRACE_EVENT(intel_fbc_activate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -485,11 -530,12 +530,12 @@@ TRACE_EVENT(intel_fbc_deactivate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -512,11 -558,12 +558,12 @@@ TRACE_EVENT(intel_fbc_nuke ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -538,8 -585,8 +585,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_star ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -561,8 -608,8 +608,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_end ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -586,8 -633,8 +633,8 @@@ TRACE_EVENT(intel_pipe_update_start ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->min = crtc->debug.min_vbl; @@@ -614,8 -661,8 +661,8 @@@ TRACE_EVENT(intel_pipe_update_vblank_ev ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = crtc->debug.start_vbl_count; __entry->scanline = crtc->debug.scanline_start; __entry->min = crtc->debug.min_vbl; @@@ -640,8 -687,8 +687,8 @@@ TRACE_EVENT(intel_pipe_update_end ), TP_fast_assign( - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = frame; __entry->scanline = scanline_end; ), diff --cc drivers/gpu/drm/xe/Makefile index b578ef68bc34,bc7a04ce69fd..21a1ecca0fea --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@@ -145,10 -147,9 +147,9 @@@ endi # i915 Display compat #defines and #includes subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ - -I$(src)/display/ext \ - -I$(src)/compat-i915-headers \ + -I$(srctree)/$(src)/display/ext \ + -I$(srctree)/$(src)/compat-i915-headers \ -I$(srctree)/drivers/gpu/drm/i915/display/ \ - -Ddrm_i915_gem_object=xe_bo \ -Ddrm_i915_private=xe_device # Rule to build SOC code shared with i915 diff --cc drivers/gpu/drm/xe/xe_gt_topology.c index 3e113422b88d,df2042db7ee6..f504b1012493 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@@ -129,8 -129,8 +129,20 @@@ static voi load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) { struct xe_device *xe = gt_to_xe(gt); - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3); + u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); + ++ /* ++ * PTL platforms with media version 30.00 do not provide proper values ++ * for the media GT's L3 bank registers. Skip the readout since we ++ * don't have any way to obtain real values. ++ * ++ * This may get re-described as an official workaround in the future, ++ * but there's no tracking number assigned yet so we use a custom ++ * OOB workaround descriptor. ++ */ ++ if (XE_WA(gt, no_media_l3)) ++ return; + /* * PTL platforms with media version 30.00 do not provide proper values * for the media GT's L3 bank registers. Skip the readout since we diff --cc drivers/gpu/drm/xe/xe_guc_log.c index be47780ec2a7,df4cfb698cdb..38db790f254b --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@@ -5,11 -5,14 +5,15 @@@ #include "xe_guc_log.h" + #include <linux/fault-inject.h> + #include <drm/drm_managed.h> +#include <linux/vmalloc.h> + #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_devcoredump.h" + #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_map.h" Commit list: commit 3973a8d052829dcc5193fb6330dcd13c2b7127ca commit 7a5115ba1d691bd14db91d2fcc3ce0b056574ce9 commit c7d84a45f4266e9ff4c61eddde4acbfddb8f6b57 commit eb4accc5234525e2cb2b720187ccaf6db99b705f commit 3742c20958a5b02ecba08d71036bae3e7b9d21b3 commit 2872a57c7ad427d428c6d12e95e55b32bdc8e3b8 commit 9c75b16cabc69adbbfdc9d219df87c9173f0da0a commit 3a8d97611b564b5b25f68c90b543056fc9ae0bec commit 9b79594aa470fd5fe2173d281fd604d11ec8e902 commit e8653e63e834e4c7de60b81b8b24deb7bdd3bf56 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commit 5db89168c408871d306e9fb669e494a1444da8ee commit b26de02cf903b5182588c0df91a6e1b512f7d3f3 commit 79a21fc921d7aafaf69d00b4938435b81bf66022 commit fa6493440f084c5ba8e30dce84158cbfeac86311 commit cf8182d33798966146c7eaab7209b606939a17c5 commit b1231ff7ea0689d04040a44864c265bc11612fa8 commit cfaf51adaf4e0b1850c84e05c81e879dd571c17c commit 9b1c673a1648cc3501a3b7719db2bec931cf00f7 commit 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d Signed-off-by: Robert Foss <rfoss@redhat.com>
2025-04-01 09:44:50 +00:00
soc/intel_pch.o \
soc/intel_rom.o
Merge DRM changes from upstream v6.2..v6.3 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.3 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/display/drm_dp_aux_bus.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/i915_irq.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6ff156cd64ae,54933903bcb8..fe2752ec67f7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -1017,10 -1029,10 +1022,11 @@@ int svm_migrate_init(struct amdgpu_devi r = devm_memremap_pages(adev->dev, pgmap); if (IS_ERR(r)) { pr_err("failed to register HMM device memory\n"); + /* Disable SVM support capability */ pgmap->type = 0; - devm_release_mem_region(adev->dev, res->start, resource_size(res)); + if (pgmap->type == MEMORY_DEVICE_PRIVATE) + devm_release_mem_region(adev->dev, res->start, resource_size(res)); return PTR_ERR(r); } diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index b617b27577ef,d5b5d40ed817..710e51d2377f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -686,8 -683,15 +687,16 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); + /* + * Seamless M/N update may need to update frame timings. + * + * FIXME Should be synchronized with the start of vblank somehow... + */ + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + intel_crtc_update_active_timings(new_crtc_state); + - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; Commit list: commit 7ae2e684854cd955eff8daceff84fea33a1c94be commit 192bb40f030a41ca95c5cff8c9340b725bc7ba8b commit 4b9cc6efeb0684912d518e9953a1d493b2b89a02 commit 3b5130a68df1a513713b027d03125ba11ebc2975 commit 6ebf5caf1fae75634b0564152958ecb433cfa952 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commit f126f41cec1b6fa04c1d06517ec8f3e19908c5f7 commit 3b1f2be527ce04e7d8dce6fad6be16fa59058713 commit 00a4bd000e78a3a898e60bdc13e2852c8044a38c Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-05-02 06:34:23 +00:00
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
# core library code
i915-y += \
i915_memcpy.o \
i915_mm.o \
i915_sw_fence.o \
drm/i915: Generalise the clflush dma-worker Extract the dma-fence worker used by clflush for wider use, as we anticipate using workers coupled to dma-fences more frequently. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190821191606.17001-1-chris@chris-wilson.co.uk
2019-08-21 19:16:06 +00:00
i915_sw_fence_work.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
i915_syncmap.o \
i915_user_extensions.o
drm/i915: Extract intel_runtime_pm.c Geez is the audio hack ugly. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Rebased on top of the skl patches.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-30 08:56:38 +00:00
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-$(CONFIG_COMPAT) += \
i915_ioc32.o
drm/i915/params: add i915 parameters to debugfs Add a debugfs subdirectory i915_params with all the i915 module parameters. This is a first step, with lots of boilerplate, and not much benefit yet. This will result in a new device specific debugfs directory at /sys/kernel/debug/dri/<N>/i915_params duplicating the module specific sysfs directory at /sys/module/i915/parameters/. Going forward, all users of the parameters should use the debugfs, with the module parameters being phased out. Add debugfs permissions to I915_PARAMS_FOR_EACH(). This duplicates the mode with module parameter sysfs, but the goal is to make the module parameters read-only initial values for device specific parameters. 0 mode will bypass debugfs creation. Use it for verbose_state_checks which will need special attention in follow-up work. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/600101c8433e7caf9303663fc85a9972fa1f05e7.1575560168.git.jani.nikula@intel.com
2019-12-05 15:43:40 +00:00
i915-$(CONFIG_DEBUG_FS) += \
i915_debugfs.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915_debugfs_params.o
i915-$(CONFIG_PERF_EVENTS) += \
i915_pmu.o
drm/i915: Go OCD on the Makefile Chris suggested to split things up a bit into the different parts of the driver and also sort it all correctly, with the hope that we're trying to organize things a bit better eventually. It should also help newcomers to orient themselves a bit better. v2: - Move intel_pm.c to the core - to make things perfect we should split out the modeset related pm features (psr/fbc) into a separate file. Maybe something Rodrigo can do once the PSR patches have settled. - Split the modesetting sections into core and encoders/outputs. intel_ddi.c is a bit funky since it has core hsw+ support and ddi output support. Whatever. v3: Failed to git add ... v4: Really go ocd, i.e. spelling fix in a comment from Jani. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-07 08:17:21 +00:00
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
# "Graphics Technology" (aka we talk to the gpu)
gt-y += \
drm/i915/gt: Split low level gen2-7 CS emitters Pull the routines for writing CS packets out of intel_ring_submission into their own files. These are low level operations for building CS instructions, rather than the logic for filling the global ring buffer with requests, and we will want to reuse them outside of this context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200601072446.19548-2-chris@chris-wilson.co.uk
2020-06-01 07:24:12 +00:00
gt/gen2_engine_cs.o \
gt/gen6_engine_cs.o \
drm/i915/gtt: split up i915_gem_gtt Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
2020-01-07 13:40:09 +00:00
gt/gen6_ppgtt.o \
drm/i915/gen7: Clear all EU/L3 residual contexts On gen7 and gen7.5 devices, there could be leftover data residuals in EU/L3 from the retiring context. This patch introduces workaround to clear that residual contexts, by submitting a batch buffer with dedicated HW context to the GPU with ring allocation for each context switching. This security mitigation changes does not triggers any performance regression. Performance is on par with current drm-tips. v2: Add igt generated header file for CB kernel assembled with Mesa tool and addressed use of Kernel macro for ptr_align comment. v3: Resolve Sparse warnings with newly generated, and imported CB kernel. v4: Include new igt generated CB kernel for gen7 and gen7.5. Also add code formatting and compiler warnings changes (Chris Wilson) Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Cc: Chris Wilson <chris.p.wilson@intel.com> Cc: Balestrieri Francesco <francesco.balestrieri@intel.com> Cc: Bloomfield Jon <jon.bloomfield@intel.com> Cc: Dutt Sudeep <sudeep.dutt@intel.com> Acked-by: Chris Wilson <chris@chris-wilso.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200306000957.2836150-2-chris@chris-wilson.co.uk
2020-03-06 00:09:57 +00:00
gt/gen7_renderclear.o \
drm/i915: split gen8+ flush and bb_start emission functions These functions are independent from the backend used and can therefore be split out of the exelists submission file, so they can be re-used by the upcoming GuC submission backend. Based on a patch by Chris Wilson. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201209233618.4287-3-chris@chris-wilson.co.uk Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2020-12-09 23:36:18 +00:00
gt/gen8_engine_cs.o \
drm/i915/gtt: split up i915_gem_gtt Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
2020-01-07 13:40:09 +00:00
gt/gen8_ppgtt.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
gt/intel_breadcrumbs.o \
gt/intel_context.o \
drm/i915/gt: Pull sseu context updates under gt Lift the routines to emit a request to update the SSEU on the intel_context out of i915_gem_context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200131104548.2451485-6-chris@chris-wilson.co.uk
2020-01-31 10:45:42 +00:00
gt/intel_context_sseu.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
gt/intel_engine_cs.o \
drm/i915/gt: Introduce barrier pulses along engines To flush idle barriers, and even inflight requests, we want to send a preemptive 'pulse' along an engine. We use a no-op request along the pinned kernel_context at high priority so that it should run or else kick off the stuck requests. We can use this to ensure idle barriers are immediately flushed, as part of a context cancellation mechanism, or as part of a heartbeat mechanism to detect and reset a stuck GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191021174339.5389-1-chris@chris-wilson.co.uk
2019-10-21 17:43:39 +00:00
gt/intel_engine_heartbeat.o \
drm/i915: Invert the GEM wakeref hierarchy In the current scheme, on submitting a request we take a single global GEM wakeref, which trickles down to wake up all GT power domains. This is undesirable as we would like to be able to localise our power management to the available power domains and to remove the global GEM operations from the heart of the driver. (The intent there is to push global GEM decisions to the boundary as used by the GEM user interface.) Now during request construction, each request is responsible via its logical context to acquire a wakeref on each power domain it intends to utilize. Currently, each request takes a wakeref on the engine(s) and the engines themselves take a chipset wakeref. This gives us a transition on each engine which we can extend if we want to insert more powermangement control (such as soft rc6). The global GEM operations that currently require a struct_mutex are reduced to listening to pm events from the chipset GT wakeref. As we reduce the struct_mutex requirement, these listeners should evaporate. Perhaps the biggest immediate change is that this removes the struct_mutex requirement around GT power management, allowing us greater flexibility in request construction. Another important knock-on effect, is that by tracking engine usage, we can insert a switch back to the kernel context on that engine immediately, avoiding any extra delay or inserting global synchronisation barriers. This makes tracking when an engine and its associated contexts are idle much easier -- important for when we forgo our assumed execution ordering and need idle barriers to unpin used contexts. In the process, it means we remove a large chunk of code whose only purpose was to switch back to the kernel context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-24 20:07:17 +00:00
gt/intel_engine_pm.o \
drm/i915/gt: Move the [class][inst] lookup for engines onto the GT To maintain a fast lookup from a GT centric irq handler, we want the engine lookup tables on the intel_gt. To avoid having multiple copies of the same multi-dimension lookup table, move the generic user engine lookup into an rbtree (for fast and flexible indexing). v2: Split uabi_instance cf uabi_class v3: Set uabi_class/uabi_instance after collating all engines to provide a stable uabi across parallel unordered construction. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20190806124300.24945-2-chris@chris-wilson.co.uk
2019-08-06 12:43:00 +00:00
gt/intel_engine_user.o \
drm/i915/gt: Rename lrc.c to execlists_submission.c We want to separate the utility functions for controlling the logical ring context from the execlists submission mechanism (which is an overgrown scheduler). This is similar to Daniele's work to split up the files, but being selfish I wanted to base it after my own changes to intel_lrc.c petered out. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201209233618.4287-2-chris@chris-wilson.co.uk
2020-12-09 23:36:17 +00:00
gt/intel_execlists_submission.o \
drm/i915/gtt: split up i915_gem_gtt Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
2020-01-07 13:40:09 +00:00
gt/intel_ggtt.o \
drm/i915: Move GGTT fence registers under gt/ Since the fence registers control HW detiling through the GGTT aperture, make them a part of the intel_ggtt under gt/ Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200316113846.4974-1-chris@chris-wilson.co.uk
2020-03-16 11:38:43 +00:00
gt/intel_ggtt_fencing.o \
drm/i915: Move intel_gt initialization to a separate file As it will grow in a following patch make a new home for it. v2: * Convert mock_gem_device as well. (Chris) v3: * Rename to intel_gt_init_early and move call site to i915_drv.c. (Chris) v4: * Adjust SPDX tags. * No need to gt/ path when including intel_gt_types.h. (Chris) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-3-tvrtko.ursulin@linux.intel.com
2019-06-21 07:07:41 +00:00
gt/intel_gt.o \
drm/i915/gt: Move the batch buffer pool from the engine to the gt Since the introduction of 'soft-rc6', we aim to park the device quickly and that results in frequent idling of the whole device. Currently upon idling we free the batch buffer pool, and so this renders the cache ineffective for many workloads. If we want to have an effective cache of recently allocated buffers available for reuse, we need to decouple that cache from the engine powermanagement and make it timer based. As there is no reason then to keep it within the engine (where it once made retirement order easier to track), we can move it up the hierarchy to the owner of the memory allocations. v2: Hook up to debugfs/drop_caches to clear the cache on demand. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430111819.10262-2-chris@chris-wilson.co.uk
2020-04-30 11:18:12 +00:00
gt/intel_gt_buffer_pool.o \
Merge DRM changes from upstream v6.8..v6.9 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.9 RHEL-24102 airlied: fix buddy test to use PAGE_SIZE for now backport s390x fb test fix fix i915 perf table sentinel (upstream removed need for these) JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/accel/drm_accel.c drivers/accel/habanalabs/common/command_submission.c drivers/accel/habanalabs/common/debugfs.c drivers/accel/habanalabs/common/device.c drivers/accel/habanalabs/common/firmware_if.c drivers/accel/habanalabs/common/habanalabs.h drivers/accel/habanalabs/common/hw_queue.c drivers/accel/habanalabs/common/hwmon.c drivers/accel/habanalabs/common/mmu/Makefile drivers/accel/habanalabs/common/mmu/mmu.c drivers/accel/habanalabs/common/mmu/mmu_v1.c drivers/accel/habanalabs/common/mmu/mmu_v2_hr.c drivers/accel/habanalabs/common/security.c drivers/accel/habanalabs/common/security.h drivers/accel/habanalabs/gaudi/gaudi.c drivers/accel/habanalabs/gaudi2/gaudi2.c drivers/accel/habanalabs/gaudi2/gaudi2P.h drivers/accel/habanalabs/goya/goya.c drivers/accel/habanalabs/goya/goya_coresight.c drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h drivers/accel/ivpu/ivpu_debugfs.c drivers/accel/ivpu/ivpu_drv.c drivers/accel/ivpu/ivpu_drv.h drivers/accel/ivpu/ivpu_fw.c drivers/accel/ivpu/ivpu_fw_log.c drivers/accel/ivpu/ivpu_gem.c drivers/accel/ivpu/ivpu_gem.h drivers/accel/ivpu/ivpu_hw.h drivers/accel/ivpu/ivpu_hw_37xx.c drivers/accel/ivpu/ivpu_hw_40xx.c drivers/accel/ivpu/ivpu_ipc.c drivers/accel/ivpu/ivpu_job.c drivers/accel/ivpu/ivpu_mmu.c drivers/accel/ivpu/ivpu_pm.c drivers/accel/ivpu/vpu_boot_api.h drivers/accel/ivpu/vpu_jsm_api.h drivers/accel/qaic/mhi_controller.c drivers/accel/qaic/qaic.h drivers/accel/qaic/qaic_data.c drivers/accel/qaic/qaic_drv.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/mgag200/mgag200_drv.c drivers/gpu/drm/mgag200/mgag200_mode.c drivers/gpu/drm/panel/panel-ilitek-ili9341.c drivers/gpu/drm/tegra/sor.c Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index ea46a61af148,5a0c476361c3..c43e8a298618 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -81,8 -81,7 +80,8 @@@ config DRM_KUNIT_TES select DRM_EXEC select DRM_EXPORT_FOR_TESTS if m select DRM_GEM_SHMEM_HELPER - select DRM_KMS_HELPER select DRM_KUNIT_TEST_HELPERS ++ select DRM_KMS_HELPER select DRM_LIB_RANDOM select PRIME_NUMBERS default KUNIT_ALL_TESTS diff --cc drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 324b46f78b32,1e6cc0bfc432..a0d088e43699 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@@ -3347,10 -3349,13 +3349,13 @@@ static int kfd_mmio_mmap(struct kfd_nod if (vma->vm_end - vma->vm_start != PAGE_SIZE) return -EINVAL; + if (PAGE_SIZE > 4096) + return -EINVAL; + address = dev->adev->rmmio_remap.bus_addr; - vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | - VM_DONTDUMP | VM_PFNMAP); + vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | + VM_DONTDUMP | VM_PFNMAP; vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 73a561af13d1,25593f6aae7d..22b80004574f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -580,42 -512,13 +512,14 @@@ void intel_pipe_update_start(struct int */ intel_psr_wait_for_idle_locked(new_crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); - crtc->debug.min_vbl = min; - crtc->debug.max_vbl = max; + crtc->debug.min_vbl = evade.min; + crtc->debug.max_vbl = evade.max; trace_intel_pipe_update_start(crtc); - for (;;) { - /* - * prepare_to_wait() has a memory barrier, which guarantees - * other CPUs can see the task state update by the time we - * read the scanline. - */ - prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); - - scanline = intel_get_crtc_scanline(crtc); - if (scanline < min || scanline > max) - break; - - if (!timeout) { - drm_err(&dev_priv->drm, - "Potential atomic update failure on pipe %c\n", - pipe_name(crtc->pipe)); - break; - } - - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) - local_irq_enable(); - - timeout = schedule_timeout(timeout); - - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) - local_irq_disable(); - } - - finish_wait(wq, &wait); + scanline = intel_vblank_evade(&evade); drm_crtc_vblank_put(&crtc->base); diff --cc drivers/gpu/drm/i915/i915_drv.h index f3be9033a93f,e81b3b2858ac..8ac1f870b911 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@@ -163,16 -163,8 +163,8 @@@ struct i915_gem_mm struct notifier_block oom_notifier; struct notifier_block vmap_notifier; - struct shrinker *shrinker; + struct shrinker shrinker; - #ifdef CONFIG_MMU_NOTIFIER - /** - * notifier_lock for mmu notifiers, memory may not be allocated - * while holding this lock. - */ - rwlock_t notifier_lock; - #endif - /* shrinker accounting, also useful for userland debugging */ u64 shrink_memory; u32 shrink_count; diff --cc drivers/gpu/drm/i915/intel_runtime_pm.c index 860b51b56a92,d4e844128826..38e42b20aedf --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@@ -246,8 -246,11 +246,8 @@@ static intel_wakeref_t __intel_runtime_ * function, since the power state is undefined. This applies * atm to the late/early system suspend/resume handlers. */ - if ((ignore_usecount && - pm_runtime_get_if_active(rpm->kdev) <= 0) || - (!ignore_usecount && - pm_runtime_get_if_in_use(rpm->kdev) <= 0)) - return 0; + if (pm_runtime_get_if_active(rpm->kdev, ignore_usecount) <= 0) - return 0; ++ return 0; } intel_runtime_pm_acquire(rpm, true); diff --cc drivers/gpu/drm/tegra/sor.c index 89afa6e808b8,bad3b8fcc726..d0ab8b46cf5a --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@@ -16,10 -16,11 +16,11 @@@ #include <soc/tegra/pmc.h> -#include <drm/display/drm_dp_helper.h> -#include <drm/display/drm_scdc_helper.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_debugfs.h> + +#include <drm/display/drm_dp_helper.h> + #include <drm/drm_edid.h> #include <drm/drm_eld.h> #include <drm/drm_file.h> #include <drm/drm_panel.h> diff --cc drivers/video/Makefile index 831c9fa57a6c,831c9fa57a6c..db6568e69be7 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@@ -2,8 -2,8 +2,7 @@@ obj-$(CONFIG_APERTURE_HELPERS) += aperture.o obj-$(CONFIG_VGASTATE) += vgastate.o --obj-$(CONFIG_VIDEO_CMDLINE) += cmdline.o --obj-$(CONFIG_VIDEO_NOMODESET) += nomodeset.o ++obj-$(CONFIG_VIDEO_CMDLINE) += cmdline.o nomodeset.o obj-$(CONFIG_HDMI) += hdmi.o obj-$(CONFIG_VT) += console/ diff --cc redhat/configs/common/generic/CONFIG_DRM_DEBUG_MM index 000000000000,000000000000..117f02c9e72a new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_DEBUG_MM @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_DEBUG_MM is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE index 000000000000,000000000000..f41d366c6b7e new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_I915_DP_TUNNEL index 000000000000,000000000000..fd15321b5596 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_I915_DP_TUNNEL @@@ -1,0 -1,0 +1,1 @@@ ++CONFIG_DRM_I915_DP_TUNNEL=y diff --cc redhat/configs/common/generic/CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE index 000000000000,000000000000..f18775160d7a new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_IMX8MP_HDMI_PVI index 000000000000,000000000000..a2b6a8b10206 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_IMX8MP_HDMI_PVI @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_IMX8MP_HDMI_PVI is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_MGAG200_IOBURST_WORKAROUND index 000000000000,000000000000..24b7b124437c new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_MGAG200_IOBURST_WORKAROUND @@@ -1,0 -1,0 +1,1 @@@ ++CONFIG_DRM_MGAG200_IOBURST_WORKAROUND=y diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A index 000000000000,000000000000..6d37b899099e new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_HIMAX_HX83112A index 000000000000,000000000000..e5411775710c new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_HIMAX_HX83112A @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_NOVATEK_NT36672E index 000000000000,000000000000..1511cd4623a8 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_NOVATEK_NT36672E @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set Commit list: commit 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commit fa68a34ec31b75915463435056493efa388f1b79 commit be4a2a81b6b90d1a47eaeaace4cc8e2cb57b96c7 commit 8d2c930735f850e5be6860aeb39b27ac73ca192f commit 06fbf84f46d20ca3d67f742de2a0a055fbdd2bec commit b61821bb32c5577272408e1b05e6a0879a64257f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-05-14 00:10:15 +00:00
gt/intel_gt_ccs_mode.o \
drm/i915/gt: Use the RPM config register to determine clk frequencies For many configuration details within RC6 and RPS we are programming intervals for the internal clocks. From gen11, these clocks are configuration via the RPM_CONFIG and so for convenience, we would like to convert to/from more natural units (ns). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200424162805.25920-2-chris@chris-wilson.co.uk
2020-04-24 16:28:05 +00:00
gt/intel_gt_clock_utils.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
gt/intel_gt_debugfs.o \
gt/intel_gt_engines_debugfs.o \
drm/i915: Extract general GT interrupt handlers i915_irq.c is large. It serves as the central dispatch and handler for all of our device interrupts. Lets break it up by pulling out the GT interrupt handlers. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190811210633.18417-1-chris@chris-wilson.co.uk
2019-08-11 21:06:33 +00:00
gt/intel_gt_irq.o \
Merge DRM changes from upstream v5.19..v6.0 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.0 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/hyperv/hyperv_drm_drv.c drivers/gpu/drm/mgag200/mgag200_mode.c Conflict resolution: Commit list: commit d10f7117aa43b0b0d1c4b878afafb6d151da441d commit 115fcf5899f7e0b0d3358a22a8cd76b1398642ee commit d8cb49d203556707ff4c3aa05032c4fc7c3ff1a2 commit 9d72b7e2d2ce3746950929a2c54171d183ea89f2 commit 94afc5382669c3a201c5817c47b57a879b6dabce commit aba5825439d7691343aa562dfeaf6616455bcb01 commit a9ec4fd004b84c26207a8cae41662c501c8a284b commit 537d9ed2f6c1dbfe8465365c2f74a855ffad5e6a commit ed3173077d3fa6fd085960aa6347ec30f532bf31 commit b07debc2a8ce7324c85479a28d145eaa05382286 commit 4ce08703a8c4be77b060aefd14eda272f50a45e4 commit 9975af040a04ba9aef33f3ef1ca4e8f04c7223dd commit dfc0312596561ac462308fae32130a0c580b7ac1 commit 37852141965d467a4ae118139b6eee266e7d953c commit 2af243444f9100639451b11d311982279e00cc16 commit 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83ca5fb40e758e0a0257bf4e3a1148dd52c6d0f2 commit a3aded135e84a581ba567c30ecddff47c8b6cfcf commit 541540b9045c2665d6736a77c776ac81d4225eec commit 153a97b4e3de713c05b6bd42d734a2f9eeaf7968 commit 91462afa42e6b8c5a148a44482c893f1800c513d commit 6643b3836f3908c4f77883b2fae72451e85cf3ca commit af81a9201e0112e9c4ca7258e32cd28baf19f31a commit 2f3f958602721c7915ddb1f2a0e8dc5031bc0151 commit 90df15124526176ff03c246362c196a047c8a39a commit bcecb6524881c54ded92f14a6cf2406d5c439637 commit c1c3f41ffb1bd262e40d68938af68c6ab53a41f8 commit b33139ee15352043123b81b32ca1a6a84340eb5d commit 04fa38cce6e02be4362cd889780d58ec275c4d26 commit 0fd85e89b5bf18447e56099a010ee5be5dc9f2b0 commit 414208e48963fdb136240d7f59c15e627832d288 Omitted-fix: 14773bfa70e6 ("mm: shrinkers: fix double kfree on shrinker name") Omitted-fix: 20529e260ff2 ("Revert "drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new"") Omitted-fix: 3024d95a4c52 ("bpf: Partially revert flexible-array member replacement") Omitted-fix: 3915f8bddefd ("drm: xlnx: add <linux/io.h> for readl/writel") Omitted-fix: 395d10ae4d29 ("drm/xlnx: Fix build failure due to missing include") Omitted-fix: 3f61631d47f1 ("take care to handle NULL ->proc_lseek()") Omitted-fix: 5e6723ef3fda ("drm/lcdif: Consistently use plain timings") Omitted-fix: 71c627c0a87a ("drm/lcdif: Clean up debug prints and comments") Omitted-fix: d395fb1999ab ("Revert "drm/amdgpu: move internal vram_mgr function into the C file"") Omitted-fix: ea19684afb54 ("drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers") Omitted-fix: f423fa1bc9fe ("drm/i915/gvt: Add missing vfio_unregister_group_dev() call") Omitted-fix: fcfd3e5fb2f0 ("drm/lcdif: Clean up headers") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:48:10 +00:00
gt/intel_gt_mcr.o \
drm/i915: Invert the GEM wakeref hierarchy In the current scheme, on submitting a request we take a single global GEM wakeref, which trickles down to wake up all GT power domains. This is undesirable as we would like to be able to localise our power management to the available power domains and to remove the global GEM operations from the heart of the driver. (The intent there is to push global GEM decisions to the boundary as used by the GEM user interface.) Now during request construction, each request is responsible via its logical context to acquire a wakeref on each power domain it intends to utilize. Currently, each request takes a wakeref on the engine(s) and the engines themselves take a chipset wakeref. This gives us a transition on each engine which we can extend if we want to insert more powermangement control (such as soft rc6). The global GEM operations that currently require a struct_mutex are reduced to listening to pm events from the chipset GT wakeref. As we reduce the struct_mutex requirement, these listeners should evaporate. Perhaps the biggest immediate change is that this removes the struct_mutex requirement around GT power management, allowing us greater flexibility in request construction. Another important knock-on effect, is that by tracking engine usage, we can insert a switch back to the kernel context on that engine immediately, avoiding any extra delay or inserting global synchronisation barriers. This makes tracking when an engine and its associated contexts are idle much easier -- important for when we forgo our assumed execution ordering and need idle barriers to unpin used contexts. In the process, it means we remove a large chunk of code whose only purpose was to switch back to the kernel context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-24 20:07:17 +00:00
gt/intel_gt_pm.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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commit aa464957f7e660abd554f2546a588f6533720e21 commit 78fed39af1af5d702089fe53076c524646e64997 commit a2fbfd517117157e99160ff1b39b171872dcba07 commit fc74881c28d314b10efac016ef49df4ff40b8b97 commit bf67014d6bda16a72deea11dbbff2a97c705ca92 commit 19e66d512e4182a0461530fa3159638e0f55d97e commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5 commit 7807bf28fe02a76bf112916c6b9194f282f5e43c commit 67f74302f45d5d862f22ced3297624e50ac352f0 commit 4d625a97a7e96be016382e3bb0a3cead05fec153 commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c commit d46f329a3f6048e04736e86cb13c880645048792 commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1 commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464 commit ebae8973884ee9ac703b3bfe34cabbb118b18538 commit 2eb82577a16d4c8eb31e4ed520649850bb95b223 commit d97e631af2db84c8c9d63abf68d487d0bb559e4c commit a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
gt/intel_gt_pm_debugfs.o \
drm/i915: Extract GT powermanagement interrupt handling i915_irq.c is large. It serves as the central dispatch and handler for all of our device interrupts. Pull out the GT pm interrupt handling (leaving the central dispatch) so that we can encapsulate the logic a little better. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190811142801.2460-1-chris@chris-wilson.co.uk
2019-08-11 14:28:00 +00:00
gt/intel_gt_pm_irq.o \
drm/i915: Move request runtime management onto gt Requests are run from the gt and are tided into the gt runtime power management, so pull the runtime request management under gt/ Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191004134015.13204-12-chris@chris-wilson.co.uk
2019-10-04 13:40:06 +00:00
gt/intel_gt_requests.o \
Merge DRM changes from upstream v5.18..v5.19 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.19 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/bridge/Kconfig drivers/gpu/drm/bridge/analogix/analogix_dp_core.c drivers/gpu/drm/bridge/chipone-icn6211.c drivers/gpu/drm/drm_edid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/drm_format_helper.c drivers/gpu/drm/i915/gt/intel_gsc.c drivers/gpu/drm/i915/gvt/gvt.h drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/i915_driver.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_gvt_mmio_table.c drivers/gpu/drm/mgag200/mgag200_mode.c drivers/gpu/drm/solomon/ssd130x.c drivers/gpu/drm/vmwgfx/vmwgfx_fb.c include/drm/i915_drm.h Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index d91dc8b0effc,30fe847c6664..193c7c83c70f --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -5,6 -5,8 +5,7 @@@ */ #include <linux/dma-resv.h> + #include <linux/highmem.h> -#include <linux/intel-iommu.h> #include <linux/sync_file.h> #include <linux/uaccess.h> Commit list: commit c6e7deb0f092616bd8cb19e8c436b212c64daaab commit 072ce4164f973bc762b25ce9a41636bffe75ab36 commit f8a005eb89720c913e59707d061a1b7e9c8b3358 commit 14ad15296d1fd067e54ad04d96056fe0aed61f2d commit 0225a90981c83408e9606b52a65edee1c6891106 commit 7ad9993b2368f2a861f335184cd2bb1909f13827 commit 772ba8d68515fb8d5414eb714a1d4d446903eb13 commit b4eb76d82a0ea92241f5079874a7aea10c5cc4ae commit 2ff5560e23c863b22afb7db01208a76d9f1d1046 commit 53581504a8e216d435f114a4f2596ad0dfd902fc commit cccc71b552a1040ad3d738d7ec95570801fb0bf6 commit 6c6465fc33c5679a418fb06ff582cd38e68eb5e2 commit c2393a1d8bd1a69ff74ee769fa5d36e4900d4fba commit 3dda9ee49ea5d332359ca372728ee13e570b7e04 commit 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90af0ca047f3049c4b46e902f432ad6ef1e2ded6 commit 1c46f3c0759116d70cb424fc227371a254c47b25 commit 7f5ec14a4e07a2a78fbde069709d5c8806882be2 commit a7a47a5dfa9a9692a41764ee9ab4054f12924a42 commit c653c591789b3acfa4bf6ae45d5af4f330e50a91 commit 0c09bc33aa8e9dc867300acaadc318c2f0d85a1e commit 66cee9097e2b74ff3c8cc040ce5717c521a0c3fa commit 9d928d9b78beec5d4b8afde9c144919b979685f2 commit ce156c8a1811c96a243590abd0e9b5a3b72c1f3a commit e65c6a46df94c8d76ea1129eb2d4564670c6f214 Omitted-fix: 0b752df77633 ("drm/rockchip: Fix Kconfig dependencies for display-port encoders") Omitted-fix: 16c8d76abe83 ("dt-bindings: display: bridge: ldb: Fill in reg property") Omitted-fix: 30bdc36b8c77 ("drm/imx/dcss: get rid of HPD warning message") Omitted-fix: 91954c6c904b ("drm/amd/display: Fix mutex lock in dcn10") Omitted-fix: 920169041baa ("drm/sun4i: dw-hdmi: Fix ddc-en GPIO consumer conflict") Omitted-fix: be273ecfbe8a ("drm/vc4: Use newer fence API properly to fix build errors") Omitted-fix: d9927abb4594 ("Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:27:09 +00:00
gt/intel_gt_sysfs.o \
gt/intel_gt_sysfs_pm.o \
drm/i915/gtt: split up i915_gem_gtt Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
2020-01-07 13:40:09 +00:00
gt/intel_gtt.o \
drm/i915: Extract GT ring management Although the ring management is much smaller compared to the other GT power management functions, continue the theme of extracting it out of the huge intel_pm.c for maintenance. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191020184139.9145-1-chris@chris-wilson.co.uk
2019-10-20 18:41:39 +00:00
gt/intel_llc.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
gt/intel_lrc.o \
Merge DRM changes from upstream v5.14..v5.15 This commit was generated using: rhdrm-merge-drm v5.15 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: Makefile drivers/gpu/drm/drm_gem_atomic_helper.c drivers/gpu/drm/drm_gem_framebuffer_helper.c drivers/gpu/drm/gud/gud_pipe.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c include/drm/drm_gem_atomic_helper.h include/drm/drm_gem_framebuffer_helper.h Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment } } #endif /* CONFIG_DMA_API_DEBUG */ - return sg_table; } -EXPORT_SYMBOL_GPL(dma_buf_map_attachment); +EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF); /** * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd goto free; if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) - adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); } +#ifdef CONFIG_X86_MCE_AMD + if ((adev->asic_type == CHIP_ALDEBARAN) && + (adev->gmc.xgmi.connected_to_cpu)) + amdgpu_register_bad_pages_mca_notifier(); +#endif + return 0; free: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) #define I915_BO_ALLOC_VOLATILE BIT(1) - #define I915_BO_ALLOC_STRUCT_PAGE BIT(2) - #define I915_BO_ALLOC_CPU_CLEAR BIT(3) + #define I915_BO_ALLOC_CPU_CLEAR BIT(2) + #define I915_BO_ALLOC_USER BIT(3) #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ - I915_BO_ALLOC_STRUCT_PAGE | \ - I915_BO_ALLOC_CPU_CLEAR) + I915_BO_ALLOC_CPU_CLEAR | \ + I915_BO_ALLOC_USER) #define I915_BO_READONLY BIT(4) #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ +#define I915_BO_WAS_BOUND_BIT 6 - /* - * Is the object to be mapped as read-only to the GPU - * Only honoured if hardware has relevant pte bit + /** + * @mem_flags - Mutable placement-related flags + * + * These are flags that indicate specifics of the memory region + * the object is currently in. As such they are only stable + * either under the object lock or if the object is pinned. + */ + unsigned int mem_flags; + #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */ + #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */ + /** + * @cache_level: The desired GTT caching level. + * + * See enum i915_cache_level for possible values, along with what + * each does. */ unsigned int cache_level:3; - unsigned int cache_coherent:2; + /** + * @cache_coherent: + * + * Track whether the pages are coherent with the GPU if reading or + * writing through the CPU caches. The largely depends on the + * @cache_level setting. + * + * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom + * platforms, coherency must be explicitly requested with some special + * GTT caching bits(see enum i915_cache_level). When enabling coherency + * it does come at a performance and power cost on such platforms. On + * the flip side the kernel does not need to manually flush any buffers + * which need to be coherent with the GPU, if the object is not coherent + * i.e @cache_coherent is zero. + * + * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory + * access will automatically snoop the CPU caches(even with CACHE_NONE). + * The one exception is when dealing with the display engine, like with + * scanout surfaces. To handle this the kernel will always flush the + * surface out of the CPU caches when preparing it for scanout. Also + * note that since scanout surfaces are only ever read by the display + * engine we only need to care about flushing any writes through the CPU + * cache, reads on the other hand will always be coherent. + * + * Something strange here is why @cache_coherent is not a simple + * boolean, i.e coherent vs non-coherent. The reasoning for this is back + * to the display engine not being fully coherent. As a result scanout + * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT. + * In the case of seeing I915_CACHE_NONE the kernel makes the assumption + * that this is likely a scanout surface, and will set @cache_coherent + * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared + * LLC. The kernel uses this to always flush writes through the CPU + * cache as early as possible, where it can, in effect keeping + * @cache_dirty clean, so we can potentially avoid stalling when + * flushing the surface just before doing the scanout. This does mean + * we might unnecessarily flush non-scanout objects in some places, but + * the default assumption is that all normal objects should be using + * I915_CACHE_LLC, at least on platforms with the shared LLC. + * + * Supported values: + * + * I915_BO_CACHE_COHERENT_FOR_READ: + * + * On shared LLC platforms, we use this for special scanout surfaces, + * where the display engine is not coherent with the CPU cache. As such + * we need to ensure we flush any writes before doing the scanout. As an + * optimisation we try to flush any writes as early as possible to avoid + * stalling later. + * + * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC + * platforms, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ + * + * While for normal objects that are fully coherent, including special + * scanout surfaces marked as I915_CACHE_WT, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ | + * I915_BO_CACHE_COHERENT_FOR_WRITE + * + * And then for objects that are not coherent at all we use: + * + * cache_coherent = 0 + * + * I915_BO_CACHE_COHERENT_FOR_WRITE: + * + * When writing through the CPU cache, the GPU is still coherent. Note + * that this also implies I915_BO_CACHE_COHERENT_FOR_READ. + */ #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) + unsigned int cache_coherent:2; + + /** + * @cache_dirty: + * + * Track if we are we dirty with writes through the CPU cache for this + * object. As a result reading directly from main memory might yield + * stale data. + * + * This also ties into whether the kernel is tracking the object as + * coherent with the GPU, as per @cache_coherent, as it determines if + * flushing might be needed at various points. + * + * Another part of @cache_dirty is managing flushing when first + * acquiring the pages for system memory, at this point the pages are + * considered foreign, so the default assumption is that the cache is + * dirty, for example the page zeroing done by the kernel might leave + * writes though the CPU cache, or swapping-in, while the actual data in + * main memory is potentially stale. Note that this is a potential + * security issue when dealing with userspace objects and zeroing. Now, + * whether we actually need apply the big sledgehammer of flushing all + * the pages on acquire depends on if @cache_coherent is marked as + * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent + * for both reads and writes though the CPU cache. + * + * Note that on shared LLC platforms we still apply the heavy flush for + * I915_CACHE_NONE objects, under the assumption that this is going to + * be used for scanout. + * + * Update: On some hardware there is now also the 'Bypass LLC' MOCS + * entry, which defeats our @cache_coherent tracking, since userspace + * can freely bypass the CPU cache when touching the pages with the GPU, + * where the kernel is completely unaware. On such platform we need + * apply the sledgehammer-on-acquire regardless of the @cache_coherent. + */ unsigned int cache_dirty:1; /** diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c index b9aaf640f372,6109cd9e3399..e7efd9ede8e4 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de struct nvkm_client *client; struct nvkm_device *device; - drm_dev_unregister(dev); + drm_dev_unplug(dev); - dev->irq_enabled = false; client = nvxx_client(&drm->client.base); device = nvkm_device_find(client->device); diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c index f9d399ea628d,e50fb82a3030..2aceac7856e2 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c @@@ -28,9 -28,10 +28,10 @@@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/mem_encrypt.h> +#include <linux/cc_platform.h> #include <asm/hypervisor.h> + #include <drm/drm_ioctl.h> #include "vmwgfx_drv.h" #include "vmwgfx_msg_x86.h" @@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st unsigned long msg_len = strlen(msg); /* HB port can't access encrypted memory. */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_high; + u32 channel_id = (channel->channel_id << 16); si = (uintptr_t) msg; di = channel->cookie_low; @@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str unsigned long si, di, eax, ebx, ecx, edx; /* HB port can't access encrypted memory */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_low; + u32 channel_id = (channel->channel_id << 16); si = channel->cookie_high; di = (uintptr_t) reply; Commit list: commit 241a9e233e7cf1001d09426c9fc520768f8961bf commit 4154fa0e2688118ba3dbc67aa834435463f9ea68 commit 3faea9939a3d1eb5a40f3f6100c24792865b6445 commit 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b253c3026c29d4231099d3cf8d984d25787793af commit d1d94b0129dccd226784633c60b7df90e8a051b5 commit a14bc107edd0c108bda2245e50daa22f91c95d20 commit 59be177a909ac320e5f4b2a461ac09e20f35b2d8 commit 5afa7898ab7a0ec9c28556a91df714bf3c2f725e commit c21b105380cf86e829c68586ca1315cfc253ad8c commit c938aed88f8259dc913b717a32319101c66e87a9 commit 672437486ee9da3ed0e774937e6d0dd570921b39 commit 4835ea6c173a8d8dfbfdbb21c4cd987d12681610 commit dd8cb18906d97b2916fde42d32d915ae363c7e55 commit 2ef8ea23942f4c2569930c34e7689a0cb1b232cc commit 53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67 commit 772970620a839141835eaf2bc507d957b10adcca commit 3e4c31e8f70251732529a10934355084c7fab0ac commit a79f40cccd4644c32f6d5ae1ccf091a262e1dc57 commit 13047a092c6d3f23b7d684b5b3fe46b2b50423b9 commit 982f8ad666a1123028a077b6b009871a0dc9df26 commit 004d2719806fb8e355c1bccd538e82c04319d391 commit 74056092ff415e7e20ce2544689b32ee811c4f0b commit 0db55f9a1bafbe3dac750ea669de9134922389b5 commit def0c3697287f6e85d5ac68b21302966c95474f9 commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7 commit fcf918ffd3b35e288097036c04af7446b2c6f2f1 commit 9761ffb8f1090289b908590039e2c363cc35cf45 commit 6e6f96630805874fa80b0067e1a57aafc06225f6 commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2 commit defbbcd99fa68cb7feed453662048baa87e9a441 commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5 commit 54149d13f369e1ab02f36b91feee02069184c1d8 commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e commit 19928833e8f8fa5ee687c451437ce674f19d6c09 commit 79516af3497a5b89acb09f4a644f61d6c69e5f16 commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626 commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
gt/intel_migrate.o \
drm/i915/gt: Split intel_ring_submission Split the legacy submission backend from the common CS ring buffer handling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024100344.5041-1-chris@chris-wilson.co.uk
2019-10-24 10:03:44 +00:00
gt/intel_mocs.o \
drm/i915/gtt: split up i915_gem_gtt Attempt to split i915_gem_gtt.[ch] into more manageable chunks. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200107134009.3255354-1-chris@chris-wilson.co.uk
2020-01-07 13:40:09 +00:00
gt/intel_ppgtt.o \
drm/i915: Extract GT render sleep (rc6) management Continuing the theme of breaking intel_pm.c up in a reasonable chunk of powermanagement utilities, pull out the rc6 setup into its GT handler. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190919143840.20384-1-andi.shyti@intel.com Link: https://patchwork.freedesktop.org/patch/msgid/20190927110849.28734-1-chris@chris-wilson.co.uk
2019-09-27 11:08:49 +00:00
gt/intel_rc6.o \
drm/i915: move region_lmem under gt Device local-memory should be thought of as part the GT, which means it should also sit under gt/. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210112164300.356524-1-matthew.auld@intel.com
2021-01-12 16:43:00 +00:00
gt/intel_region_lmem.o \
drm/i915: Move the renderstate setup under gt/ The render state is used to initialise the default RCS context, and only used during early setup from within the gt code. As such, it makes a good candidate for placing within gt/, even if it is not yet entirely clean of our GEM heritage. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190704091925.7391-1-chris@chris-wilson.co.uk
2019-07-04 09:19:25 +00:00
gt/intel_renderstate.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
gt/intel_reset.o \
drm/i915/gt: Split intel_ring_submission Split the legacy submission backend from the common CS ring buffer handling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024100344.5041-1-chris@chris-wilson.co.uk
2019-10-24 10:03:44 +00:00
gt/intel_ring.o \
gt/intel_ring_submission.o \
drm/i915: Extract GT render power state management i915_irq.c is large. One reason for this is that has a large chunk of the GT render power management stashed away in it. Extract that logic out of i915_irq.c and intel_pm.c and put it under one roof. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-1-chris@chris-wilson.co.uk
2019-10-24 21:16:41 +00:00
gt/intel_rps.o \
Merge DRM changes from upstream v6.0.8..v6.1 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.1 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c drivers/gpu/drm/amd/amdgpu/amdgpu_job.c drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/i915/display/intel_display.c drivers/gpu/drm/i915/gt/intel_gt_sysfs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_guc_log.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/mgag200/mgag200_pll.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index ecb8db731081,253ea6b159df..6ebed4d58ced --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@@ -162,6 -162,7 +162,8 @@@ #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) ++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) + #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque */ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - uint8_t i; - int j; ++ + int i, j; struct dc_stream_state *stream = NULL; struct dc_plane_state *plane = NULL; uint32_t cursor_size = 0; @@@ -237,24 -236,24 +237,27 @@@ mblk_width = DCN3_2_MBLK_WIDTH; mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; ++ /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - * FLOOR(vp_x_start, blk_width) * * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + - pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + + pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); ++ /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - * FLOOR(vp_y_start, blk_height) * * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c */ mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + - pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) + + pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); ++ num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); diff --cc drivers/gpu/drm/ast/ast_mode.c index b93181a42048,1bc0220e6783..ae5a4cce972f --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@@ -42,9 -40,8 +42,8 @@@ #include <drm/drm_fourcc.h> #include <drm/drm_gem_atomic_helper.h> #include <drm/drm_gem_framebuffer_helper.h> -#include <drm/drm_gem_vram_helper.h> +#include <drm/drm_gem_shmem_helper.h> #include <drm/drm_managed.h> - #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> @@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_crtc_state *crtc_state; - struct ast_crtc_state *ast_crtc_state; + struct drm_device *dev = plane->dev; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_crtc_state *new_crtc_state = NULL; + struct ast_crtc_state *new_ast_crtc_state; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, false, true); - if (ret) + if (ret) { return ret; + } else if (!new_plane_state->visible) { + if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */ + return -EINVAL; + else + return 0; + } - if (!new_plane_state->visible) - return 0; - - ast_crtc_state = to_ast_crtc_state(crtc_state); + new_ast_crtc_state = to_ast_crtc_state(new_crtc_state); - ast_crtc_state->format = new_plane_state->fb->format; + new_ast_crtc_state->format = new_plane_state->fb->format; return 0; } @@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_framebuffer *fb = new_plane_state->fb; - struct drm_crtc_state *crtc_state; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_framebuffer *new_fb = new_plane_state->fb; + struct drm_crtc_state *new_crtc_state = NULL; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, true, true); - if (ret) + if (ret || !new_plane_state->visible) return ret; - if (!new_plane_state->visible) - return 0; - - if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) + if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT) return -EINVAL; return 0; diff --cc drivers/gpu/drm/i915/display/intel_display.c index bd629f2da6eb,de77054195c6..d3bfa2a675b8 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9 else if (DISPLAY_VER(i915) >= 11) pipes = BIT(PIPE_B) | BIT(PIPE_C); else ++ pipes = 0; - return pipes & RUNTIME_INFO(i915)->pipe_mask; + return pipes & INTEL_INFO(i915)->display.pipe_mask; } static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj return !strncmp(kobj->name, "gt", 2); } - static struct intel_gt *kobj_to_gt(struct kobject *kobj) - { - return container_of(kobj, struct intel_gt, sysfs_gt); - } - -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name) { - struct kobject *kobj = &dev->kobj; - /* * We are interested at knowing from where the interface * has been called, whether it's called from gt/ or from diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h index 6bee2c6a894d,6232923a420d..c3a123faee98 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h @@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g struct kobject *dir, const char *name); + static inline struct intel_gt *kobj_to_gt(struct kobject *kobj) + { + return container_of(kobj, struct intel_gt, sysfs_gt); + } + void intel_gt_sysfs_register(struct intel_gt *gt); void intel_gt_sysfs_unregister(struct intel_gt *gt); -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name); #endif /* SYSFS_GT_H */ diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe NULL }; + static ssize_t + default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.min_freq); + } + + static struct kobj_attribute default_min_freq_mhz = + __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL); + + static ssize_t + default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.max_freq); + } + + static struct kobj_attribute default_max_freq_mhz = + __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL); + + static const struct attribute * const rps_defaults_attrs[] = { + &default_min_freq_mhz.attr, + &default_max_freq_mhz.attr, + NULL + }; + -static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj, - const struct attribute * const *attrs) +static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj) { + const struct attribute * const *attrs; + struct attribute *vlv_attr; int ret; if (GRAPHICS_VER(gt->i915) < 6) diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 070cec4ff8a4,3955292483a6..d3ac73c3559f --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc /* hsdes: 1809175790 */ if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine->gt, + cs, GEN12_GFX_CCS_AUX_NV); + + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 1b6479b5bd32,a821e3d405db..21cd1a4e1823 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_ if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14013392000:dg2_g11 */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); + } - /* Wa_16011620976:dg2_g11 */ - wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); + } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14012419201:dg2 */ diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 844dee09a321,1db59eeb34db..1ac0e66d39e5 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i return 0; } +struct scheduling_policy { + /* internal data */ + u32 max_words, num_words; + u32 count; + /* API data */ + struct guc_update_scheduling_policy h2g; +}; + +static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy) +{ + u32 *start = (void *)&policy->h2g; + u32 *end = policy->h2g.data + policy->num_words; + size_t delta = end - start; + + return delta; +} + +static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy) +{ + policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV; + policy->max_words = ARRAY_SIZE(policy->h2g.data); + policy->num_words = 0; + policy->count = 0; + + return policy; +} + +static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy, + u32 action, u32 *data, u32 len) +{ + u32 *klv_ptr = policy->h2g.data + policy->num_words; + + GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words); + *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) | + FIELD_PREP(GUC_KLV_0_LEN, len); + memcpy(klv_ptr, data, sizeof(u32) * len); + policy->num_words += 1 + len; + policy->count++; +} + +static int __guc_action_set_scheduling_policies(struct intel_guc *guc, + struct scheduling_policy *policy) +{ + int ret; + + ret = intel_guc_send(guc, (u32 *)&policy->h2g, + __guc_scheduling_policy_action_size(policy)); + if (ret < 0) + return ret; + + if (ret != policy->count) { + drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!", + ret, policy->count); + if (ret > policy->count) + return -EPROTO; + } + + return 0; +} + +static int guc_init_global_schedule_policy(struct intel_guc *guc) +{ + struct scheduling_policy policy; + struct intel_gt *gt = guc_to_gt(guc); + intel_wakeref_t wakeref; + int ret = 0; + + if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0)) + return 0; + + __guc_scheduling_policy_start_klv(&policy); + + with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref) { + u32 yield[] = { + GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION, + GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO, + }; + + __guc_scheduling_policy_add_klv(&policy, + GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD, + yield, ARRAY_SIZE(yield)); + + ret = __guc_action_set_scheduling_policies(guc, &policy); + if (ret) + i915_probe_error(gt->i915, + "Failed to configure global scheduling policies: %pe!\n", + ERR_PTR(ret)); + } + + return ret; +} + void intel_guc_submission_enable(struct intel_guc *guc) { + struct intel_gt *gt = guc_to_gt(guc); + + /* Enable and route to GuC */ + if (GRAPHICS_VER(gt->i915) >= 12) + intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, + GUC_SEM_INTR_ROUTE_TO_GUC | + GUC_SEM_INTR_ENABLE_ALL); + guc_init_lrc_mapping(guc); guc_init_engine_stats(guc); + guc_init_global_schedule_policy(guc); } void intel_guc_submission_disable(struct intel_guc *guc) diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index fb309ae43001,b91ad4aede1f..24aac2f32dd1 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@@ -339,6 -347,6 +347,7 @@@ bad fw_blobs[i].blob.patch); uc_fw->file_selected.path = NULL; ++ } } } diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c index 098955526b68,c481daa4bbce..38a0ba4a1b3f --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi st7701->dsi = dsi; st7701->desc = desc; - return mipi_dsi_attach(dsi); + ret = mipi_dsi_attach(dsi); + if (ret) + goto err_attach; + + return 0; + +err_attach: + drm_panel_remove(&st7701->panel); + return ret; } - static int st7701_dsi_remove(struct mipi_dsi_device *dsi) + static void st7701_dsi_remove(struct mipi_dsi_device *dsi) { struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); Commit list: commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f commit 6dc548745d5b5102e3c53dc5097296ac270b6c69 commit 859161b952a453b86362f168fadef72a8ba31a05 commit d72ac4bbf4cc8f6b50526ce400861f176659884f commit 1fd452c403ca2cd9dcbd8465f9f72be52e15ac1a commit 79abca2b399009eb8d12c652d0f0f7a9c7a06289 commit 96dc635d5538055cb6ccd7b6e9290dfcfc385f97 commit dc1dc76bd9a48c6aba3efae5eadb9a884043966e commit 356d2c8e76ebb1134a0685ce4b923d8201337475 commit 4c59b0805e9bf873fd3f5dca4fc53d8c220e39b4 commit e5bd7e3e4a68f0befe53f59954b25eec9a792d60 commit ba71593217b5b03c9e3385b268ff8613a71fc6ce commit 0a2486f85e0cfa6439116abb9078ab888a619746 commit 8aba4d30520ed656065eb36f0628109bdea385ee commit d093100b425df6fe400881f2e62c3f0be7bf18cf commit b92db7e4fe740daab858366faff1f992d53d3ff4 commit 0c05fcd3b45d6769c496fc6e2b88d18fc78ebe11 commit a6aa679a70e9d8fa4ad3f519c060db9bb186e21c commit 6de745238aa30529778a26622a430dfcb171b089 commit d395fb1999abb7eaa3fb5fd2107cae0f1e41e6d0 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commit a26a54fbe32b564ff868710d59fbe1a387a2cc7c commit f2e1aa267f12b82e03927d1e918d2844ddd3eea5 commit 3cb93f390453cde4d6afda1587aaa00e75e09617 commit a6e1775da04ab042bc9e2e42399fa25714c253da commit 602ad43c3cd8f15cbb25ce9bb494129edb2024ed commit ecb41b71ef90cf4741bcc3286b769dda746b67e6 commit 9e2c5c651a63baaa39005070481d39dcf5b0893a commit b65a648865c4a1e717c4f56f5025546b9553189a commit e57702069b26b8601a33fdc0c9bbe40c6bb9c72f commit ed14d225cc7c842f6d4d5a3009f71a44f5852d09 commit 2f3830544a89af2e72e7fd3d6ca44dd9cffec197 commit 3c1ea6a5f4f55d4e376675dda16945eb5d9bb4de commit a8899b8728013c7b2456f0bfa20e5fea85ee0fd1 commit 12b8b046e4c9de40fa59b6f067d6826f4e688f68 commit 8c115864501fc09932cdfec53d9ec1cde82b4a28 commit 04aa64375f48a5d430b5550d9271f8428883e550 commit 6f6cb1714365a07dbc66851879538df9f6969288 commit d3d6b1bf85aefe0ebc0624574b3bb62f0693914c commit 9a8cc8cabc1e351614fd7f9e774757a5143b6fe8 commit c082fbd687ad70a92e0a8be486a7555a66f03079 commit bdaa78c6aa861f0e8c612a0b2272423d92f0071c commit c290db013742e98fe5b64073bc2dd8c8a2ac9e4c commit 24013314be6ee4ee456114a671e9fa3461323de8 commit 09bf649a74573cb596e211418a4f8008f265c5a9 commit 6e90293618ed476d6b11f82ce724efbb9e9a071b commit bc21fe9a5844c5bc8f7ec319b11d2671a94eb867 commit aeffc8fb2174f017a10df114bc312f899904dc68 commit c4252650a8c4770b669398fe7270ed8c94fc0eba Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
gt/intel_sa_media.o \
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
gt/intel_sseu.o \
drm/i915: Move sseu debugfs under gt/ In line with what happened for other gt-related features, move the sseu debugfs files under gt/. The sseu_status debugfs has also been kept at the top level as we do have tests that use it; it will be removed once we teach the tests to look into the new path. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-10-daniele.ceraolospurio@intel.com
2020-07-08 00:39:52 +00:00
gt/intel_sseu_debugfs.o \
drm/i915: Rename i915_timeline to intel_timeline and move under gt Move all timeline code under gt and rename to intel_gt prefix. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-32-tvrtko.ursulin@linux.intel.com
2019-06-21 07:08:10 +00:00
gt/intel_timeline.o \
Merge DRM changes from upstream v6.5..v6.6 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.6 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/host1x/bus.c Conflict resolution: diff --cc drivers/gpu/drm/Makefile index c4d29229527d,7fba2a3f29e8..57cb5b063510 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@@ -194,4 -197,8 +197,5 @@@ obj-y += gud obj-$(CONFIG_DRM_HYPERV) += hyperv/ obj-y += solomon/ obj-$(CONFIG_DRM_SPRD) += sprd/ + obj-$(CONFIG_DRM_LOONGSON) += loongson/ -# Enable shims for the RHEL DRM backport -subdir-ccflags-y += -DRH_DRM_BACKPORT -drm-y += drm_backport.o diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 9cc33c117883,ba9e07fc2b57..d50876a68951 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -310,21 -310,10 +310,21 @@@ void intel_huc_init_early(struct intel_ huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); - huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; - huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS(MTL_GSC_HECI1_BASE, 5); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI1_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI1_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/tegra/nvdec.c index d150cbc576c3,4860790666af..6beab3756667 --- a/drivers/gpu/drm/tegra/nvdec.c +++ b/drivers/gpu/drm/tegra/nvdec.c @@@ -8,10 -8,9 +8,8 @@@ #include <linux/dma-mapping.h> #include <linux/host1x.h> #include <linux/iommu.h> -#include <linux/iopoll.h> #include <linux/module.h> #include <linux/of.h> - #include <linux/of_device.h> - #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> diff --cc drivers/gpu/host1x/bus.c index 966c243aa448,84d042796d2e..dbbda6813507 --- a/drivers/gpu/host1x/bus.c +++ b/drivers/gpu/host1x/bus.c @@@ -338,32 -338,15 +338,15 @@@ static int host1x_device_match(struct d return strcmp(dev_name(dev), drv->name) == 0; } + /* + * Note that this is really only needed for backwards compatibility + * with libdrm, which parses this information from sysfs and will + * fail if it can't find the OF_FULLNAME, specifically. + */ -static int host1x_device_uevent(const struct device *dev, +static int host1x_device_uevent(struct device *dev, struct kobj_uevent_env *env) { - struct device_node *np = dev->parent->of_node; - unsigned int count = 0; - struct property *p; - const char *compat; - - /* - * This duplicates most of of_device_uevent(), but the latter cannot - * be called from modules and operates on dev->of_node, which is not - * available in this case. - * - * Note that this is really only needed for backwards compatibility - * with libdrm, which parses this information from sysfs and will - * fail if it can't find the OF_FULLNAME, specifically. - */ - add_uevent_var(env, "OF_NAME=%pOFn", np); - add_uevent_var(env, "OF_FULLNAME=%pOF", np); - - of_property_for_each_string(np, "compatible", p, compat) { - add_uevent_var(env, "OF_COMPATIBLE_%u=%s", count, compat); - count++; - } - - add_uevent_var(env, "OF_COMPATIBLE_N=%u", count); + of_device_uevent(dev->parent, env); return 0; } Commit list: commit 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commit 280bd84f0743f95849dbaadb12e9c0e532398d8d commit d3df66fd98557c25856860b7d9c3b8b93d449f0a commit 4984fc578a911f3146965f4086d0a219a9806002 commit cba94bbcff08d209710dd7bdc139caad675a6f8d commit 4e6c38c38723a954b85aa9ee62603bb4a37acbb4 commit 78cc55e0b64c820673a796635daf82c7eadfe152 commit 4cbed7702eb775cca22fff6827a549092cb59f61 commit 64ffd2f1d00c6235dabe9704bbb0d9ce3e28147f commit 6366ffa6edd832de870aaef184d5949a2e09c0c2 commit 5679dd241bbf36492d8fcddb99af48b22a5f99ec commit 44117828ed5c129a8146585e81262c0025daa50f Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-10-30 05:31:55 +00:00
gt/intel_tlb.o \
Merge DRM changes from upstream v6.1..v6.2 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.2 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/dma-buf/dma-buf.c drivers/gpu/drm/amd/amdgpu/mes_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c drivers/gpu/drm/ast/ast_drv.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/selftest_slpc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_huc.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/pxp/intel_pxp_huc.c drivers/gpu/drm/i915/pxp/intel_pxp_tee.c drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c drivers/gpu/drm/vmwgfx/vmwgfx_kms.c Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st init_waitqueue_head(&dmabuf->poll); dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll; dmabuf->cb_in.active = dmabuf->cb_out.active = 0; + INIT_LIST_HEAD(&dmabuf->attachments); if (!resv) { - resv = (struct dma_resv *)&dmabuf[1]; - dma_resv_init(resv); + dmabuf->resv = (struct dma_resv *)&dmabuf[1]; + dma_resv_init(dmabuf->resv); + } else { + dmabuf->resv = resv; } - dmabuf->resv = resv; - file = dma_buf_getfile(dmabuf, exp_info->flags); - if (IS_ERR(file)) { - ret = PTR_ERR(file); + ret = dma_buf_stats_setup(dmabuf, file); + if (ret) goto err_dmabuf; - } + file->f_mode |= FMODE_LSEEK; + file->private_data = dmabuf; + file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); mutex_unlock(&db_list.lock); diff --cc drivers/gpu/drm/bridge/ite-it6505.c index 99123eec4551,21a9b8422bda..c13fb0bc6260 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_ DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev)); debugfs_init(it6505); + pm_runtime_enable(dev); + + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->bridge.funcs = &it6505_bridge_funcs; it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 21cd1a4e1823,a0740308555d..bf68f2330dd9 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); /* Wa_18018781329:dg2,pvc */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + } } static void diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 4d1cc383b681,410905da8e97..e8d1bd04d2a2 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -291,16 -350,17 +361,55 @@@ out } void intel_huc_fini(struct intel_huc *huc) + { + /* + * the fence is initialized in init_early, so we need to clean it up + * even if HuC loading is off. + */ + delayed_huc_load_fini(huc); + + if (intel_uc_fw_is_loadable(&huc->fw)) + intel_uc_fw_fini(&huc->fw); + } + ++void intel_huc_suspend(struct intel_huc *huc) +{ + if (!intel_uc_fw_is_loadable(&huc->fw)) + return; + ++ /* ++ * in the unlikely case that we're suspending before the GSC has ++ * completed its loading sequence, just stop waiting. We'll restart ++ * on resume. ++ */ + delayed_huc_load_complete(huc); ++} + - i915_sw_fence_fini(&huc->delayed_load.fence); - intel_uc_fw_fini(&huc->fw); ++int intel_huc_wait_for_auth_complete(struct intel_huc *huc) ++{ ++ struct intel_gt *gt = huc_to_gt(huc); ++ int ret; ++ ++ ret = __intel_wait_for_register(gt->uncore, ++ huc->status.reg, ++ huc->status.mask, ++ huc->status.value, ++ 2, 50, NULL); ++ ++ /* mark the load process as complete even if the wait failed */ ++ delayed_huc_load_complete(huc); ++ ++ if (ret) { ++ drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret); ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); ++ return ret; ++ } ++ ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); ++ drm_info(&gt->i915->drm, "HuC authenticated\n"); ++ return 0; +} + void intel_huc_suspend(struct intel_huc *huc) { if (!intel_uc_fw_is_loadable(&huc->fw)) Commit list: commit 78a033433a5ae4fee85511ee075bc9a48312c79e commit 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commit 8f32378986218812083b127da5ba42d48297d7c4 commit 2a00299e7447395d0898e7c6214817c06a61a8e8 commit a2a04b515562bbb040e8ae3decae8c1e9ef05327 commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
gt/intel_wopcm.o \
drm/i915/gt: Expose engine properties via sysfs Preliminary stub to add engines underneath /sys/class/drm/cardN/, so that we can expose properties on each engine to the sysadmin. To start with we have basic analogues of the i915_query ioctl so that we can pretty print engine discovery from the shell, and flesh out the directory structure. Later we will add writeable sysadmin properties such as per-engine timeout controls. An example tree of the engine properties on Braswell: /sys/class/drm/card0 └── engine    ├── bcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    ├── rcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    ├── vcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    └── vecs0       ├── capabilities    ├── class    ├── instance       ├── known_capabilities    └── name v2: Include stringified capabilities v3: Include all known capabilities for futureproofing. v4: Combine the two caps loops into one v5: Hide underneath Kconfig.unstable for wider discussion Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Tested-by: Steve Carbonari <steven.carbonari@intel.com> Reviewed-by: Steve Carbonari <steven.carbonari@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200228131716.3243616-1-chris@chris-wilson.co.uk
2020-02-28 13:17:10 +00:00
gt/intel_workarounds.o \
drm/i915/gt: Keep a no-frills swappable copy of the default context state We need to keep the default context state around to instantiate new contexts (aka golden rendercontext), and we also keep it pinned while the engine is active so that we can quickly reset a hanging context. However, the default contexts are large enough to merit keeping in swappable memory as opposed to kernel memory, so we store them inside shmemfs. Currently, we use the normal GEM objects to create the default context image, but we can throw away all but the shmemfs file. This greatly simplifies the tricky power management code which wants to run underneath the normal GT locking, and we definitely do not want to use any high level objects that may appear to recurse back into the GT. Though perhaps the primary advantage of the complex GEM object is that we aggressively cache the mapping, but here we are recreating the vm_area everytime time we unpark. At the worst, we add a lightweight cache, but first find a microbenchmark that is impacted. Having started to create some utility functions to make working with shmemfs objects easier, we can start putting them to wider use, where GEM objects are overkill, such as storing persistent error state. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429172429.6054-1-chris@chris-wilson.co.uk
2020-04-29 17:24:29 +00:00
gt/shmem_utils.o \
drm/i915/gt: Expose engine properties via sysfs Preliminary stub to add engines underneath /sys/class/drm/cardN/, so that we can expose properties on each engine to the sysadmin. To start with we have basic analogues of the i915_query ioctl so that we can pretty print engine discovery from the shell, and flesh out the directory structure. Later we will add writeable sysadmin properties such as per-engine timeout controls. An example tree of the engine properties on Braswell: /sys/class/drm/card0 └── engine    ├── bcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    ├── rcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    ├── vcs0    │   ├── capabilities    │   ├── class    │   ├── instance    │   ├── known_capabilities    │   └── name    └── vecs0       ├── capabilities    ├── class    ├── instance       ├── known_capabilities    └── name v2: Include stringified capabilities v3: Include all known capabilities for futureproofing. v4: Combine the two caps loops into one v5: Hide underneath Kconfig.unstable for wider discussion Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Tested-by: Steve Carbonari <steven.carbonari@intel.com> Reviewed-by: Steve Carbonari <steven.carbonari@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200228131716.3243616-1-chris@chris-wilson.co.uk
2020-02-28 13:17:10 +00:00
gt/sysfs_engines.o
Merge DRM changes from upstream v6.1..v6.2 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.2 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/dma-buf/dma-buf.c drivers/gpu/drm/amd/amdgpu/mes_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c drivers/gpu/drm/ast/ast_drv.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/selftest_slpc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_huc.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/pxp/intel_pxp_huc.c drivers/gpu/drm/i915/pxp/intel_pxp_tee.c drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c drivers/gpu/drm/vmwgfx/vmwgfx_kms.c Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st init_waitqueue_head(&dmabuf->poll); dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll; dmabuf->cb_in.active = dmabuf->cb_out.active = 0; + INIT_LIST_HEAD(&dmabuf->attachments); if (!resv) { - resv = (struct dma_resv *)&dmabuf[1]; - dma_resv_init(resv); + dmabuf->resv = (struct dma_resv *)&dmabuf[1]; + dma_resv_init(dmabuf->resv); + } else { + dmabuf->resv = resv; } - dmabuf->resv = resv; - file = dma_buf_getfile(dmabuf, exp_info->flags); - if (IS_ERR(file)) { - ret = PTR_ERR(file); + ret = dma_buf_stats_setup(dmabuf, file); + if (ret) goto err_dmabuf; - } + file->f_mode |= FMODE_LSEEK; + file->private_data = dmabuf; + file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); mutex_unlock(&db_list.lock); diff --cc drivers/gpu/drm/bridge/ite-it6505.c index 99123eec4551,21a9b8422bda..c13fb0bc6260 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_ DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev)); debugfs_init(it6505); + pm_runtime_enable(dev); + + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->bridge.funcs = &it6505_bridge_funcs; it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 21cd1a4e1823,a0740308555d..bf68f2330dd9 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); /* Wa_18018781329:dg2,pvc */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + } } static void diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 4d1cc383b681,410905da8e97..e8d1bd04d2a2 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -291,16 -350,17 +361,55 @@@ out } void intel_huc_fini(struct intel_huc *huc) + { + /* + * the fence is initialized in init_early, so we need to clean it up + * even if HuC loading is off. + */ + delayed_huc_load_fini(huc); + + if (intel_uc_fw_is_loadable(&huc->fw)) + intel_uc_fw_fini(&huc->fw); + } + ++void intel_huc_suspend(struct intel_huc *huc) +{ + if (!intel_uc_fw_is_loadable(&huc->fw)) + return; + ++ /* ++ * in the unlikely case that we're suspending before the GSC has ++ * completed its loading sequence, just stop waiting. We'll restart ++ * on resume. ++ */ + delayed_huc_load_complete(huc); ++} + - i915_sw_fence_fini(&huc->delayed_load.fence); - intel_uc_fw_fini(&huc->fw); ++int intel_huc_wait_for_auth_complete(struct intel_huc *huc) ++{ ++ struct intel_gt *gt = huc_to_gt(huc); ++ int ret; ++ ++ ret = __intel_wait_for_register(gt->uncore, ++ huc->status.reg, ++ huc->status.mask, ++ huc->status.value, ++ 2, 50, NULL); ++ ++ /* mark the load process as complete even if the wait failed */ ++ delayed_huc_load_complete(huc); ++ ++ if (ret) { ++ drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret); ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); ++ return ret; ++ } ++ ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); ++ drm_info(&gt->i915->drm, "HuC authenticated\n"); ++ return 0; +} + void intel_huc_suspend(struct intel_huc *huc) { if (!intel_uc_fw_is_loadable(&huc->fw)) Commit list: commit 78a033433a5ae4fee85511ee075bc9a48312c79e commit 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commit 8f32378986218812083b127da5ba42d48297d7c4 commit 2a00299e7447395d0898e7c6214817c06a61a8e8 commit a2a04b515562bbb040e8ae3decae8c1e9ef05327 commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
Merge DRM changes from upstream v5.18..v5.19 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.19 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/bridge/Kconfig drivers/gpu/drm/bridge/analogix/analogix_dp_core.c drivers/gpu/drm/bridge/chipone-icn6211.c drivers/gpu/drm/drm_edid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/drm_format_helper.c drivers/gpu/drm/i915/gt/intel_gsc.c drivers/gpu/drm/i915/gvt/gvt.h drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/i915_driver.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_gvt_mmio_table.c drivers/gpu/drm/mgag200/mgag200_mode.c drivers/gpu/drm/solomon/ssd130x.c drivers/gpu/drm/vmwgfx/vmwgfx_fb.c include/drm/i915_drm.h Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index d91dc8b0effc,30fe847c6664..193c7c83c70f --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -5,6 -5,8 +5,7 @@@ */ #include <linux/dma-resv.h> + #include <linux/highmem.h> -#include <linux/intel-iommu.h> #include <linux/sync_file.h> #include <linux/uaccess.h> Commit list: commit c6e7deb0f092616bd8cb19e8c436b212c64daaab commit 072ce4164f973bc762b25ce9a41636bffe75ab36 commit f8a005eb89720c913e59707d061a1b7e9c8b3358 commit 14ad15296d1fd067e54ad04d96056fe0aed61f2d commit 0225a90981c83408e9606b52a65edee1c6891106 commit 7ad9993b2368f2a861f335184cd2bb1909f13827 commit 772ba8d68515fb8d5414eb714a1d4d446903eb13 commit b4eb76d82a0ea92241f5079874a7aea10c5cc4ae commit 2ff5560e23c863b22afb7db01208a76d9f1d1046 commit 53581504a8e216d435f114a4f2596ad0dfd902fc commit cccc71b552a1040ad3d738d7ec95570801fb0bf6 commit 6c6465fc33c5679a418fb06ff582cd38e68eb5e2 commit c2393a1d8bd1a69ff74ee769fa5d36e4900d4fba commit 3dda9ee49ea5d332359ca372728ee13e570b7e04 commit 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90af0ca047f3049c4b46e902f432ad6ef1e2ded6 commit 1c46f3c0759116d70cb424fc227371a254c47b25 commit 7f5ec14a4e07a2a78fbde069709d5c8806882be2 commit a7a47a5dfa9a9692a41764ee9ab4054f12924a42 commit c653c591789b3acfa4bf6ae45d5af4f330e50a91 commit 0c09bc33aa8e9dc867300acaadc318c2f0d85a1e commit 66cee9097e2b74ff3c8cc040ce5717c521a0c3fa commit 9d928d9b78beec5d4b8afde9c144919b979685f2 commit ce156c8a1811c96a243590abd0e9b5a3b72c1f3a commit e65c6a46df94c8d76ea1129eb2d4564670c6f214 Omitted-fix: 0b752df77633 ("drm/rockchip: Fix Kconfig dependencies for display-port encoders") Omitted-fix: 16c8d76abe83 ("dt-bindings: display: bridge: ldb: Fill in reg property") Omitted-fix: 30bdc36b8c77 ("drm/imx/dcss: get rid of HPD warning message") Omitted-fix: 91954c6c904b ("drm/amd/display: Fix mutex lock in dcn10") Omitted-fix: 920169041baa ("drm/sun4i: dw-hdmi: Fix ddc-en GPIO consumer conflict") Omitted-fix: be273ecfbe8a ("drm/vc4: Use newer fence API properly to fix build errors") Omitted-fix: d9927abb4594 ("Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:27:09 +00:00
# x86 intel-gtt module support
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
gt-$(CONFIG_X86) += \
gt/intel_ggtt_gmch.o
drm/i915: Move the renderstate setup under gt/ The render state is used to initialise the default RCS context, and only used during early setup from within the gt code. As such, it makes a good candidate for placing within gt/, even if it is not yet entirely clean of our GEM heritage. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190704091925.7391-1-chris@chris-wilson.co.uk
2019-07-04 09:19:25 +00:00
# autogenerated null render state
gt-y += \
gt/gen6_renderstate.o \
gt/gen7_renderstate.o \
gt/gen8_renderstate.o \
gt/gen9_renderstate.o
drm/i915: Move GraphicsTechnology files under gt/ Start partitioning off the code that talks to the hardware (GT) from the uapi layers and move the device facing code under gt/ One casualty is s/intel_ringbuffer.h/intel_engine.h/ with the plan to subdivide that header and body further (and split out the submission code from the ringbuffer and logical context handling). This patch aims to be simple motion so git can fixup inflight patches with little mess. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424174839.7141-1-chris@chris-wilson.co.uk
2019-04-24 17:48:39 +00:00
i915-y += $(gt-y)
# GEM (Graphics Execution Management) code
drm/i915: Move object->pages API to i915_gem_object.[ch] Currently the code for manipulating the pages on an object is still residing in i915_gem.c, move it to i915_gem_object.c Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-3-chris@chris-wilson.co.uk
2019-05-28 09:29:44 +00:00
gem-y += \
drm/i915: Move GEM object busy checking to its own file Continuing the decluttering of i915_gem.c by moving the object busy checking into its own file. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-12-chris@chris-wilson.co.uk
2019-05-28 09:29:53 +00:00
gem/i915_gem_busy.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_clflush.o \
gem/i915_gem_context.o \
drm/i915/gem: split gem_create into own file In preparation for gem_create_ext break out the gem_create uAPI, so that we don't clutter i915_gem.c once we start adding various extensions Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210114182402.840247-1-matthew.auld@intel.com
2021-01-14 18:24:00 +00:00
gem/i915_gem_create.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_dmabuf.o \
drm/i915: Move GEM domain management to its own file Continuing the decluttering of i915_gem.c, that of the read/write domains, perhaps the biggest of GEM's follies? Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-7-chris@chris-wilson.co.uk
2019-05-28 09:29:48 +00:00
gem/i915_gem_domain.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_execbuffer.o \
gem/i915_gem_internal.o \
drm/i915: support creating LMEM objects We currently define LMEM, or local memory, as just another memory region, like system memory or stolen, which we can expose to userspace and can be mapped to the CPU via some BAR. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191025153728.23689-1-chris@chris-wilson.co.uk
2019-10-25 15:37:22 +00:00
gem/i915_gem_lmem.o \
drm/i915: Move mmap and friends to its own file Continuing the decluttering of i915_gem.c, now the turn of do_mmap and the faulthandlers Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-6-chris@chris-wilson.co.uk
2019-05-28 09:29:47 +00:00
gem/i915_gem_mman.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
gem/i915_gem_object.o \
drm/i915: Move phys objects to its own file Continuing the decluttering of i915_gem.c, this time the legacy physical object. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-5-chris@chris-wilson.co.uk
2019-05-28 09:29:46 +00:00
gem/i915_gem_pages.o \
gem/i915_gem_phys.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_pm.o \
drm/i915: introduce intel_memory_region Support memory regions, as defined by a given (start, end), and allow creating GEM objects which are backed by said region. The immediate goal here is to have something to represent our device memory, but later on we also want to represent every memory domain with a region, so stolen, shmem, and of course device. At some point we are probably going to want use a common struct here, such that we are better aligned with say TTM. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191008160116.18379-2-matthew.auld@intel.com
2019-10-08 16:01:14 +00:00
gem/i915_gem_region.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_shmem.o \
gem/i915_gem_shrinker.o \
gem/i915_gem_stolen.o \
drm/i915: Move GEM client throttling to its own file Continuing the decluttering of i915_gem.c by moving the client self throttling into its own file. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-13-chris@chris-wilson.co.uk
2019-05-28 09:29:54 +00:00
gem/i915_gem_throttle.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_tiling.o \
Merge DRM changes from upstream v5.14..v5.15 This commit was generated using: rhdrm-merge-drm v5.15 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: Makefile drivers/gpu/drm/drm_gem_atomic_helper.c drivers/gpu/drm/drm_gem_framebuffer_helper.c drivers/gpu/drm/gud/gud_pipe.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c include/drm/drm_gem_atomic_helper.h include/drm/drm_gem_framebuffer_helper.h Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment } } #endif /* CONFIG_DMA_API_DEBUG */ - return sg_table; } -EXPORT_SYMBOL_GPL(dma_buf_map_attachment); +EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF); /** * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd goto free; if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) - adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); } +#ifdef CONFIG_X86_MCE_AMD + if ((adev->asic_type == CHIP_ALDEBARAN) && + (adev->gmc.xgmi.connected_to_cpu)) + amdgpu_register_bad_pages_mca_notifier(); +#endif + return 0; free: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) #define I915_BO_ALLOC_VOLATILE BIT(1) - #define I915_BO_ALLOC_STRUCT_PAGE BIT(2) - #define I915_BO_ALLOC_CPU_CLEAR BIT(3) + #define I915_BO_ALLOC_CPU_CLEAR BIT(2) + #define I915_BO_ALLOC_USER BIT(3) #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ - I915_BO_ALLOC_STRUCT_PAGE | \ - I915_BO_ALLOC_CPU_CLEAR) + I915_BO_ALLOC_CPU_CLEAR | \ + I915_BO_ALLOC_USER) #define I915_BO_READONLY BIT(4) #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ +#define I915_BO_WAS_BOUND_BIT 6 - /* - * Is the object to be mapped as read-only to the GPU - * Only honoured if hardware has relevant pte bit + /** + * @mem_flags - Mutable placement-related flags + * + * These are flags that indicate specifics of the memory region + * the object is currently in. As such they are only stable + * either under the object lock or if the object is pinned. + */ + unsigned int mem_flags; + #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */ + #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */ + /** + * @cache_level: The desired GTT caching level. + * + * See enum i915_cache_level for possible values, along with what + * each does. */ unsigned int cache_level:3; - unsigned int cache_coherent:2; + /** + * @cache_coherent: + * + * Track whether the pages are coherent with the GPU if reading or + * writing through the CPU caches. The largely depends on the + * @cache_level setting. + * + * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom + * platforms, coherency must be explicitly requested with some special + * GTT caching bits(see enum i915_cache_level). When enabling coherency + * it does come at a performance and power cost on such platforms. On + * the flip side the kernel does not need to manually flush any buffers + * which need to be coherent with the GPU, if the object is not coherent + * i.e @cache_coherent is zero. + * + * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory + * access will automatically snoop the CPU caches(even with CACHE_NONE). + * The one exception is when dealing with the display engine, like with + * scanout surfaces. To handle this the kernel will always flush the + * surface out of the CPU caches when preparing it for scanout. Also + * note that since scanout surfaces are only ever read by the display + * engine we only need to care about flushing any writes through the CPU + * cache, reads on the other hand will always be coherent. + * + * Something strange here is why @cache_coherent is not a simple + * boolean, i.e coherent vs non-coherent. The reasoning for this is back + * to the display engine not being fully coherent. As a result scanout + * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT. + * In the case of seeing I915_CACHE_NONE the kernel makes the assumption + * that this is likely a scanout surface, and will set @cache_coherent + * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared + * LLC. The kernel uses this to always flush writes through the CPU + * cache as early as possible, where it can, in effect keeping + * @cache_dirty clean, so we can potentially avoid stalling when + * flushing the surface just before doing the scanout. This does mean + * we might unnecessarily flush non-scanout objects in some places, but + * the default assumption is that all normal objects should be using + * I915_CACHE_LLC, at least on platforms with the shared LLC. + * + * Supported values: + * + * I915_BO_CACHE_COHERENT_FOR_READ: + * + * On shared LLC platforms, we use this for special scanout surfaces, + * where the display engine is not coherent with the CPU cache. As such + * we need to ensure we flush any writes before doing the scanout. As an + * optimisation we try to flush any writes as early as possible to avoid + * stalling later. + * + * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC + * platforms, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ + * + * While for normal objects that are fully coherent, including special + * scanout surfaces marked as I915_CACHE_WT, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ | + * I915_BO_CACHE_COHERENT_FOR_WRITE + * + * And then for objects that are not coherent at all we use: + * + * cache_coherent = 0 + * + * I915_BO_CACHE_COHERENT_FOR_WRITE: + * + * When writing through the CPU cache, the GPU is still coherent. Note + * that this also implies I915_BO_CACHE_COHERENT_FOR_READ. + */ #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) + unsigned int cache_coherent:2; + + /** + * @cache_dirty: + * + * Track if we are we dirty with writes through the CPU cache for this + * object. As a result reading directly from main memory might yield + * stale data. + * + * This also ties into whether the kernel is tracking the object as + * coherent with the GPU, as per @cache_coherent, as it determines if + * flushing might be needed at various points. + * + * Another part of @cache_dirty is managing flushing when first + * acquiring the pages for system memory, at this point the pages are + * considered foreign, so the default assumption is that the cache is + * dirty, for example the page zeroing done by the kernel might leave + * writes though the CPU cache, or swapping-in, while the actual data in + * main memory is potentially stale. Note that this is a potential + * security issue when dealing with userspace objects and zeroing. Now, + * whether we actually need apply the big sledgehammer of flushing all + * the pages on acquire depends on if @cache_coherent is marked as + * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent + * for both reads and writes though the CPU cache. + * + * Note that on shared LLC platforms we still apply the heavy flush for + * I915_CACHE_NONE objects, under the assumption that this is going to + * be used for scanout. + * + * Update: On some hardware there is now also the 'Bypass LLC' MOCS + * entry, which defeats our @cache_coherent tracking, since userspace + * can freely bypass the CPU cache when touching the pages with the GPU, + * where the kernel is completely unaware. On such platform we need + * apply the sledgehammer-on-acquire regardless of the @cache_coherent. + */ unsigned int cache_dirty:1; /** diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c index b9aaf640f372,6109cd9e3399..e7efd9ede8e4 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de struct nvkm_client *client; struct nvkm_device *device; - drm_dev_unregister(dev); + drm_dev_unplug(dev); - dev->irq_enabled = false; client = nvxx_client(&drm->client.base); device = nvkm_device_find(client->device); diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c index f9d399ea628d,e50fb82a3030..2aceac7856e2 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c @@@ -28,9 -28,10 +28,10 @@@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/mem_encrypt.h> +#include <linux/cc_platform.h> #include <asm/hypervisor.h> + #include <drm/drm_ioctl.h> #include "vmwgfx_drv.h" #include "vmwgfx_msg_x86.h" @@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st unsigned long msg_len = strlen(msg); /* HB port can't access encrypted memory. */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_high; + u32 channel_id = (channel->channel_id << 16); si = (uintptr_t) msg; di = channel->cookie_low; @@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str unsigned long si, di, eax, ebx, ecx, edx; /* HB port can't access encrypted memory */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_low; + u32 channel_id = (channel->channel_id << 16); si = channel->cookie_high; di = (uintptr_t) reply; Commit list: commit 241a9e233e7cf1001d09426c9fc520768f8961bf commit 4154fa0e2688118ba3dbc67aa834435463f9ea68 commit 3faea9939a3d1eb5a40f3f6100c24792865b6445 commit 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commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7 commit fcf918ffd3b35e288097036c04af7446b2c6f2f1 commit 9761ffb8f1090289b908590039e2c363cc35cf45 commit 6e6f96630805874fa80b0067e1a57aafc06225f6 commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2 commit defbbcd99fa68cb7feed453662048baa87e9a441 commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5 commit 54149d13f369e1ab02f36b91feee02069184c1d8 commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e commit 19928833e8f8fa5ee687c451437ce674f19d6c09 commit 79516af3497a5b89acb09f4a644f61d6c69e5f16 commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626 commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
gem/i915_gem_ttm.o \
Merge DRM changes from upstream v5.16..v5.17 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.17 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/Makefile drivers/gpu/drm/i915/gem/i915_gem_pages.c drivers/gpu/drm/i915/gt/intel_gt.c drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c Conflict resolution: diff --cc drivers/gpu/drm/Makefile index 0dff40bb863c,ec2ef2cce11c..301a44dc18e3 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@@ -127,3 -134,8 +134,4 @@@ obj-$(CONFIG_DRM_TIDSS) += tidss obj-y += xlnx/ obj-y += gud/ obj-$(CONFIG_DRM_HYPERV) += hyperv/ + obj-$(CONFIG_DRM_SPRD) += sprd/ - -# Enable shims for the RHEL DRM backport -subdir-ccflags-y += -DRH_DRM_BACKPORT -drm-y += drm_backport.o Commit list: commit 107fe904302092c683cf5462b4af3cb3cfa40998 commit a1a98689301b9af0313e4c1ba44558e8b67ff76e commit befe5404a00b3b1547c944738df4a9229909bdc9 commit 8a12b170558aabb31cc98fda0da6a56b518cadaa commit 334f74ee85dc26a50c1a2b0da82517595191f92f commit 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commit 08783aa7693f55619859f4f63f384abf17cb58c5 commit 26d3474348293dc752c55fe6d41282199f73714c commit 62929726ef0ec72cbbe9440c5d125d4278b99894 commit f1ef17011c765495c876fa75435e59eecfdc1ee4 commit c9585249c245e23580a2c3edbc8f14d9d7173f12 commit 8fdb19679722a02fe21642d39710c701d2ed567a commit 804f468853179b9b58af05c153c411931aa5b310 commit 3755d35ee1d2454b20b8a1e20d790e56201678a4 commit 40ce1121c1d76daf9048a86e36c83e469281b9fd commit fc1b6ef7bfb3d1d4df868b1c3e0480cacda6cd81 commit a8253684eb4b30abd3faf055bc475c23da748dc6 commit 3c3384050d68570f9de0fec9e58824decfefba7a Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:15:52 +00:00
gem/i915_gem_ttm_move.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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commit aa464957f7e660abd554f2546a588f6533720e21 commit 78fed39af1af5d702089fe53076c524646e64997 commit a2fbfd517117157e99160ff1b39b171872dcba07 commit fc74881c28d314b10efac016ef49df4ff40b8b97 commit bf67014d6bda16a72deea11dbbff2a97c705ca92 commit 19e66d512e4182a0461530fa3159638e0f55d97e commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5 commit 7807bf28fe02a76bf112916c6b9194f282f5e43c commit 67f74302f45d5d862f22ced3297624e50ac352f0 commit 4d625a97a7e96be016382e3bb0a3cead05fec153 commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c commit d46f329a3f6048e04736e86cb13c880645048792 commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1 commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464 commit ebae8973884ee9ac703b3bfe34cabbb118b18538 commit 2eb82577a16d4c8eb31e4ed520649850bb95b223 commit d97e631af2db84c8c9d63abf68d487d0bb559e4c commit a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
gem/i915_gem_ttm_pm.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gem_userptr.o \
drm/i915: Move GEM object waiting to its own file Continuing the decluttering of i915_gem.c by moving the object wait decomposition into its own file. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-11-chris@chris-wilson.co.uk
2019-05-28 09:29:52 +00:00
gem/i915_gem_wait.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/i915_gemfs.o
drm/i915: Generalise GPU activity tracking We currently track GPU memory usage inside VMA, such that we never release memory used by the GPU until after it has finished accessing it. However, we may want to track other resources aside from VMA, or we may want to split a VMA into multiple independent regions and track each separately. For this purpose, generalise our request tracking (akin to struct reservation_object) so that we can embed it into other objects. v2: Tweak error handling during selftest setup. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190205130005.2807-2-chris@chris-wilson.co.uk
2019-02-05 13:00:02 +00:00
i915-y += \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
$(gem-y) \
i915_active.o \
i915_cmd_parser.o \
i915_deps.o \
i915_gem.o \
i915_gem_evict.o \
i915_gem_gtt.o \
i915_gem_ww.o \
i915_query.o \
i915_request.o \
i915_scheduler.o \
i915_trace_points.o \
i915_ttm_buddy_manager.o \
i915_vma.o \
i915_vma_resource.o
drm/i915: Go OCD on the Makefile Chris suggested to split things up a bit into the different parts of the driver and also sort it all correctly, with the hope that we're trying to organize things a bit better eventually. It should also help newcomers to orient themselves a bit better. v2: - Move intel_pm.c to the core - to make things perfect we should split out the modeset related pm features (psr/fbc) into a separate file. Maybe something Rodrigo can do once the PSR patches have settled. - Split the modesetting sections into core and encoders/outputs. intel_ddi.c is a bit funky since it has core hsw+ support and ddi output support. Whatever. v3: Failed to git add ... v4: Really go ocd, i.e. spelling fix in a comment from Jani. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-07 08:17:21 +00:00
drm/i915: GuC-specific firmware loader This fetches the required firmware image from the filesystem, then loads it into the GuC's memory via a dedicated DMA engine. This patch is derived from GuC loading work originally done by Vinit Azad and Ben Widawsky. v2: Various improvements per review comments by Chris Wilson v3: Removed 'wait' parameter to intel_guc_ucode_load() as firmware prefetch is no longer supported in the common firmware loader, per Daniel Vetter's request. Firmware checker callback fn now returns errno rather than bool. v4: Squash uC-independent code into GuC-specifc loader [Daniel Vetter] Don't keep the driver working (by falling back to execlist mode) if GuC firmware loading fails [Daniel Vetter] v5: Clarify WOPCM-related #defines [Tom O'Rourke] Delete obsolete code no longer required with current h/w & f/w [Tom O'Rourke] Move the call to intel_guc_ucode_init() later, so that it can allocate GEM objects, and have it fetch the firmware; then intel_guc_ucode_load() doesn't need to fetch it later. [Daniel Vetter]. v6: Update comment describing intel_guc_ucode_load() [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:36 +00:00
# general-purpose microcontroller (GuC) support
Merge DRM changes from upstream v6.2..v6.3 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.3 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/display/drm_dp_aux_bus.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/i915_irq.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6ff156cd64ae,54933903bcb8..fe2752ec67f7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -1017,10 -1029,10 +1022,11 @@@ int svm_migrate_init(struct amdgpu_devi r = devm_memremap_pages(adev->dev, pgmap); if (IS_ERR(r)) { pr_err("failed to register HMM device memory\n"); + /* Disable SVM support capability */ pgmap->type = 0; - devm_release_mem_region(adev->dev, res->start, resource_size(res)); + if (pgmap->type == MEMORY_DEVICE_PRIVATE) + devm_release_mem_region(adev->dev, res->start, resource_size(res)); return PTR_ERR(r); } diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index b617b27577ef,d5b5d40ed817..710e51d2377f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -686,8 -683,15 +687,16 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); + /* + * Seamless M/N update may need to update frame timings. + * + * FIXME Should be synchronized with the start of vblank somehow... + */ + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + intel_crtc_update_active_timings(new_crtc_state); + - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; Commit list: commit 7ae2e684854cd955eff8daceff84fea33a1c94be commit 192bb40f030a41ca95c5cff8c9340b725bc7ba8b commit 4b9cc6efeb0684912d518e9953a1d493b2b89a02 commit 3b5130a68df1a513713b027d03125ba11ebc2975 commit 6ebf5caf1fae75634b0564152958ecb433cfa952 commit 201ec1bbca03a0c190962626574f8061a84cc9e7 commit c584f86c6242dff11d3e8f7b1646e5470a132784 commit d82b9a898d52a30adbedd158222f162489db52ac commit 09b350d7b05a62c9a59e201fcad4331ac6ee40c7 commit ef228dbfff70ca5823495d78ddb632abe230ce6f commit f322ed0d76ef0c0f2be99780c2a40ac405411cf5 commit 7aa3d63e1ad56c174536a5aba76d8a54c4c5acb4 commit 8b83e1a455382dc667898a525a93f4eb6716cc41 commit e3ddd2d25533d1cc6f9fea421e4a5f16b60b3434 commit 71feb6f901ecba962177a0a029dc545c91a4b396 commit 7df34a619f59439f38e56d389df02ee7e9e8cc97 commit 834c23e4f798dcdc8af251b3c428ceef94741991 commit 67b5655b2e717b8b681f8acd9cbddd2d687d5d4e commit e746f84b8e813816951b63485134927ed6763a1b commit 9a0a4ec530a7514ccd6061ecdeaf719a03cb34cd commit 25e0e5ae561003817797c23ae3b85cf510be11c5 commit 86c0ef7234a7c517b010fd5ecf1e176127bce521 commit 282e86eaa5d5e032541b5e3c0b9d0a55fe000607 commit 8853750dbad8f5dbf912a9f13b3fea41965634e1 commit f1c87a94a1087a26f41007ee83264033007421b5 commit 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commit f126f41cec1b6fa04c1d06517ec8f3e19908c5f7 commit 3b1f2be527ce04e7d8dce6fad6be16fa59058713 commit 00a4bd000e78a3a898e60bdc13e2852c8044a38c Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-05-02 06:34:23 +00:00
i915-y += \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
gt/uc/intel_gsc_fw.o \
gt/uc/intel_gsc_proxy.o \
gt/uc/intel_gsc_uc.o \
gt/uc/intel_gsc_uc_debugfs.o \
gt/uc/intel_gsc_uc_heci_cmd_submit.o\
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
gt/uc/intel_guc_capture.o \
gt/uc/intel_guc_ct.o \
gt/uc/intel_guc_debugfs.o \
gt/uc/intel_guc_fw.o \
gt/uc/intel_guc_hwconfig.o \
gt/uc/intel_guc_log.o \
gt/uc/intel_guc_log_debugfs.o \
gt/uc/intel_guc_rc.o \
gt/uc/intel_guc_slpc.o \
gt/uc/intel_guc_submission.o \
gt/uc/intel_huc.o \
gt/uc/intel_huc_debugfs.o \
gt/uc/intel_huc_fw.o \
gt/uc/intel_uc.o \
gt/uc/intel_uc_debugfs.o \
gt/uc/intel_uc_fw.o
drm/i915: GuC-specific firmware loader This fetches the required firmware image from the filesystem, then loads it into the GuC's memory via a dedicated DMA engine. This patch is derived from GuC loading work originally done by Vinit Azad and Ben Widawsky. v2: Various improvements per review comments by Chris Wilson v3: Removed 'wait' parameter to intel_guc_ucode_load() as firmware prefetch is no longer supported in the common firmware loader, per Daniel Vetter's request. Firmware checker callback fn now returns errno rather than bool. v4: Squash uC-independent code into GuC-specifc loader [Daniel Vetter] Don't keep the driver working (by falling back to execlist mode) if GuC firmware loading fails [Daniel Vetter] v5: Clarify WOPCM-related #defines [Tom O'Rourke] Delete obsolete code no longer required with current h/w & f/w [Tom O'Rourke] Move the call to intel_guc_ucode_init() later, so that it can allocate GEM objects, and have it fetch the firmware; then intel_guc_ucode_load() doesn't need to fetch it later. [Daniel Vetter]. v6: Update comment describing intel_guc_ucode_load() [Tom O'Rourke] Issue: VIZ-4884 Signed-off-by: Alex Dai <yu.dai@intel.com> Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 14:43:36 +00:00
drm/i915/gsc: add gsc as a mei auxiliary device Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Upstream Status: v5.19-rc1 commit 1e3dc1d8622b2699e6cf1cc06885105b13c9c514 Author: Tomas Winkler <tomas.winkler@intel.com> AuthorDate: Tue Apr 19 12:33:08 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Thu Apr 21 11:33:56 2022 -0700 GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-2-daniele.ceraolospurio@intel.com Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-09-26 14:12:00 +00:00
# graphics system controller (GSC) support
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-y += \
gt/intel_gsc.o
drm/i915/gsc: add gsc as a mei auxiliary device Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Upstream Status: v5.19-rc1 commit 1e3dc1d8622b2699e6cf1cc06885105b13c9c514 Author: Tomas Winkler <tomas.winkler@intel.com> AuthorDate: Tue Apr 19 12:33:08 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Thu Apr 21 11:33:56 2022 -0700 GSC is a graphics system controller, it provides a chassis controller for graphics discrete cards. There are two MEI interfaces in GSC: HECI1 and HECI2. Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000. GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled via bit 15 and HECI2 via bit 14 in the interrupt register. This patch exports GSC as auxiliary device for mei driver to bind to for HECI2 interface and prepares for HECI1 interface as it will follow up soon. CC: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220419193314.526966-2-daniele.ceraolospurio@intel.com Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-09-26 14:12:00 +00:00
Merge DRM changes from upstream v6.1..v6.2 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.2 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/dma-buf/dma-buf.c drivers/gpu/drm/amd/amdgpu/mes_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c drivers/gpu/drm/ast/ast_drv.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/selftest_slpc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_huc.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/pxp/intel_pxp_huc.c drivers/gpu/drm/i915/pxp/intel_pxp_tee.c drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c drivers/gpu/drm/vmwgfx/vmwgfx_kms.c Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st init_waitqueue_head(&dmabuf->poll); dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll; dmabuf->cb_in.active = dmabuf->cb_out.active = 0; + INIT_LIST_HEAD(&dmabuf->attachments); if (!resv) { - resv = (struct dma_resv *)&dmabuf[1]; - dma_resv_init(resv); + dmabuf->resv = (struct dma_resv *)&dmabuf[1]; + dma_resv_init(dmabuf->resv); + } else { + dmabuf->resv = resv; } - dmabuf->resv = resv; - file = dma_buf_getfile(dmabuf, exp_info->flags); - if (IS_ERR(file)) { - ret = PTR_ERR(file); + ret = dma_buf_stats_setup(dmabuf, file); + if (ret) goto err_dmabuf; - } + file->f_mode |= FMODE_LSEEK; + file->private_data = dmabuf; + file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); mutex_unlock(&db_list.lock); diff --cc drivers/gpu/drm/bridge/ite-it6505.c index 99123eec4551,21a9b8422bda..c13fb0bc6260 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_ DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev)); debugfs_init(it6505); + pm_runtime_enable(dev); + + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->bridge.funcs = &it6505_bridge_funcs; it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 21cd1a4e1823,a0740308555d..bf68f2330dd9 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); /* Wa_18018781329:dg2,pvc */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + } } static void diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 4d1cc383b681,410905da8e97..e8d1bd04d2a2 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -291,16 -350,17 +361,55 @@@ out } void intel_huc_fini(struct intel_huc *huc) + { + /* + * the fence is initialized in init_early, so we need to clean it up + * even if HuC loading is off. + */ + delayed_huc_load_fini(huc); + + if (intel_uc_fw_is_loadable(&huc->fw)) + intel_uc_fw_fini(&huc->fw); + } + ++void intel_huc_suspend(struct intel_huc *huc) +{ + if (!intel_uc_fw_is_loadable(&huc->fw)) + return; + ++ /* ++ * in the unlikely case that we're suspending before the GSC has ++ * completed its loading sequence, just stop waiting. We'll restart ++ * on resume. ++ */ + delayed_huc_load_complete(huc); ++} + - i915_sw_fence_fini(&huc->delayed_load.fence); - intel_uc_fw_fini(&huc->fw); ++int intel_huc_wait_for_auth_complete(struct intel_huc *huc) ++{ ++ struct intel_gt *gt = huc_to_gt(huc); ++ int ret; ++ ++ ret = __intel_wait_for_register(gt->uncore, ++ huc->status.reg, ++ huc->status.mask, ++ huc->status.value, ++ 2, 50, NULL); ++ ++ /* mark the load process as complete even if the wait failed */ ++ delayed_huc_load_complete(huc); ++ ++ if (ret) { ++ drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret); ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); ++ return ret; ++ } ++ ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); ++ drm_info(&gt->i915->drm, "HuC authenticated\n"); ++ return 0; +} + void intel_huc_suspend(struct intel_huc *huc) { if (!intel_uc_fw_is_loadable(&huc->fw)) Commit list: commit 78a033433a5ae4fee85511ee075bc9a48312c79e commit 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commit 8f32378986218812083b127da5ba42d48297d7c4 commit 2a00299e7447395d0898e7c6214817c06a61a8e8 commit a2a04b515562bbb040e8ae3decae8c1e9ef05327 commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
# graphics hardware monitoring (HWMON) support
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-$(CONFIG_HWMON) += \
i915_hwmon.o
Merge DRM changes from upstream v6.1..v6.2 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.2 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/dma-buf/dma-buf.c drivers/gpu/drm/amd/amdgpu/mes_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c drivers/gpu/drm/ast/ast_drv.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/selftest_slpc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_huc.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/pxp/intel_pxp_huc.c drivers/gpu/drm/i915/pxp/intel_pxp_tee.c drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c drivers/gpu/drm/vmwgfx/vmwgfx_kms.c Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st init_waitqueue_head(&dmabuf->poll); dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll; dmabuf->cb_in.active = dmabuf->cb_out.active = 0; + INIT_LIST_HEAD(&dmabuf->attachments); if (!resv) { - resv = (struct dma_resv *)&dmabuf[1]; - dma_resv_init(resv); + dmabuf->resv = (struct dma_resv *)&dmabuf[1]; + dma_resv_init(dmabuf->resv); + } else { + dmabuf->resv = resv; } - dmabuf->resv = resv; - file = dma_buf_getfile(dmabuf, exp_info->flags); - if (IS_ERR(file)) { - ret = PTR_ERR(file); + ret = dma_buf_stats_setup(dmabuf, file); + if (ret) goto err_dmabuf; - } + file->f_mode |= FMODE_LSEEK; + file->private_data = dmabuf; + file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); mutex_unlock(&db_list.lock); diff --cc drivers/gpu/drm/bridge/ite-it6505.c index 99123eec4551,21a9b8422bda..c13fb0bc6260 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_ DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev)); debugfs_init(it6505); + pm_runtime_enable(dev); + + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->bridge.funcs = &it6505_bridge_funcs; it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 21cd1a4e1823,a0740308555d..bf68f2330dd9 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); /* Wa_18018781329:dg2,pvc */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + } } static void diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 4d1cc383b681,410905da8e97..e8d1bd04d2a2 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -291,16 -350,17 +361,55 @@@ out } void intel_huc_fini(struct intel_huc *huc) + { + /* + * the fence is initialized in init_early, so we need to clean it up + * even if HuC loading is off. + */ + delayed_huc_load_fini(huc); + + if (intel_uc_fw_is_loadable(&huc->fw)) + intel_uc_fw_fini(&huc->fw); + } + ++void intel_huc_suspend(struct intel_huc *huc) +{ + if (!intel_uc_fw_is_loadable(&huc->fw)) + return; + ++ /* ++ * in the unlikely case that we're suspending before the GSC has ++ * completed its loading sequence, just stop waiting. We'll restart ++ * on resume. ++ */ + delayed_huc_load_complete(huc); ++} + - i915_sw_fence_fini(&huc->delayed_load.fence); - intel_uc_fw_fini(&huc->fw); ++int intel_huc_wait_for_auth_complete(struct intel_huc *huc) ++{ ++ struct intel_gt *gt = huc_to_gt(huc); ++ int ret; ++ ++ ret = __intel_wait_for_register(gt->uncore, ++ huc->status.reg, ++ huc->status.mask, ++ huc->status.value, ++ 2, 50, NULL); ++ ++ /* mark the load process as complete even if the wait failed */ ++ delayed_huc_load_complete(huc); ++ ++ if (ret) { ++ drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret); ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); ++ return ret; ++ } ++ ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); ++ drm_info(&gt->i915->drm, "HuC authenticated\n"); ++ return 0; +} + void intel_huc_suspend(struct intel_huc *huc) { if (!intel_uc_fw_is_loadable(&huc->fw)) Commit list: commit 78a033433a5ae4fee85511ee075bc9a48312c79e commit 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commit 8f32378986218812083b127da5ba42d48297d7c4 commit 2a00299e7447395d0898e7c6214817c06a61a8e8 commit a2a04b515562bbb040e8ae3decae8c1e9ef05327 commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
drm/i915: Go OCD on the Makefile Chris suggested to split things up a bit into the different parts of the driver and also sort it all correctly, with the hope that we're trying to organize things a bit better eventually. It should also help newcomers to orient themselves a bit better. v2: - Move intel_pm.c to the core - to make things perfect we should split out the modeset related pm features (psr/fbc) into a separate file. Maybe something Rodrigo can do once the PSR patches have settled. - Split the modesetting sections into core and encoders/outputs. intel_ddi.c is a bit funky since it has core hsw+ support and ddi output support. Whatever. v3: Failed to git add ... v4: Really go ocd, i.e. spelling fix in a comment from Jani. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-07 08:17:21 +00:00
# modesetting core code
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
i915-y += \
Merge DRM changes from upstream v5.17..v5.18 This commit was generated using: rhdrm-merge-drm v5.18 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/drm_cache.c drivers/gpu/drm/drm_gem.c Conflict resolution: diff --cc drivers/gpu/drm/Makefile index 301a44dc18e3,308c302c58e9..c2ef5f9fce54 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@@ -134,4 -132,9 +132,5 @@@ obj-$(CONFIG_DRM_TIDSS) += tidss obj-y += xlnx/ obj-y += gud/ obj-$(CONFIG_DRM_HYPERV) += hyperv/ + obj-y += solomon/ obj-$(CONFIG_DRM_SPRD) += sprd/ - -# Enable shims for the RHEL DRM backport -subdir-ccflags-y += -DRH_DRM_BACKPORT -drm-y += drm_backport.o Commit list: commit cce936f4fff736927ffd53a61d7b2c6a1064e0c5 commit a908db6d98782e8d9a8d545dcc74937db5bfac04 commit ae361eb07e9b498bc224db81113118fd28e35f6e commit c2a9682d2214e834b493c454e38809e571bb3045 commit b8ca477e51318d28f7514abfb5a369e11848a8cf commit e74c6aa955caedd06b5ade58e31e33338e4efde6 commit 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commit eb7bac3973d209e5227d1783676362ee5a8a7127 commit 54395a33718af1c04b5098203335b25382291a16 commit 89e96d822bd51f7afe2d3e95a34099480b5c3d55 commit 6e03b13cc7d9427c2c77feed1549191015615202 commit 7123d39dc24dcd21ff23d75f46f926b15269b9da commit 7b1d6924f27ba24b9e47abb9bd53d0bbc430a835 commit 6e4a61cd39685476f7ea74e75fb66666d541050b commit 64eea6805ecf7092a113bdb4cb73860430d39de6 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:17:03 +00:00
display/hsw_ips.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/i9xx_plane.o \
display/i9xx_wm.o \
Merge DRM changes from upstream v6.10..v6.11 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.11 RHEL-53570 JIRA: https://issues.redhat.com/browse/RHEL-53570 Conflicts: drivers/gpu/drm/vmwgfx/vmwgfx_msg_x86.h Conflict resolution: diff --cc drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 323c33c9c37aa,c6b669866fed1..349a0ef6fd1fc --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@@ -16,14 -16,10 +16,10 @@@ #include <linux/gpio/consumer.h> #include <linux/delay.h> #include <linux/module.h> -#include <linux/of.h> +#include <linux/of_device.h> #include <linux/regulator/consumer.h> - #define JD9365DA_INIT_CMD_LEN 2 - - struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; - }; + struct jadard; struct jadard_panel_desc { const struct drm_display_mode mode; Commit list: commit 869e54d4d54b1b0ee16c98c2149f5785eea08c02 commit 06e7139a034f26804904368fe4af2ceb70724756 commit 8f21f82d8b7652e11e6800612e34547bffdc7fd2 commit 1cb4db30cf685709584743d8bf8a0db2eac620c9 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commit 38e3285dbd07db44487bbaca8c383a5d7f3c11f3 commit 43cf50eb1408ccb99cab01521263e8cb4cfdc023 commit a13494de53258d8cf82ed3bcd69176bbf7f2640e commit 466cb3c630a51b04995c6247d2fb73b5ce7bfd7f commit 9da7ec9b19d8c1ad4f44e459fa5f93ad7a117dcd commit 9a71cf8b6fa433a8f243626ba9930a3870584e38 commit 529bf8d1118bbaa1aa835563a22b0b5c64ca9d68 commit fe13fd68337512da4b7aee6326c397e817a943c7 commit 82122d1f54ec2244fb9c367ee2390b51ce08cf44 commit 269a3f60843b9d2045e0c09d4bd34a91ed4222aa commit 880b398288487029ef5062ec5d7fcfc90672f782 commit 4bfc9c553f5ea8cbfe085824f3283885cf173c20 commit 5f7762042f8a5377bd8a32844db353c0311a7369 commit 76dce2a96c0f48295e92acf7a8f3fa46ea0ee524 commit 7de295d1a1a1b84e57b348e8bfd0fab5aab3ce69 commit 5a498d4d06d6d9bad76d8a50a7f8fe01670ad46f commit 1a8d845470941f1b6de1b392227530c097dc5e0c commit 4de4a0f160cf8ccf29a9a70f00403e6948e7e108 commit ca10367a5abe5f04df1374b227a10439ef686b90 commit 141bb6bc73cf45e8b742d6fafa6734b6d5f82b77 commit ea5ff5d351b520524019f7ff7f9ce418de2dad87 commit d3d37f74683e2f16f2635ee265884f7ca69350ae commit 6db9df4f7055eb4ea339e7b83ca676edd9ec1277 commit 8c7c44be57672e1474bf15a451011c291e85fda4 commit 02c132166993c8f8ca1b319665181f72f22ebc6b commit a7aeb03888b92304e2fc7d4d1c242f54a312561b commit e835d5144f5ef78e4f8828c63e2f0d61144f283a commit c5b1a06697eae4d365691195ab2e0b45539bc2a9 commit 612e3bacf8009e329342934ce403fd4ca553beba commit 7a0982523cf3ff00f35b210fc3405c528a2ce7af commit 3a23aa0b9c24c682c506121e2e0f6cbcfdae9076 commit 8409fb50ce48d66cf9dc5391f03f05c56c430605 commit 17ea4383649fdeaff3181ddcf1ff03350d42e591 commit 2a2a865aee43dd6f1ddbb0581c2a2cc205beb768 commit a2655358cbda38d53d4a443c7edc7951d91c3043 commit 572239f7f15223e4cf22a8233677b9a080c3d873 commit 5e2d1d4dc1c15da3e1e3dc09dc3c1276274439b2 commit 062d59eb96b24990429c13706cb74ef09cec7e99 commit dd10595c3232d362f5a01e5d616434b2371ae8d4 commit a262cc8d554217fbe67e083159584beee3ea9b11 commit 9bd7ff293fc84792514aeafa06c5a17f05cb5f4b commit 94c4aa266111262c96c98f822d1bccc494786fee commit bb7e19bd6cb68e08272e08acb814b9342ad5a43d commit 690e516e9869791bcac00ad5a351d953a928044b commit 135be1dc46c64c454f2828dbb7f239d035f47180 Signed-off-by: Robert Foss <rfoss@redhat.com>
2024-11-21 22:32:33 +00:00
display/intel_alpm.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_atomic.o \
display/intel_atomic_plane.o \
display/intel_audio.o \
display/intel_bios.o \
Merge DRM changes from upstream v6.12..v6.13 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.13 RHEL-75951 JIRA: https://issues.redhat.com/browse/RHEL-75951 Conflicts: drivers/dma-buf/udmabuf.c drivers/gpu/drm/Kconfig drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c drivers/gpu/drm/amd/display/Kconfig drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c drivers/gpu/drm/amd/display/dc/inc/core_types.h drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_syncobj.c drivers/gpu/drm/i915/display/intel_display_trace.h drivers/gpu/drm/i915/i915_trace.h drivers/gpu/drm/i915/i915_utils.h drivers/gpu/drm/panthor/panthor_device.h drivers/gpu/drm/xe/xe_devcoredump.c drivers/gpu/drm/xe/xe_devcoredump_types.h drivers/gpu/drm/xe/xe_guc_log.c drivers/gpu/drm/xe/xe_hw_engine.c drivers/gpu/drm/xe/xe_pci.c drivers/gpu/drm/xe/xe_wa.c drivers/gpu/drm/xe/xe_wa_oob.rules include/drm/intel/xe_pciids.h Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index 7f8cbb07a24f,772fc7625639..7c1f72832160 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -211,15 -209,48 +209,53 @@@ config DRM_DEBUG_MODESET_LOC If in doubt, say "N". + config DRM_CLIENT + bool + depends on DRM + help + Enables support for DRM clients. DRM drivers that need + struct drm_client_dev and its interfaces should select this + option. Drivers that support the default clients should + select DRM_CLIENT_SELECTION instead. + + config DRM_CLIENT_LIB + tristate + depends on DRM + select DRM_KMS_HELPER if DRM_FBDEV_EMULATION + select FB_CORE if DRM_FBDEV_EMULATION + help + This option enables the DRM client library and selects all + modules and components according to the enabled clients. + + config DRM_CLIENT_SELECTION + tristate + depends on DRM + select DRM_CLIENT_LIB if DRM_FBDEV_EMULATION + help + Drivers that support in-kernel DRM clients have to select this + option. + + config DRM_CLIENT_SETUP + bool + depends on DRM_CLIENT_SELECTION + help + Enables the DRM client selection. DRM drivers that support the + default clients should select DRM_CLIENT_SELECTION instead. + + menu "Supported DRM clients" + depends on DRM_CLIENT_SELECTION + config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" - depends on DRM + depends on DRM_CLIENT_SELECTION + select DRM_CLIENT + select DRM_CLIENT_SETUP select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT ++ select FB_SYS_IMAGEBLIT default FB help Choose this option if you have a need for the legacy fbdev diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bd0dab9811d1,cd4fac120834..d73f84c53e76 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -33,11 -35,11 +35,10 @@@ #include <linux/iommu.h> #include <linux/pci.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_event.h> #include <drm/drm_crtc_helper.h> - #include <drm/drm_fb_helper.h> #include <drm/drm_probe_helper.h> #include <drm/amdgpu_drm.h> #include <linux/device.h> @@@ -4494,16 -4584,18 +4617,15 @@@ fence_driver_init if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); - px = amdgpu_device_supports_px(ddev); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(ddev)) { + px = true; vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, px); - - if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + } - if (adev->gmc.xgmi.pending_reset) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --cc drivers/gpu/drm/display/drm_dp_mst_topology.c index f0c6d50d8c33,dc4446d589e7..6bff2d5eb59c --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@@ -4184,10 -4188,10 +4191,21 @@@ static int drm_dp_mst_handle_up_req(str out_put_primary: drm_dp_mst_topology_put_mstb(mst_primary); out_clear_reply: - memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx)); - return 0; + reset_msg_rx_state(&mgr->up_req_recv); + return ret; + } + ++static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) ++{ ++ mutex_lock(&mgr->lock); ++ if (mgr->reset_rx_state) { ++ mgr->reset_rx_state = false; ++ reset_msg_rx_state(&mgr->down_rep_recv); ++ reset_msg_rx_state(&mgr->up_req_recv); ++ } ++ mutex_unlock(&mgr->lock); +} + static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --cc drivers/gpu/drm/drm_syncobj.c index 4fcfc0b9b386,4f2ab8a7b50f..0058689f69fa --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@@ -712,19 -712,17 +712,17 @@@ static int drm_syncobj_fd_to_handle(str int fd, u32 *handle) { struct drm_syncobj *syncobj; - struct fd f = fdget(fd); + CLASS(fd, f)(fd); int ret; - if (!f.file) + if (fd_empty(f)) return -EINVAL; - if (f.file->f_op != &drm_syncobj_file_fops) { - fdput(f); + if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - } /* take a reference to put in the idr */ - syncobj = fd_file(f)->private_data; + syncobj = f.file->private_data; drm_syncobj_get(syncobj); idr_preload(GFP_KERNEL); diff --cc drivers/gpu/drm/hyperv/hyperv_drm_drv.c index 7ef4d7ea5468,e0953777a206..34d8d5ef2a62 --- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c @@@ -7,10 -8,9 +8,10 @@@ #include <linux/hyperv.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/screen_info.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_shmem.h> #include <drm/drm_gem_shmem_helper.h> diff --cc drivers/gpu/drm/i915/display/intel_display_trace.h index fbd3f83df807,9bd8f1e505b0..eeb73303e2e0 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@@ -61,10 -102,14 +102,14 @@@ TRACE_EVENT(intel_pipe_disable ), TP_fast_assign( - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc *it__; - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - for_each_intel_crtc(&dev_priv->drm, it__) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, it__) { __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); } @@@ -90,8 -132,8 +132,8 @@@ TRACE_EVENT(intel_crtc_flip_done ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -114,8 -156,8 +156,8 @@@ TRACE_EVENT(intel_pipe_crc ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); @@@ -141,9 -183,9 +183,9 @@@ TRACE_EVENT(intel_cpu_fifo_underrun ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = pipe; + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -166,9 -208,9 +208,9 @@@ TRACE_EVENT(intel_pch_fifo_underrun TP_fast_assign( enum pipe pipe = pch_transcoder; - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - __entry->pipe = pipe; + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -192,8 -234,12 +234,12 @@@ TRACE_EVENT(intel_memory_cxsr TP_fast_assign( struct intel_crtc *crtc; - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - for_each_intel_crtc(&dev_priv->drm, crtc) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, crtc) { __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); } @@@ -232,8 -276,8 +276,8 @@@ TRACE_EVENT(g4x_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; @@@ -279,8 -323,8 +323,8 @@@ TRACE_EVENT(vlv_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->level = wm->level; @@@ -316,8 -360,8 +360,8 @@@ TRACE_EVENT(vlv_fifo_size ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->sprite0_start = sprite0_start; @@@ -345,9 -389,9 +389,9 @@@ TRACE_EVENT(intel_plane_async_flip ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, __dev_name_kms(plane)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; @@@ -373,9 -417,9 +417,9 @@@ TRACE_EVENT(intel_plane_update_noarm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -404,9 -448,9 +448,9 @@@ TRACE_EVENT(intel_plane_update_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -433,9 -477,9 +477,9 @@@ TRACE_EVENT(intel_plane_disable_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); - __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; ++ __assign_str(name, plane->base.name); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -458,11 -502,12 +502,12 @@@ TRACE_EVENT(intel_fbc_activate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -485,11 -530,12 +530,12 @@@ TRACE_EVENT(intel_fbc_deactivate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -512,11 -558,12 +558,12 @@@ TRACE_EVENT(intel_fbc_nuke ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -538,8 -585,8 +585,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_star ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -561,8 -608,8 +608,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_end ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -586,8 -633,8 +633,8 @@@ TRACE_EVENT(intel_pipe_update_start ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->min = crtc->debug.min_vbl; @@@ -614,8 -661,8 +661,8 @@@ TRACE_EVENT(intel_pipe_update_vblank_ev ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = crtc->debug.start_vbl_count; __entry->scanline = crtc->debug.scanline_start; __entry->min = crtc->debug.min_vbl; @@@ -640,8 -687,8 +687,8 @@@ TRACE_EVENT(intel_pipe_update_end ), TP_fast_assign( - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = frame; __entry->scanline = scanline_end; ), diff --cc drivers/gpu/drm/xe/Makefile index b578ef68bc34,bc7a04ce69fd..21a1ecca0fea --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@@ -145,10 -147,9 +147,9 @@@ endi # i915 Display compat #defines and #includes subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ - -I$(src)/display/ext \ - -I$(src)/compat-i915-headers \ + -I$(srctree)/$(src)/display/ext \ + -I$(srctree)/$(src)/compat-i915-headers \ -I$(srctree)/drivers/gpu/drm/i915/display/ \ - -Ddrm_i915_gem_object=xe_bo \ -Ddrm_i915_private=xe_device # Rule to build SOC code shared with i915 diff --cc drivers/gpu/drm/xe/xe_gt_topology.c index 3e113422b88d,df2042db7ee6..f504b1012493 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@@ -129,8 -129,8 +129,20 @@@ static voi load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) { struct xe_device *xe = gt_to_xe(gt); - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3); + u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); + ++ /* ++ * PTL platforms with media version 30.00 do not provide proper values ++ * for the media GT's L3 bank registers. Skip the readout since we ++ * don't have any way to obtain real values. ++ * ++ * This may get re-described as an official workaround in the future, ++ * but there's no tracking number assigned yet so we use a custom ++ * OOB workaround descriptor. ++ */ ++ if (XE_WA(gt, no_media_l3)) ++ return; + /* * PTL platforms with media version 30.00 do not provide proper values * for the media GT's L3 bank registers. Skip the readout since we diff --cc drivers/gpu/drm/xe/xe_guc_log.c index be47780ec2a7,df4cfb698cdb..38db790f254b --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@@ -5,11 -5,14 +5,15 @@@ #include "xe_guc_log.h" + #include <linux/fault-inject.h> + #include <drm/drm_managed.h> +#include <linux/vmalloc.h> + #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_devcoredump.h" + #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_map.h" Commit list: commit 3973a8d052829dcc5193fb6330dcd13c2b7127ca commit 7a5115ba1d691bd14db91d2fcc3ce0b056574ce9 commit c7d84a45f4266e9ff4c61eddde4acbfddb8f6b57 commit eb4accc5234525e2cb2b720187ccaf6db99b705f commit 3742c20958a5b02ecba08d71036bae3e7b9d21b3 commit 2872a57c7ad427d428c6d12e95e55b32bdc8e3b8 commit 9c75b16cabc69adbbfdc9d219df87c9173f0da0a commit 3a8d97611b564b5b25f68c90b543056fc9ae0bec commit 9b79594aa470fd5fe2173d281fd604d11ec8e902 commit e8653e63e834e4c7de60b81b8b24deb7bdd3bf56 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commit 5db89168c408871d306e9fb669e494a1444da8ee commit b26de02cf903b5182588c0df91a6e1b512f7d3f3 commit 79a21fc921d7aafaf69d00b4938435b81bf66022 commit fa6493440f084c5ba8e30dce84158cbfeac86311 commit cf8182d33798966146c7eaab7209b606939a17c5 commit b1231ff7ea0689d04040a44864c265bc11612fa8 commit cfaf51adaf4e0b1850c84e05c81e879dd571c17c commit 9b1c673a1648cc3501a3b7719db2bec931cf00f7 commit 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d Signed-off-by: Robert Foss <rfoss@redhat.com>
2025-04-01 09:44:50 +00:00
display/intel_bo.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_bw.o \
display/intel_cdclk.o \
display/intel_color.o \
display/intel_combo_phy.o \
display/intel_connector.o \
drm/i915: refactor some crtc code out of intel display. (v2) There may be more crtc code that can be pulled out, but this is a good start. v2: move plane before this. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_crtc.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eacbe964f90d189c5940c12af5e09091b37a19c3.1610622609.git.jani.nikula@intel.com
2021-01-14 11:13:45 +00:00
display/intel_crtc.o \
Merge DRM changes from upstream v5.19..v6.0 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.0 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/hyperv/hyperv_drm_drv.c drivers/gpu/drm/mgag200/mgag200_mode.c Conflict resolution: Commit list: commit d10f7117aa43b0b0d1c4b878afafb6d151da441d commit 115fcf5899f7e0b0d3358a22a8cd76b1398642ee commit d8cb49d203556707ff4c3aa05032c4fc7c3ff1a2 commit 9d72b7e2d2ce3746950929a2c54171d183ea89f2 commit 94afc5382669c3a201c5817c47b57a879b6dabce commit aba5825439d7691343aa562dfeaf6616455bcb01 commit a9ec4fd004b84c26207a8cae41662c501c8a284b commit 537d9ed2f6c1dbfe8465365c2f74a855ffad5e6a commit ed3173077d3fa6fd085960aa6347ec30f532bf31 commit b07debc2a8ce7324c85479a28d145eaa05382286 commit 4ce08703a8c4be77b060aefd14eda272f50a45e4 commit 9975af040a04ba9aef33f3ef1ca4e8f04c7223dd commit dfc0312596561ac462308fae32130a0c580b7ac1 commit 37852141965d467a4ae118139b6eee266e7d953c commit 2af243444f9100639451b11d311982279e00cc16 commit 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("drm: xlnx: add <linux/io.h> for readl/writel") Omitted-fix: 395d10ae4d29 ("drm/xlnx: Fix build failure due to missing include") Omitted-fix: 3f61631d47f1 ("take care to handle NULL ->proc_lseek()") Omitted-fix: 5e6723ef3fda ("drm/lcdif: Consistently use plain timings") Omitted-fix: 71c627c0a87a ("drm/lcdif: Clean up debug prints and comments") Omitted-fix: d395fb1999ab ("Revert "drm/amdgpu: move internal vram_mgr function into the C file"") Omitted-fix: ea19684afb54 ("drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers") Omitted-fix: f423fa1bc9fe ("drm/i915/gvt: Add missing vfio_unregister_group_dev() call") Omitted-fix: fcfd3e5fb2f0 ("drm/lcdif: Clean up headers") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:48:10 +00:00
display/intel_crtc_state_dump.o \
drm/i915: refactor cursor code out of i915_display.c This file is a monster, let's start simple, the cursor plane code seems pretty standalone, and splits out easily enough. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_cursor.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201221090449.8288-4-jani.nikula@intel.com
2020-12-21 09:04:48 +00:00
display/intel_cursor.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_display.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_display_driver.o \
display/intel_display_irq.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_display_params.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_display_power.o \
Merge DRM changes from upstream v5.18..v5.19 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.19 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c drivers/gpu/drm/amd/amdgpu/dce_v8_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/bridge/Kconfig drivers/gpu/drm/bridge/analogix/analogix_dp_core.c drivers/gpu/drm/bridge/chipone-icn6211.c drivers/gpu/drm/drm_edid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/drm_format_helper.c drivers/gpu/drm/i915/gt/intel_gsc.c drivers/gpu/drm/i915/gvt/gvt.h drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/i915_driver.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_gvt_mmio_table.c drivers/gpu/drm/mgag200/mgag200_mode.c drivers/gpu/drm/solomon/ssd130x.c drivers/gpu/drm/vmwgfx/vmwgfx_fb.c include/drm/i915_drm.h Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index d91dc8b0effc,30fe847c6664..193c7c83c70f --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -5,6 -5,8 +5,7 @@@ */ #include <linux/dma-resv.h> + #include <linux/highmem.h> -#include <linux/intel-iommu.h> #include <linux/sync_file.h> #include <linux/uaccess.h> Commit list: commit c6e7deb0f092616bd8cb19e8c436b212c64daaab commit 072ce4164f973bc762b25ce9a41636bffe75ab36 commit f8a005eb89720c913e59707d061a1b7e9c8b3358 commit 14ad15296d1fd067e54ad04d96056fe0aed61f2d commit 0225a90981c83408e9606b52a65edee1c6891106 commit 7ad9993b2368f2a861f335184cd2bb1909f13827 commit 772ba8d68515fb8d5414eb714a1d4d446903eb13 commit b4eb76d82a0ea92241f5079874a7aea10c5cc4ae commit 2ff5560e23c863b22afb7db01208a76d9f1d1046 commit 53581504a8e216d435f114a4f2596ad0dfd902fc commit cccc71b552a1040ad3d738d7ec95570801fb0bf6 commit 6c6465fc33c5679a418fb06ff582cd38e68eb5e2 commit c2393a1d8bd1a69ff74ee769fa5d36e4900d4fba commit 3dda9ee49ea5d332359ca372728ee13e570b7e04 commit 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90af0ca047f3049c4b46e902f432ad6ef1e2ded6 commit 1c46f3c0759116d70cb424fc227371a254c47b25 commit 7f5ec14a4e07a2a78fbde069709d5c8806882be2 commit a7a47a5dfa9a9692a41764ee9ab4054f12924a42 commit c653c591789b3acfa4bf6ae45d5af4f330e50a91 commit 0c09bc33aa8e9dc867300acaadc318c2f0d85a1e commit 66cee9097e2b74ff3c8cc040ce5717c521a0c3fa commit 9d928d9b78beec5d4b8afde9c144919b979685f2 commit ce156c8a1811c96a243590abd0e9b5a3b72c1f3a commit e65c6a46df94c8d76ea1129eb2d4564670c6f214 Omitted-fix: 0b752df77633 ("drm/rockchip: Fix Kconfig dependencies for display-port encoders") Omitted-fix: 16c8d76abe83 ("dt-bindings: display: bridge: ldb: Fill in reg property") Omitted-fix: 30bdc36b8c77 ("drm/imx/dcss: get rid of HPD warning message") Omitted-fix: 91954c6c904b ("drm/amd/display: Fix mutex lock in dcn10") Omitted-fix: 920169041baa ("drm/sun4i: dw-hdmi: Fix ddc-en GPIO consumer conflict") Omitted-fix: be273ecfbe8a ("drm/vc4: Use newer fence API properly to fix build errors") Omitted-fix: d9927abb4594 ("Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:27:09 +00:00
display/intel_display_power_map.o \
display/intel_display_power_well.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_display_reset.o \
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
display/intel_display_rps.o \
Merge DRM changes from upstream v6.12..v6.13 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.13 RHEL-75951 JIRA: https://issues.redhat.com/browse/RHEL-75951 Conflicts: drivers/dma-buf/udmabuf.c drivers/gpu/drm/Kconfig drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c drivers/gpu/drm/amd/display/Kconfig drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c drivers/gpu/drm/amd/display/dc/inc/core_types.h drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_syncobj.c drivers/gpu/drm/i915/display/intel_display_trace.h drivers/gpu/drm/i915/i915_trace.h drivers/gpu/drm/i915/i915_utils.h drivers/gpu/drm/panthor/panthor_device.h drivers/gpu/drm/xe/xe_devcoredump.c drivers/gpu/drm/xe/xe_devcoredump_types.h drivers/gpu/drm/xe/xe_guc_log.c drivers/gpu/drm/xe/xe_hw_engine.c drivers/gpu/drm/xe/xe_pci.c drivers/gpu/drm/xe/xe_wa.c drivers/gpu/drm/xe/xe_wa_oob.rules include/drm/intel/xe_pciids.h Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index 7f8cbb07a24f,772fc7625639..7c1f72832160 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -211,15 -209,48 +209,53 @@@ config DRM_DEBUG_MODESET_LOC If in doubt, say "N". + config DRM_CLIENT + bool + depends on DRM + help + Enables support for DRM clients. DRM drivers that need + struct drm_client_dev and its interfaces should select this + option. Drivers that support the default clients should + select DRM_CLIENT_SELECTION instead. + + config DRM_CLIENT_LIB + tristate + depends on DRM + select DRM_KMS_HELPER if DRM_FBDEV_EMULATION + select FB_CORE if DRM_FBDEV_EMULATION + help + This option enables the DRM client library and selects all + modules and components according to the enabled clients. + + config DRM_CLIENT_SELECTION + tristate + depends on DRM + select DRM_CLIENT_LIB if DRM_FBDEV_EMULATION + help + Drivers that support in-kernel DRM clients have to select this + option. + + config DRM_CLIENT_SETUP + bool + depends on DRM_CLIENT_SELECTION + help + Enables the DRM client selection. DRM drivers that support the + default clients should select DRM_CLIENT_SELECTION instead. + + menu "Supported DRM clients" + depends on DRM_CLIENT_SELECTION + config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" - depends on DRM + depends on DRM_CLIENT_SELECTION + select DRM_CLIENT + select DRM_CLIENT_SETUP select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT ++ select FB_SYS_IMAGEBLIT default FB help Choose this option if you have a need for the legacy fbdev diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bd0dab9811d1,cd4fac120834..d73f84c53e76 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -33,11 -35,11 +35,10 @@@ #include <linux/iommu.h> #include <linux/pci.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_event.h> #include <drm/drm_crtc_helper.h> - #include <drm/drm_fb_helper.h> #include <drm/drm_probe_helper.h> #include <drm/amdgpu_drm.h> #include <linux/device.h> @@@ -4494,16 -4584,18 +4617,15 @@@ fence_driver_init if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); - px = amdgpu_device_supports_px(ddev); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(ddev)) { + px = true; vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, px); - - if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + } - if (adev->gmc.xgmi.pending_reset) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --cc drivers/gpu/drm/display/drm_dp_mst_topology.c index f0c6d50d8c33,dc4446d589e7..6bff2d5eb59c --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@@ -4184,10 -4188,10 +4191,21 @@@ static int drm_dp_mst_handle_up_req(str out_put_primary: drm_dp_mst_topology_put_mstb(mst_primary); out_clear_reply: - memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx)); - return 0; + reset_msg_rx_state(&mgr->up_req_recv); + return ret; + } + ++static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) ++{ ++ mutex_lock(&mgr->lock); ++ if (mgr->reset_rx_state) { ++ mgr->reset_rx_state = false; ++ reset_msg_rx_state(&mgr->down_rep_recv); ++ reset_msg_rx_state(&mgr->up_req_recv); ++ } ++ mutex_unlock(&mgr->lock); +} + static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --cc drivers/gpu/drm/drm_syncobj.c index 4fcfc0b9b386,4f2ab8a7b50f..0058689f69fa --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@@ -712,19 -712,17 +712,17 @@@ static int drm_syncobj_fd_to_handle(str int fd, u32 *handle) { struct drm_syncobj *syncobj; - struct fd f = fdget(fd); + CLASS(fd, f)(fd); int ret; - if (!f.file) + if (fd_empty(f)) return -EINVAL; - if (f.file->f_op != &drm_syncobj_file_fops) { - fdput(f); + if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - } /* take a reference to put in the idr */ - syncobj = fd_file(f)->private_data; + syncobj = f.file->private_data; drm_syncobj_get(syncobj); idr_preload(GFP_KERNEL); diff --cc drivers/gpu/drm/hyperv/hyperv_drm_drv.c index 7ef4d7ea5468,e0953777a206..34d8d5ef2a62 --- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c @@@ -7,10 -8,9 +8,10 @@@ #include <linux/hyperv.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/screen_info.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_shmem.h> #include <drm/drm_gem_shmem_helper.h> diff --cc drivers/gpu/drm/i915/display/intel_display_trace.h index fbd3f83df807,9bd8f1e505b0..eeb73303e2e0 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@@ -61,10 -102,14 +102,14 @@@ TRACE_EVENT(intel_pipe_disable ), TP_fast_assign( - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc *it__; - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - for_each_intel_crtc(&dev_priv->drm, it__) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, it__) { __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); } @@@ -90,8 -132,8 +132,8 @@@ TRACE_EVENT(intel_crtc_flip_done ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -114,8 -156,8 +156,8 @@@ TRACE_EVENT(intel_pipe_crc ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); @@@ -141,9 -183,9 +183,9 @@@ TRACE_EVENT(intel_cpu_fifo_underrun ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = pipe; + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -166,9 -208,9 +208,9 @@@ TRACE_EVENT(intel_pch_fifo_underrun TP_fast_assign( enum pipe pipe = pch_transcoder; - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - __entry->pipe = pipe; + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -192,8 -234,12 +234,12 @@@ TRACE_EVENT(intel_memory_cxsr TP_fast_assign( struct intel_crtc *crtc; - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - for_each_intel_crtc(&dev_priv->drm, crtc) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, crtc) { __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); } @@@ -232,8 -276,8 +276,8 @@@ TRACE_EVENT(g4x_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; @@@ -279,8 -323,8 +323,8 @@@ TRACE_EVENT(vlv_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->level = wm->level; @@@ -316,8 -360,8 +360,8 @@@ TRACE_EVENT(vlv_fifo_size ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->sprite0_start = sprite0_start; @@@ -345,9 -389,9 +389,9 @@@ TRACE_EVENT(intel_plane_async_flip ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, __dev_name_kms(plane)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; @@@ -373,9 -417,9 +417,9 @@@ TRACE_EVENT(intel_plane_update_noarm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -404,9 -448,9 +448,9 @@@ TRACE_EVENT(intel_plane_update_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -433,9 -477,9 +477,9 @@@ TRACE_EVENT(intel_plane_disable_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); - __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; ++ __assign_str(name, plane->base.name); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -458,11 -502,12 +502,12 @@@ TRACE_EVENT(intel_fbc_activate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -485,11 -530,12 +530,12 @@@ TRACE_EVENT(intel_fbc_deactivate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -512,11 -558,12 +558,12 @@@ TRACE_EVENT(intel_fbc_nuke ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -538,8 -585,8 +585,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_star ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -561,8 -608,8 +608,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_end ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -586,8 -633,8 +633,8 @@@ TRACE_EVENT(intel_pipe_update_start ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->min = crtc->debug.min_vbl; @@@ -614,8 -661,8 +661,8 @@@ TRACE_EVENT(intel_pipe_update_vblank_ev ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = crtc->debug.start_vbl_count; __entry->scanline = crtc->debug.scanline_start; __entry->min = crtc->debug.min_vbl; @@@ -640,8 -687,8 +687,8 @@@ TRACE_EVENT(intel_pipe_update_end ), TP_fast_assign( - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = frame; __entry->scanline = scanline_end; ), diff --cc drivers/gpu/drm/xe/Makefile index b578ef68bc34,bc7a04ce69fd..21a1ecca0fea --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@@ -145,10 -147,9 +147,9 @@@ endi # i915 Display compat #defines and #includes subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ - -I$(src)/display/ext \ - -I$(src)/compat-i915-headers \ + -I$(srctree)/$(src)/display/ext \ + -I$(srctree)/$(src)/compat-i915-headers \ -I$(srctree)/drivers/gpu/drm/i915/display/ \ - -Ddrm_i915_gem_object=xe_bo \ -Ddrm_i915_private=xe_device # Rule to build SOC code shared with i915 diff --cc drivers/gpu/drm/xe/xe_gt_topology.c index 3e113422b88d,df2042db7ee6..f504b1012493 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@@ -129,8 -129,8 +129,20 @@@ static voi load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) { struct xe_device *xe = gt_to_xe(gt); - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3); + u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); + ++ /* ++ * PTL platforms with media version 30.00 do not provide proper values ++ * for the media GT's L3 bank registers. Skip the readout since we ++ * don't have any way to obtain real values. ++ * ++ * This may get re-described as an official workaround in the future, ++ * but there's no tracking number assigned yet so we use a custom ++ * OOB workaround descriptor. ++ */ ++ if (XE_WA(gt, no_media_l3)) ++ return; + /* * PTL platforms with media version 30.00 do not provide proper values * for the media GT's L3 bank registers. Skip the readout since we diff --cc drivers/gpu/drm/xe/xe_guc_log.c index be47780ec2a7,df4cfb698cdb..38db790f254b --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@@ -5,11 -5,14 +5,15 @@@ #include "xe_guc_log.h" + #include <linux/fault-inject.h> + #include <drm/drm_managed.h> +#include <linux/vmalloc.h> + #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_devcoredump.h" + #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_map.h" Commit list: commit 3973a8d052829dcc5193fb6330dcd13c2b7127ca commit 7a5115ba1d691bd14db91d2fcc3ce0b056574ce9 commit c7d84a45f4266e9ff4c61eddde4acbfddb8f6b57 commit eb4accc5234525e2cb2b720187ccaf6db99b705f commit 3742c20958a5b02ecba08d71036bae3e7b9d21b3 commit 2872a57c7ad427d428c6d12e95e55b32bdc8e3b8 commit 9c75b16cabc69adbbfdc9d219df87c9173f0da0a commit 3a8d97611b564b5b25f68c90b543056fc9ae0bec commit 9b79594aa470fd5fe2173d281fd604d11ec8e902 commit e8653e63e834e4c7de60b81b8b24deb7bdd3bf56 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commit 5db89168c408871d306e9fb669e494a1444da8ee commit b26de02cf903b5182588c0df91a6e1b512f7d3f3 commit 79a21fc921d7aafaf69d00b4938435b81bf66022 commit fa6493440f084c5ba8e30dce84158cbfeac86311 commit cf8182d33798966146c7eaab7209b606939a17c5 commit b1231ff7ea0689d04040a44864c265bc11612fa8 commit cfaf51adaf4e0b1850c84e05c81e879dd571c17c commit 9b1c673a1648cc3501a3b7719db2bec931cf00f7 commit 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d Signed-off-by: Robert Foss <rfoss@redhat.com>
2025-04-01 09:44:50 +00:00
display/intel_display_snapshot.o \
drm/i915/display: Extract display workarounds from clock gating init JIRA: https://issues.redhat.com/browse/RHEL-1350 Upstream Status: v6.7-rc1 commit 53dd7b1fb4e54d5f029824636b6d17504a4fe80c Author: Matt Roper <matthew.d.roper@intel.com> AuthorDate: Wed Sep 6 17:10:10 2023 -0700 Commit: Matt Roper <matthew.d.roper@intel.com> CommitDate: Fri Sep 8 15:45:23 2023 -0700 Several of the register updates that are currently done in the clock gating init functions are actually display workarounds that should move into the display-specific part of the code. Furthermore, some of the registers being programmed don't even have anything to do with clock gating at all. Extract the display workarounds for gen11 and later platforms to a dedicated display/intel_display_wa.c file to keep these separate from the SOC / sgunit clock gating that we need on some platforms. The gen11 cutoff here is selected somewhat arbitrarily; this is the point where workarounds were first assigned dedicated lineage numbers that can be easily looked up and confirmed in the modern workaround database. It also avoids any confusion on older platforms where the exact boundaries between display/GT/other IP blocks wasn't as well-defined as it is today. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230907001009.3732474-2-matthew.d.roper@intel.com Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-11-17 18:50:49 +00:00
display/intel_display_wa.o \
drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.h Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210518213444.11420-6-anusha.srivatsa@intel.com
2021-05-18 21:34:44 +00:00
display/intel_dmc.o \
Merge DRM changes from upstream v6.9.11..v6.10 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.10 RHEL-53570 JIRA: https://issues.redhat.com/browse/RHEL-53570 Conflicts: drivers/gpu/drm/i915/display/intel_psr.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/i915/i915_params.h index 038a5bb57446,2eb3f2115ff2..0e675cceb06a --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@@ -49,12 -49,8 +49,11 @@@ struct drm_printer param(int, modeset, -1, 0400) \ param(int, enable_guc, -1, 0400) \ param(int, guc_log_level, -1, 0400) \ + param(int, guc_log_size_crash, -1, 0400) \ + param(int, guc_log_size_debug, -1, 0400) \ + param(int, guc_log_size_capture, -1, 0400) \ param(char *, guc_firmware_path, NULL, 0400) \ param(char *, huc_firmware_path, NULL, 0400) \ - param(char *, dmc_firmware_path, NULL, 0400) \ param(char *, gsc_firmware_path, NULL, 0400) \ param(bool, memtest, false, 0400) \ param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \ Commit list: commit 84a1ed5e67565b09b8fd22a26754d2897de55ce0 commit 3121fed0c51beb8ea7b18ab2ceff1ac9e358ac53 commit a9e483dda3efa5b9aae5d9eef94d2c3a878d9bea commit 30c399529f4c64e9671cba832630629d9cd08bf3 commit 0f9d886f0bf93394b09b1dfe5397f7842c0f48b9 commit 23cf006beac3db89f946a52c962cd16c82066c5c commit 6a0784e6001f42b87af21ab63b3935ef4d6c6407 commit 3f0e14651ab0ca340c4b6f77b2ea615605fcf8f8 commit 1e941c9881ec20f6d0173bcd344a605bb89cb121 commit 5b2b3a0fbb287d862cb39469a0f4826d8073b30e commit db5a5a8338347ef43bb53ccab730cde326d030e8 commit 5a2a90847450f193f681886db56c3ace5a945785 commit f9d9f94cfb25c9be40a6f51fbfdd1131dfc55ded commit 48fef288070b31a6a04ed13c929f1d15ebf52fe5 commit 5d118681d341fbf470d06bf1938d996d3bed6a1d commit 23be0e6e8316aaab6acfe15f035960914f820a2a commit 1732391763634b9e877670ecf2e2268d7323ee15 commit b2121f2bd2232cd0556b2182078d159d81497885 commit 35ed1d2bfff7b1969e7f99f3641a83ea54f037e2 commit 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commit fc932f51926698488f874ddf7d8f18483ca10271 commit 1f006470284598060ca1307355352934400b37ca commit cfbce3bcb2e4aa767b51985672a5bb7aca9b06cf commit 2879b482a91202e20841de2df249ca31500d4f96 commit 3c6f5afd91cfacba9f43fd388f2d88c85195ae32 Signed-off-by: Robert Foss <rfoss@redhat.com>
2024-11-21 22:32:21 +00:00
display/intel_dmc_wl.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_dpio_phy.o \
drm/i915: refactor pll code out into intel_dpll.c This pulls a large chunk of the pll calculation code out of intel_display.c to a new file. One function makes sense to be an inline, otherwise this is pretty much a straight copy cover. Also all the remaining hooks for g45 and older end up the same now. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_dpll.h a bit, de-duped intel_panel_use_ssc().] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/74b58e0572858b5d1734818ca594a23040d7d44f.1610622609.git.jani.nikula@intel.com
2021-01-14 11:13:46 +00:00
display/intel_dpll.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_dpll_mgr.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
display/intel_dpt.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_dpt_common.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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commit aa464957f7e660abd554f2546a588f6533720e21 commit 78fed39af1af5d702089fe53076c524646e64997 commit a2fbfd517117157e99160ff1b39b171872dcba07 commit fc74881c28d314b10efac016ef49df4ff40b8b97 commit bf67014d6bda16a72deea11dbbff2a97c705ca92 commit 19e66d512e4182a0461530fa3159638e0f55d97e commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5 commit 7807bf28fe02a76bf112916c6b9194f282f5e43c commit 67f74302f45d5d862f22ced3297624e50ac352f0 commit 4d625a97a7e96be016382e3bb0a3cead05fec153 commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c commit d46f329a3f6048e04736e86cb13c880645048792 commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1 commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464 commit ebae8973884ee9ac703b3bfe34cabbb118b18538 commit 2eb82577a16d4c8eb31e4ed520649850bb95b223 commit d97e631af2db84c8c9d63abf68d487d0bb559e4c commit a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
display/intel_drrs.o \
drm/i915/dsb: DSB context creation. This patch adds a function, which will internally get the gem buffer for DSB engine. The GEM buffer is from global GTT, and is mapped into CPU domain, contains the data + opcode to be feed to DSB engine. v1: Initial version. v2: - removed some unwanted code. (Chris) - Used i915_gem_object_create_internal instead of _shmem. (Chris) - cmd_buf_tail removed and can be derived through vma object. (Chris) v3: vma realeased if i915_gem_object_pin_map() failed. (Shashank) v4: for simplification and based on current usage added single dsb object in intel_crtc. (Shashank) v5: seting NULL to cmd_buf moved outside of mutex in dsb-put(). (Shashank) v6: - refcount machanism added. - Used atomic_add_return and atomic_dec_and_test instead of atomic_inc and atomic_dec. (Jani) Cc: Imre Deak <imre.deak@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> [Jani: added #include <linux/types.h> while pushing] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190920115930.27829-3-animesh.manna@intel.com
2019-09-20 11:59:22 +00:00
display/intel_dsb.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_dsb_buffer.o \
drm/i915/intel_fb: Pull FB plane functions from intel_display_types.h Start collecting all the FB plane related functions into a new intel_fb.c file. v2: Drop display/ part of header includes. (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210325214808.2071517-7-imre.deak@intel.com
2021-03-25 21:47:49 +00:00
display/intel_fb.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_fb_bo.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
display/intel_fb_pin.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_fbc.o \
drm/i915: split fdi code out from intel_display.c This just refactors out the fdi code to a separate file. Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: cleaned up intel_fdi.h a bit.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f9d52c3d91f0973af308ede16e266fc9b753ecf9.1610622609.git.jani.nikula@intel.com
2021-01-14 11:13:47 +00:00
display/intel_fdi.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_fifo_underrun.o \
display/intel_frontbuffer.o \
drm/i915: Introduce better global state handling Our current global state handling is pretty ad-hoc. Let's try to make it better by imitating the standard drm core private object approach. The reason why we don't want to directly use the private objects is locking; Each private object has its own lock so if we introduce any global private objects we get serialized by that single lock across all pipes. The global state apporoach instead uses a read/write lock type of approach where each individual crtc lock counts as a read lock, and grabbing all the crtc locks allows one write access. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200120174728.21095-15-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-01-20 17:47:24 +00:00
display/intel_global_state.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_hdcp.o \
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
display/intel_hdcp_gsc.o \
Merge DRM changes from upstream v6.6..v6.7 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.7 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drivers/gpu/drm/amd/amdgpu/psp_v13_0.c drivers/gpu/drm/amd/amdgpu/soc15.c drivers/gpu/drm/amd/amdkfd/kfd_svm.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h drivers/gpu/drm/amd/display/modules/power/power_helpers.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/display/intel_cdclk.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/display/intel_display_device.h drivers/gpu/drm/i915/display/intel_display_power_well.c drivers/gpu/drm/i915/display/intel_display_types.h drivers/gpu/drm/i915/display/intel_psr.c drivers/gpu/drm/i915/gt/intel_ggtt.c drivers/gpu/drm/i915/gt/intel_mocs.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_uvmm.h drivers/gpu/drm/nouveau/nvif/outp.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8e63aacb595b,93cf73d6fa11..23bf36604848 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -32,9 -32,8 +32,7 @@@ #include <linux/slab.h> #include <linux/iommu.h> #include <linux/pci.h> - #include <linux/devcoredump.h> - #include <generated/utsrelease.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> @@@ -4029,10 -4374,19 +4369,14 @@@ void amdgpu_device_fini_sw(struct amdgp kfree(adev->bios); adev->bios = NULL; + + kfree(adev->fru_info); + adev->fru_info = NULL; + - px = amdgpu_device_supports_px(adev_to_drm(adev)); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(adev_to_drm(adev))) { vga_switcheroo_unregister_client(adev->pdev); - - if (px) vga_switcheroo_fini_domain_pm_ops(adev->dev); - + } if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_unregister(adev->pdev); diff --cc drivers/gpu/drm/amd/display/dc/core/dc.c index 8cdf380bf366,5c1185206645..ebc7b005b7d3 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@@ -5285,3 -5518,20 +5518,19 @@@ void dc_set_edp_power(const struct dc * edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn); } + /* + ***************************************************************************** + * dc_get_power_profile_for_dc_state() - extracts power profile from dc state + * + * Called when DM wants to make power policy decisions based on dc_state + * + ***************************************************************************** + */ + struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) + { + struct dc_power_profile profile = { 0 }; + + profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + + return profile; + } - diff --cc drivers/gpu/drm/amd/display/dc/link/link_factory.c index 2c366866f570,7abfc67d10a6..ff7801aa552a --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@@ -367,27 -368,6 +368,30 @@@ static enum transmitter translate_encod } } +static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link) +{ + uint8_t pwrseq_inst = 0xF; ++ struct dc_context *dc_ctx = link->dc->ctx; ++ ++ DC_LOGGER_INIT(dc_ctx->logger); + + switch (link->eng_id) { + case ENGINE_ID_DIGA: + pwrseq_inst = 0; + break; + case ENGINE_ID_DIGB: + pwrseq_inst = 1; + break; + default: + DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", link->eng_id); + ASSERT(false); + break; + } + + return pwrseq_inst; +} + + static void link_destruct(struct dc_link *link) { int i; diff --cc drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 56e4c312cb7a,e1a5ee911dbb..869143b8f090 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@@ -742,11 -817,19 +818,11 @@@ static int smu_late_init(void *handle * handle the switch automatically. Driver involvement * is unnecessary. */ - if (!smu->dc_controlled_by_gpio) { - ret = smu_set_power_source(smu, - adev->pm.ac_power ? SMU_POWER_SOURCE_AC : - SMU_POWER_SOURCE_DC); - if (ret) { - dev_err(adev->dev, "Failed to switch to %s mode!\n", - adev->pm.ac_power ? "AC" : "DC"); - return ret; - } - } + adev->pm.ac_power = power_supply_is_system_supplied() > 0; + smu_set_ac_dc(smu); - if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || - (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) return 0; if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { diff --cc drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index d6336a1e8e43,5748a8581af4..86aa88df6b7a --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@@ -1387,9 -1381,8 +1381,8 @@@ static struct i2c_driver anx78xx_drive .name = "anx7814", .of_match_table = anx78xx_match_table, }, - .probe = anx78xx_i2c_probe, + .probe_new = anx78xx_i2c_probe, .remove = anx78xx_i2c_remove, - .id_table = anx78xx_id, }; module_i2c_driver(anx78xx_driver); diff --cc drivers/gpu/drm/bridge/lvds-codec.c index 67368f23d4aa,991732c4b629..19cccce2acf8 --- a/drivers/gpu/drm/bridge/lvds-codec.c +++ b/drivers/gpu/drm/bridge/lvds-codec.c @@@ -5,9 -5,9 +5,10 @@@ */ #include <linux/gpio/consumer.h> + #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --cc drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 4291798bd70f,824fb3c65742..778da07b7f81 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@@ -12,8 -12,10 +12,10 @@@ #include <linux/component.h> #include <linux/debugfs.h> #include <linux/iopoll.h> + #include <linux/math64.h> + #include <linux/media-bus-format.h> #include <linux/module.h> -#include <linux/platform_device.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index e7083689cf4d,1fd068e6e26c..8a82a7ebaf1e --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -701,20 -737,10 +741,11 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); - /* - * Seamless M/N update may need to update frame timings. - * - * FIXME Should be synchronized with the start of vblank somehow... - */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); - - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) - return; + goto out; if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { diff --cc drivers/gpu/drm/nouveau/nouveau_uvmm.h index ece2ea29e054,a308c59760a5..b11795dd655e --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.h +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.h @@@ -3,8 -3,8 +3,9 @@@ #ifndef __NOUVEAU_UVMM_H__ #define __NOUVEAU_UVMM_H__ - #include <drm/drm_gpuva_mgr.h> +#include <linux/maple_tree.h> + #include <drm/drm_gpuvm.h> + #include "nouveau_drv.h" struct nouveau_uvmm { Commit list: commit efcb492d77c42734aaf24aae02b4973323dc15d0 commit 78f46ecd9be8ec85a177c15d6188e1555657ba86 commit 192948f6a923bedf461b4aa09e70a25cfb8a6041 commit 96413b355a49fd684430a230479bd231d977894f commit 15f389da11257b806da75a070cfa41ca0cc15aae commit cc018c2626745d2e52273f941f9db222101aa11a commit b77d010d82eac31e161833b8e75d2983e3056171 commit 4bed08d99c681f1564e4a633b33d8a6d0446c706 commit b31f784ffff96643fa6dec31b182a3466cf4139e commit 5976a28b344ecb6810882a01b76a320cac21d307 commit 58554dbf0991da6a2847b3159594f6306bff978b commit 95c23e2085f28e2c763ca202fdc37a1392982c16 commit 199cf07ebd2b0d41185ac79b895547d45610b681 commit 637d3fdc109a63ed3d3864b9ffe1ae50ef57d03e commit d19859a042668277d79f8df0165ed75011f11e6d commit f5d8f9c0d8b4bc8ad7e7b23a9f4d116e99202dd3 commit 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commit 11f9eb899ecc8c02b769cf8d2532ba12786a7af7 commit d4b6e7f582e29acac17bcaf7f7771138d72f89d2 commit 2bd7a06a1208aaacb4e7a2a5436c23bce8d70801 commit ee11d2d37f5c05bd7bf5ccc820a58f48423d032b commit 9cdef4f720376ef0fb0febce1ed2377c19e531f9 commit 0cc9e952e6efa1f6f2597a305ea20d4b6ecc7573 commit ff5ab42b7926682080d87993a850a4d4b8d379e0 commit faa21f4c20960fee268bdb0fe977ed0edb6685fe commit 7e725c20fea8914ef1829da777f517ce1a93d388 commit 21f6137c64c65d6808c4a81006956197ca203383 commit 202260f64519e591b5cd99626e441b6559f571a3 commit 21ff3cc851565c01cbc25c64e506fe99c26b51aa commit 43d7e8b0127cc5f77916067431f31b424156cf74 commit f71cee97a644a6dfa3bc0eb69e29a53eab49b98d commit ed9895d8d45af78866acea5f5b42f6041abc9d4a commit 24ab185d9804e48041b370fa9354d6d941ce0a32 commit 34ce62a51e65a8b1fce0eb64dea2719c9429b306 commit 7854ea0e408d7f2e8faaada1773f3ddf9cb538f5 commit a9b9b42b54b2c9251144b3b9d4ebcd83e5f8c230 commit 3108cc03236b54c56e34de01227cdacf764c50a8 commit cf22fc2846cee83061082fa373574d6cdeb4c006 commit 59f6a3d8db2573aba994b95074d8f9911c969bcb commit 4ae3a20102b20d1927737e1a78615386d58e194d commit 9c9dd22ba5d747cceee3d1b1757448b5c48ac705 commit eacabb5462717a52fccbbbba458365a4f5e61f35 commit eb284f4b37817d2038fdfe1a9d51769730ab7b5f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 03:58:11 +00:00
display/intel_hdcp_gsc_message.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_hotplug.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_hotplug_irq.o \
Merge DRM changes from upstream v6.1..v6.2 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.2 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/dma-buf/dma-buf.c drivers/gpu/drm/amd/amdgpu/mes_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c drivers/gpu/drm/ast/ast_drv.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/i915/gt/intel_engine_cs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/selftest_slpc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_huc.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/i915/pxp/intel_pxp_huc.c drivers/gpu/drm/i915/pxp/intel_pxp_tee.c drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c drivers/gpu/drm/vmwgfx/vmwgfx_kms.c Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st init_waitqueue_head(&dmabuf->poll); dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll; dmabuf->cb_in.active = dmabuf->cb_out.active = 0; + INIT_LIST_HEAD(&dmabuf->attachments); if (!resv) { - resv = (struct dma_resv *)&dmabuf[1]; - dma_resv_init(resv); + dmabuf->resv = (struct dma_resv *)&dmabuf[1]; + dma_resv_init(dmabuf->resv); + } else { + dmabuf->resv = resv; } - dmabuf->resv = resv; - file = dma_buf_getfile(dmabuf, exp_info->flags); - if (IS_ERR(file)) { - ret = PTR_ERR(file); + ret = dma_buf_stats_setup(dmabuf, file); + if (ret) goto err_dmabuf; - } + file->f_mode |= FMODE_LSEEK; + file->private_data = dmabuf; + file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; - mutex_init(&dmabuf->lock); - INIT_LIST_HEAD(&dmabuf->attachments); - mutex_lock(&db_list.lock); list_add(&dmabuf->list_node, &db_list.head); mutex_unlock(&db_list.lock); diff --cc drivers/gpu/drm/bridge/ite-it6505.c index 99123eec4551,21a9b8422bda..c13fb0bc6260 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_ DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev)); debugfs_init(it6505); + pm_runtime_enable(dev); + + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->aux.name = "DP-AUX"; + it6505->aux.dev = dev; + it6505->aux.transfer = it6505_aux_transfer; + drm_dp_aux_init(&it6505->aux); + it6505->bridge.funcs = &it6505_bridge_funcs; it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 21cd1a4e1823,a0740308555d..bf68f2330dd9 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); /* Wa_18018781329:dg2,pvc */ - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); + wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); + } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18017747507:dg2 */ + wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); } + + if (IS_DG2(i915)) { + /* + * Wa_16011620976:dg2_g11 + * Wa_22015475538:dg2 + */ + wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + } } static void diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 4d1cc383b681,410905da8e97..e8d1bd04d2a2 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -291,16 -350,17 +361,55 @@@ out } void intel_huc_fini(struct intel_huc *huc) + { + /* + * the fence is initialized in init_early, so we need to clean it up + * even if HuC loading is off. + */ + delayed_huc_load_fini(huc); + + if (intel_uc_fw_is_loadable(&huc->fw)) + intel_uc_fw_fini(&huc->fw); + } + ++void intel_huc_suspend(struct intel_huc *huc) +{ + if (!intel_uc_fw_is_loadable(&huc->fw)) + return; + ++ /* ++ * in the unlikely case that we're suspending before the GSC has ++ * completed its loading sequence, just stop waiting. We'll restart ++ * on resume. ++ */ + delayed_huc_load_complete(huc); ++} + - i915_sw_fence_fini(&huc->delayed_load.fence); - intel_uc_fw_fini(&huc->fw); ++int intel_huc_wait_for_auth_complete(struct intel_huc *huc) ++{ ++ struct intel_gt *gt = huc_to_gt(huc); ++ int ret; ++ ++ ret = __intel_wait_for_register(gt->uncore, ++ huc->status.reg, ++ huc->status.mask, ++ huc->status.value, ++ 2, 50, NULL); ++ ++ /* mark the load process as complete even if the wait failed */ ++ delayed_huc_load_complete(huc); ++ ++ if (ret) { ++ drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret); ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL); ++ return ret; ++ } ++ ++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING); ++ drm_info(&gt->i915->drm, "HuC authenticated\n"); ++ return 0; +} + void intel_huc_suspend(struct intel_huc *huc) { if (!intel_uc_fw_is_loadable(&huc->fw)) Commit list: commit 78a033433a5ae4fee85511ee075bc9a48312c79e commit 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commit 8f32378986218812083b127da5ba42d48297d7c4 commit 2a00299e7447395d0898e7c6214817c06a61a8e8 commit a2a04b515562bbb040e8ae3decae8c1e9ef05327 commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
display/intel_hti.o \
Merge DRM changes from upstream v6.6..v6.7 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.7 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c drivers/gpu/drm/amd/amdgpu/amdgpu_device.c drivers/gpu/drm/amd/amdgpu/psp_v13_0.c drivers/gpu/drm/amd/amdgpu/soc15.c drivers/gpu/drm/amd/amdkfd/kfd_svm.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h drivers/gpu/drm/amd/display/modules/power/power_helpers.c drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/display/intel_cdclk.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/display/intel_display_device.h drivers/gpu/drm/i915/display/intel_display_power_well.c drivers/gpu/drm/i915/display/intel_display_types.h drivers/gpu/drm/i915/display/intel_psr.c drivers/gpu/drm/i915/gt/intel_ggtt.c drivers/gpu/drm/i915/gt/intel_mocs.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/nouveau/nouveau_uvmm.h drivers/gpu/drm/nouveau/nvif/outp.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8e63aacb595b,93cf73d6fa11..23bf36604848 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -32,9 -32,8 +32,7 @@@ #include <linux/slab.h> #include <linux/iommu.h> #include <linux/pci.h> - #include <linux/devcoredump.h> - #include <generated/utsrelease.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> @@@ -4029,10 -4374,19 +4369,14 @@@ void amdgpu_device_fini_sw(struct amdgp kfree(adev->bios); adev->bios = NULL; + + kfree(adev->fru_info); + adev->fru_info = NULL; + - px = amdgpu_device_supports_px(adev_to_drm(adev)); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(adev_to_drm(adev))) { vga_switcheroo_unregister_client(adev->pdev); - - if (px) vga_switcheroo_fini_domain_pm_ops(adev->dev); - + } if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_unregister(adev->pdev); diff --cc drivers/gpu/drm/amd/display/dc/core/dc.c index 8cdf380bf366,5c1185206645..ebc7b005b7d3 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@@ -5285,3 -5518,20 +5518,19 @@@ void dc_set_edp_power(const struct dc * edp_link->dc->link_srv->edp_set_panel_power(edp_link, powerOn); } + /* + ***************************************************************************** + * dc_get_power_profile_for_dc_state() - extracts power profile from dc state + * + * Called when DM wants to make power policy decisions based on dc_state + * + ***************************************************************************** + */ + struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) + { + struct dc_power_profile profile = { 0 }; + + profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + + return profile; + } - diff --cc drivers/gpu/drm/amd/display/dc/link/link_factory.c index 2c366866f570,7abfc67d10a6..ff7801aa552a --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@@ -367,27 -368,6 +368,30 @@@ static enum transmitter translate_encod } } +static uint8_t translate_dig_inst_to_pwrseq_inst(struct dc_link *link) +{ + uint8_t pwrseq_inst = 0xF; ++ struct dc_context *dc_ctx = link->dc->ctx; ++ ++ DC_LOGGER_INIT(dc_ctx->logger); + + switch (link->eng_id) { + case ENGINE_ID_DIGA: + pwrseq_inst = 0; + break; + case ENGINE_ID_DIGB: + pwrseq_inst = 1; + break; + default: + DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", link->eng_id); + ASSERT(false); + break; + } + + return pwrseq_inst; +} + + static void link_destruct(struct dc_link *link) { int i; diff --cc drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 56e4c312cb7a,e1a5ee911dbb..869143b8f090 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@@ -742,11 -817,19 +818,11 @@@ static int smu_late_init(void *handle * handle the switch automatically. Driver involvement * is unnecessary. */ - if (!smu->dc_controlled_by_gpio) { - ret = smu_set_power_source(smu, - adev->pm.ac_power ? SMU_POWER_SOURCE_AC : - SMU_POWER_SOURCE_DC); - if (ret) { - dev_err(adev->dev, "Failed to switch to %s mode!\n", - adev->pm.ac_power ? "AC" : "DC"); - return ret; - } - } + adev->pm.ac_power = power_supply_is_system_supplied() > 0; + smu_set_ac_dc(smu); - if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || - (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) return 0; if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { diff --cc drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index d6336a1e8e43,5748a8581af4..86aa88df6b7a --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@@ -1387,9 -1381,8 +1381,8 @@@ static struct i2c_driver anx78xx_drive .name = "anx7814", .of_match_table = anx78xx_match_table, }, - .probe = anx78xx_i2c_probe, + .probe_new = anx78xx_i2c_probe, .remove = anx78xx_i2c_remove, - .id_table = anx78xx_id, }; module_i2c_driver(anx78xx_driver); diff --cc drivers/gpu/drm/bridge/lvds-codec.c index 67368f23d4aa,991732c4b629..19cccce2acf8 --- a/drivers/gpu/drm/bridge/lvds-codec.c +++ b/drivers/gpu/drm/bridge/lvds-codec.c @@@ -5,9 -5,9 +5,10 @@@ */ #include <linux/gpio/consumer.h> + #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> diff --cc drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 4291798bd70f,824fb3c65742..778da07b7f81 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@@ -12,8 -12,10 +12,10 @@@ #include <linux/component.h> #include <linux/debugfs.h> #include <linux/iopoll.h> + #include <linux/math64.h> + #include <linux/media-bus-format.h> #include <linux/module.h> -#include <linux/platform_device.h> +#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index e7083689cf4d,1fd068e6e26c..8a82a7ebaf1e --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -701,20 -737,10 +741,11 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); - /* - * Seamless M/N update may need to update frame timings. - * - * FIXME Should be synchronized with the start of vblank somehow... - */ - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); - - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) - return; + goto out; if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { diff --cc drivers/gpu/drm/nouveau/nouveau_uvmm.h index ece2ea29e054,a308c59760a5..b11795dd655e --- a/drivers/gpu/drm/nouveau/nouveau_uvmm.h +++ b/drivers/gpu/drm/nouveau/nouveau_uvmm.h @@@ -3,8 -3,8 +3,9 @@@ #ifndef __NOUVEAU_UVMM_H__ #define __NOUVEAU_UVMM_H__ - #include <drm/drm_gpuva_mgr.h> +#include <linux/maple_tree.h> + #include <drm/drm_gpuvm.h> + #include "nouveau_drv.h" struct nouveau_uvmm { Commit list: commit efcb492d77c42734aaf24aae02b4973323dc15d0 commit 78f46ecd9be8ec85a177c15d6188e1555657ba86 commit 192948f6a923bedf461b4aa09e70a25cfb8a6041 commit 96413b355a49fd684430a230479bd231d977894f commit 15f389da11257b806da75a070cfa41ca0cc15aae commit cc018c2626745d2e52273f941f9db222101aa11a commit b77d010d82eac31e161833b8e75d2983e3056171 commit 4bed08d99c681f1564e4a633b33d8a6d0446c706 commit b31f784ffff96643fa6dec31b182a3466cf4139e commit 5976a28b344ecb6810882a01b76a320cac21d307 commit 58554dbf0991da6a2847b3159594f6306bff978b commit 95c23e2085f28e2c763ca202fdc37a1392982c16 commit 199cf07ebd2b0d41185ac79b895547d45610b681 commit 637d3fdc109a63ed3d3864b9ffe1ae50ef57d03e commit d19859a042668277d79f8df0165ed75011f11e6d commit f5d8f9c0d8b4bc8ad7e7b23a9f4d116e99202dd3 commit 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commit 11f9eb899ecc8c02b769cf8d2532ba12786a7af7 commit d4b6e7f582e29acac17bcaf7f7771138d72f89d2 commit 2bd7a06a1208aaacb4e7a2a5436c23bce8d70801 commit ee11d2d37f5c05bd7bf5ccc820a58f48423d032b commit 9cdef4f720376ef0fb0febce1ed2377c19e531f9 commit 0cc9e952e6efa1f6f2597a305ea20d4b6ecc7573 commit ff5ab42b7926682080d87993a850a4d4b8d379e0 commit faa21f4c20960fee268bdb0fe977ed0edb6685fe commit 7e725c20fea8914ef1829da777f517ce1a93d388 commit 21f6137c64c65d6808c4a81006956197ca203383 commit 202260f64519e591b5cd99626e441b6559f571a3 commit 21ff3cc851565c01cbc25c64e506fe99c26b51aa commit 43d7e8b0127cc5f77916067431f31b424156cf74 commit f71cee97a644a6dfa3bc0eb69e29a53eab49b98d commit ed9895d8d45af78866acea5f5b42f6041abc9d4a commit 24ab185d9804e48041b370fa9354d6d941ce0a32 commit 34ce62a51e65a8b1fce0eb64dea2719c9429b306 commit 7854ea0e408d7f2e8faaada1773f3ddf9cb538f5 commit a9b9b42b54b2c9251144b3b9d4ebcd83e5f8c230 commit 3108cc03236b54c56e34de01227cdacf764c50a8 commit cf22fc2846cee83061082fa373574d6cdeb4c006 commit 59f6a3d8db2573aba994b95074d8f9911c969bcb commit 4ae3a20102b20d1927737e1a78615386d58e194d commit 9c9dd22ba5d747cceee3d1b1757448b5c48ac705 commit eacabb5462717a52fccbbbba458365a4f5e61f35 commit eb284f4b37817d2038fdfe1a9d51769730ab7b5f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 03:58:11 +00:00
display/intel_link_bw.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_load_detect.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_lpe_audio.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit eaee1c08586395182e0004b3512a2f83570ea461 commit 63b685efaa4d6b9db388857a2e6f5f5f11454f8d commit e24e6d695377ca70008ffc39695c3975b3e177b6 commit 16fc9c08f0ec7b1c95f1ea4a16097acdb3fc943d commit 404c3acda4b65924c05bc63242e94f954f84c165 commit 57b5482bff9e4f60069a8c0de91bb397612ce059 commit ec280042094c3f700d7321e7163591c6eac72274 commit 1dcd7aac31842028beb5fa2531fd54ce0d588b17 commit 68f5f78d0fe08f277a3aea9ad28508a7f243de6a commit e0980b8d82d1306251bcd67b693e008bb6c89512 commit e006df050606785aa7d04cd47f913d9c6ce4669d commit 01c2be8e1b97ee4891d1e1ffb7758897d441bb3c commit b6f4b3a1474d8bed9fad2b4d681368710375bbe9 commit 37c8cabfcc5ce2c06baf0a2d0176043b0b256e49 commit d6fff836c0e0502a569811c7708aed0762e04337 commit ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482 commit b90b044c64f669cb20919fb5e5673933de59c653 commit 1bf3836383e6957ac848ee81eb691820c862b3d6 commit 99cc528ebe923d04767e9979665a0824727376ba commit 17e05aeb3b987a17b2ee5185264bec5db1d0c746 commit 6a98560755636b07ca54bf9cea6435b8e82b57d5 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_modeset_lock.o \
Merge DRM changes from upstream v5.19..v6.0 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.0 2115876 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2115876 Conflicts: drivers/gpu/drm/hyperv/hyperv_drm_drv.c drivers/gpu/drm/mgag200/mgag200_mode.c Conflict resolution: Commit list: commit d10f7117aa43b0b0d1c4b878afafb6d151da441d commit 115fcf5899f7e0b0d3358a22a8cd76b1398642ee commit d8cb49d203556707ff4c3aa05032c4fc7c3ff1a2 commit 9d72b7e2d2ce3746950929a2c54171d183ea89f2 commit 94afc5382669c3a201c5817c47b57a879b6dabce commit aba5825439d7691343aa562dfeaf6616455bcb01 commit a9ec4fd004b84c26207a8cae41662c501c8a284b commit 537d9ed2f6c1dbfe8465365c2f74a855ffad5e6a commit ed3173077d3fa6fd085960aa6347ec30f532bf31 commit b07debc2a8ce7324c85479a28d145eaa05382286 commit 4ce08703a8c4be77b060aefd14eda272f50a45e4 commit 9975af040a04ba9aef33f3ef1ca4e8f04c7223dd commit dfc0312596561ac462308fae32130a0c580b7ac1 commit 37852141965d467a4ae118139b6eee266e7d953c commit 2af243444f9100639451b11d311982279e00cc16 commit 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("drm: xlnx: add <linux/io.h> for readl/writel") Omitted-fix: 395d10ae4d29 ("drm/xlnx: Fix build failure due to missing include") Omitted-fix: 3f61631d47f1 ("take care to handle NULL ->proc_lseek()") Omitted-fix: 5e6723ef3fda ("drm/lcdif: Consistently use plain timings") Omitted-fix: 71c627c0a87a ("drm/lcdif: Clean up debug prints and comments") Omitted-fix: d395fb1999ab ("Revert "drm/amdgpu: move internal vram_mgr function into the C file"") Omitted-fix: ea19684afb54 ("drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers") Omitted-fix: f423fa1bc9fe ("drm/i915/gvt: Add missing vfio_unregister_group_dev() call") Omitted-fix: fcfd3e5fb2f0 ("drm/lcdif: Clean up headers") Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-11-02 15:48:10 +00:00
display/intel_modeset_setup.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_modeset_verify.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_overlay.o \
Merge DRM changes from upstream v5.16..v5.17 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.17 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/Makefile drivers/gpu/drm/i915/gem/i915_gem_pages.c drivers/gpu/drm/i915/gt/intel_gt.c drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c Conflict resolution: diff --cc drivers/gpu/drm/Makefile index 0dff40bb863c,ec2ef2cce11c..301a44dc18e3 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@@ -127,3 -134,8 +134,4 @@@ obj-$(CONFIG_DRM_TIDSS) += tidss obj-y += xlnx/ obj-y += gud/ obj-$(CONFIG_DRM_HYPERV) += hyperv/ + obj-$(CONFIG_DRM_SPRD) += sprd/ - -# Enable shims for the RHEL DRM backport -subdir-ccflags-y += -DRH_DRM_BACKPORT -drm-y += drm_backport.o Commit list: commit 107fe904302092c683cf5462b4af3cb3cfa40998 commit a1a98689301b9af0313e4c1ba44558e8b67ff76e commit befe5404a00b3b1547c944738df4a9229909bdc9 commit 8a12b170558aabb31cc98fda0da6a56b518cadaa commit 334f74ee85dc26a50c1a2b0da82517595191f92f commit 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commit 08783aa7693f55619859f4f63f384abf17cb58c5 commit 26d3474348293dc752c55fe6d41282199f73714c commit 62929726ef0ec72cbbe9440c5d125d4278b99894 commit f1ef17011c765495c876fa75435e59eecfdc1ee4 commit c9585249c245e23580a2c3edbc8f14d9d7173f12 commit 8fdb19679722a02fe21642d39710c701d2ed567a commit 804f468853179b9b58af05c153c411931aa5b310 commit 3755d35ee1d2454b20b8a1e20d790e56201678a4 commit 40ce1121c1d76daf9048a86e36c83e469281b9fd commit fc1b6ef7bfb3d1d4df868b1c3e0480cacda6cd81 commit a8253684eb4b30abd3faf055bc475c23da748dc6 commit 3c3384050d68570f9de0fec9e58824decfefba7a Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:15:52 +00:00
display/intel_pch_display.o \
display/intel_pch_refclk.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
display/intel_plane_initial.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 3c6bd1b7e2043fb00ce6b622709d176609431406 commit d5712cd22b9cf109fded1b7f178f4c1888c8b84b commit 08fffa74d9772d9538338be3f304006c94dde6f0 commit 730d44e1fa306a20746ad4a85da550662aed9daa commit d3de41ee5febe5c2d9989fe9810bce2bb54a3a8e commit 7ad1dfc144cbf62702fd07838da8fd8a77921083 commit bd60e2eafd8fb053948b6e23e8167baf7a159750 commit 61319b8e3b58a7167cf146313fd4523fe72586bc commit 96b020e2163fb2197266b2f71b1007495206e6bb commit a73ea79a0c94bacfab4df23a1043644d14f56591 commit 90e065677e0362a777b9db97ea21d43a39211399 commit 3bb575572bf498a9d39e9d1ca5c06cc3152928a1 commit 2e91e731f24817bc55f9c9acc95a8939c4077b05 commit a6dea2d64ff92851e68cd4e20a35f6534286e016 commit 616f92d188ee7142a95a52068efdbea82645f859 commit 091ae5473f96ced844af6ba39b94757359b12348 commit 07dd476f6116966cb2006e25fdcf48f0715115ff commit 8ba371c778cbb3f0399b8ba8919bf89e462cdda3 commit fbe8ff726a1de82d87524f306b0f6491e13d7dfa commit ae6546835efaa7195aaaa10e5ff4e695cd82a816 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_pmdemand.o \
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
display/intel_psr.o \
display/intel_quirks.o \
drm/i915: Move the TypeC port handling code to a separate file Move the TypeC port handling functions to a new file for clarity. While at it: - s/icl_tc_port_connected()/intel_tc_port_connected()/ icl_tc_phy_disconnect(), will be unexported later. - s/intel_dp_get_fia_supported_lane_count()/ intel_tc_port_fia_max_lane_count()/ It's used for HDMI legacy mode too. - Simplify function interfaces by passing only dig_port to them. No functional changes. v2: - Fix checkpatch issues: +1/-1 empty lines in intel_tc.c and add missing SPDX to intel_tc.h. (Jani) Cc: Animesh Manna <animesh.manna@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190628143635.22066-4-imre.deak@intel.com
2019-06-28 14:36:15 +00:00
display/intel_sprite.o \
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
display/intel_sprite_uapi.o \
drm/i915/display: abstract all vgaarb access to intel_vga.[ch] Split out the code related to vga client and vgaarb all over the place into new intel_vga.[ch]. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191001152506.7854-1-jani.nikula@intel.com
2019-10-01 15:25:06 +00:00
display/intel_tc.o \
Merge DRM changes from upstream v6.2..v6.3 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.3 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/display/drm_dp_aux_bus.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/i915_irq.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6ff156cd64ae,54933903bcb8..fe2752ec67f7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -1017,10 -1029,10 +1022,11 @@@ int svm_migrate_init(struct amdgpu_devi r = devm_memremap_pages(adev->dev, pgmap); if (IS_ERR(r)) { pr_err("failed to register HMM device memory\n"); + /* Disable SVM support capability */ pgmap->type = 0; - devm_release_mem_region(adev->dev, res->start, resource_size(res)); + if (pgmap->type == MEMORY_DEVICE_PRIVATE) + devm_release_mem_region(adev->dev, res->start, resource_size(res)); return PTR_ERR(r); } diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index b617b27577ef,d5b5d40ed817..710e51d2377f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -686,8 -683,15 +687,16 @@@ void intel_pipe_update_end(struct intel */ intel_vrr_send_push(new_crtc_state); + /* + * Seamless M/N update may need to update frame timings. + * + * FIXME Should be synchronized with the start of vblank somehow... + */ + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) + intel_crtc_update_active_timings(new_crtc_state); + - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; Commit list: commit 7ae2e684854cd955eff8daceff84fea33a1c94be commit 192bb40f030a41ca95c5cff8c9340b725bc7ba8b commit 4b9cc6efeb0684912d518e9953a1d493b2b89a02 commit 3b5130a68df1a513713b027d03125ba11ebc2975 commit 6ebf5caf1fae75634b0564152958ecb433cfa952 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95d939bb97ff9be101ae4ceeb322535589da2190 commit dc30c011469165d57af9adac5baff7d767d20e5c commit dc3421560a67361442f33ec962fc6dd48895a0df commit 3dfa8926efa910d423844bfc0132f70cd07f76e2 commit 1e1d3574e69f70b848f9d50eca2c5ff04931b7ba commit 6b8446859c971a5783a2cdc90adf32e64de3bd23 commit 86d8740dae5a397d8344ae75f8758103c1fcba97 commit 5603effb8295ada8419408d038a34ca89d658229 commit b8ca445f550a9a079134f836466ddda3bfad6108 commit f06b8887e3ef4f50098d3a949aef392c529c831a commit 85e0689eb6b10cd3b2fb455d1b3f4d4d0b13ff78 commit b9a24d8bd51e2db425602fa82d7f4c06aa3db852 commit a552b73f36cb3e59fd2015307fde8ff53874d1af commit cab2932213c5cd72a9e04e5e82002e81b946592b commit 11b3b9f461c5c4f700f6c8da202fcc2fd6418e1f commit e1c71f8f918047ce822dc19b42ab1261ed259fd1 commit 7363d6bedc000f6f9d09cfe498da2f3aca653778 commit c8b5a95b570949536a2b75cd8fc4f1de0bc60629 commit 6d9240c46f7419aa3210353b5f52cc63da5a6440 commit 1e994cc0956b8dabd1b1fef315bbd722733b8aa8 commit 0b5dfe12755f87ec014bb4cc1930485026167430 commit f126f41cec1b6fa04c1d06517ec8f3e19908c5f7 commit 3b1f2be527ce04e7d8dce6fad6be16fa59058713 commit 00a4bd000e78a3a898e60bdc13e2852c8044a38c Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-05-02 06:34:23 +00:00
display/intel_vblank.o \
drm/i915: refactor i915 plane code into separate file. Ville suggested this as a good idea, let's move this before moving the crtc code. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [Jani: fixed i915xx_plane.h standalone build.] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201221110957.18215-1-jani.nikula@intel.com
2020-12-21 11:09:57 +00:00
display/intel_vga.o \
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
display/intel_wm.o \
drm/i915: refactor skylake scaler code into new file. This moves the code from various places and consolidates it into one new file. v2: - rename skl_program_plane -> skl_program_plane_scaler (Ville) - also move skl_pfit_enable, and consequently make some skl_scaler_* functions static to skl_scaler.c (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2fa703ffc7b96a41c392fd5ebbd2e6e4ffb6fb05.1612536383.git.jani.nikula@intel.com
2021-02-05 14:48:42 +00:00
display/skl_scaler.o \
Merge DRM changes from upstream v6.0.8..v6.1 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.1 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c drivers/gpu/drm/amd/amdgpu/amdgpu_job.c drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/i915/display/intel_display.c drivers/gpu/drm/i915/gt/intel_gt_sysfs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_guc_log.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/mgag200/mgag200_pll.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index ecb8db731081,253ea6b159df..6ebed4d58ced --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@@ -162,6 -162,7 +162,8 @@@ #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) ++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) + #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque */ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - uint8_t i; - int j; ++ + int i, j; struct dc_stream_state *stream = NULL; struct dc_plane_state *plane = NULL; uint32_t cursor_size = 0; @@@ -237,24 -236,24 +237,27 @@@ mblk_width = DCN3_2_MBLK_WIDTH; mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; ++ /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - * FLOOR(vp_x_start, blk_width) * * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + - pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + + pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); ++ /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - * FLOOR(vp_y_start, blk_height) * * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c */ mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + - pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) + + pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); ++ num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); diff --cc drivers/gpu/drm/ast/ast_mode.c index b93181a42048,1bc0220e6783..ae5a4cce972f --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@@ -42,9 -40,8 +42,8 @@@ #include <drm/drm_fourcc.h> #include <drm/drm_gem_atomic_helper.h> #include <drm/drm_gem_framebuffer_helper.h> -#include <drm/drm_gem_vram_helper.h> +#include <drm/drm_gem_shmem_helper.h> #include <drm/drm_managed.h> - #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> @@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_crtc_state *crtc_state; - struct ast_crtc_state *ast_crtc_state; + struct drm_device *dev = plane->dev; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_crtc_state *new_crtc_state = NULL; + struct ast_crtc_state *new_ast_crtc_state; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, false, true); - if (ret) + if (ret) { return ret; + } else if (!new_plane_state->visible) { + if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */ + return -EINVAL; + else + return 0; + } - if (!new_plane_state->visible) - return 0; - - ast_crtc_state = to_ast_crtc_state(crtc_state); + new_ast_crtc_state = to_ast_crtc_state(new_crtc_state); - ast_crtc_state->format = new_plane_state->fb->format; + new_ast_crtc_state->format = new_plane_state->fb->format; return 0; } @@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_framebuffer *fb = new_plane_state->fb; - struct drm_crtc_state *crtc_state; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_framebuffer *new_fb = new_plane_state->fb; + struct drm_crtc_state *new_crtc_state = NULL; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, true, true); - if (ret) + if (ret || !new_plane_state->visible) return ret; - if (!new_plane_state->visible) - return 0; - - if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) + if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT) return -EINVAL; return 0; diff --cc drivers/gpu/drm/i915/display/intel_display.c index bd629f2da6eb,de77054195c6..d3bfa2a675b8 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9 else if (DISPLAY_VER(i915) >= 11) pipes = BIT(PIPE_B) | BIT(PIPE_C); else ++ pipes = 0; - return pipes & RUNTIME_INFO(i915)->pipe_mask; + return pipes & INTEL_INFO(i915)->display.pipe_mask; } static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj return !strncmp(kobj->name, "gt", 2); } - static struct intel_gt *kobj_to_gt(struct kobject *kobj) - { - return container_of(kobj, struct intel_gt, sysfs_gt); - } - -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name) { - struct kobject *kobj = &dev->kobj; - /* * We are interested at knowing from where the interface * has been called, whether it's called from gt/ or from diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h index 6bee2c6a894d,6232923a420d..c3a123faee98 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h @@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g struct kobject *dir, const char *name); + static inline struct intel_gt *kobj_to_gt(struct kobject *kobj) + { + return container_of(kobj, struct intel_gt, sysfs_gt); + } + void intel_gt_sysfs_register(struct intel_gt *gt); void intel_gt_sysfs_unregister(struct intel_gt *gt); -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name); #endif /* SYSFS_GT_H */ diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe NULL }; + static ssize_t + default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.min_freq); + } + + static struct kobj_attribute default_min_freq_mhz = + __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL); + + static ssize_t + default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.max_freq); + } + + static struct kobj_attribute default_max_freq_mhz = + __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL); + + static const struct attribute * const rps_defaults_attrs[] = { + &default_min_freq_mhz.attr, + &default_max_freq_mhz.attr, + NULL + }; + -static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj, - const struct attribute * const *attrs) +static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj) { + const struct attribute * const *attrs; + struct attribute *vlv_attr; int ret; if (GRAPHICS_VER(gt->i915) < 6) diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 070cec4ff8a4,3955292483a6..d3ac73c3559f --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc /* hsdes: 1809175790 */ if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine->gt, + cs, GEN12_GFX_CCS_AUX_NV); + + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 1b6479b5bd32,a821e3d405db..21cd1a4e1823 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_ if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14013392000:dg2_g11 */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); + } - /* Wa_16011620976:dg2_g11 */ - wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); + } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14012419201:dg2 */ diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 844dee09a321,1db59eeb34db..1ac0e66d39e5 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i return 0; } +struct scheduling_policy { + /* internal data */ + u32 max_words, num_words; + u32 count; + /* API data */ + struct guc_update_scheduling_policy h2g; +}; + +static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy) +{ + u32 *start = (void *)&policy->h2g; + u32 *end = policy->h2g.data + policy->num_words; + size_t delta = end - start; + + return delta; +} + +static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy) +{ + policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV; + policy->max_words = ARRAY_SIZE(policy->h2g.data); + policy->num_words = 0; + policy->count = 0; + + return policy; +} + +static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy, + u32 action, u32 *data, u32 len) +{ + u32 *klv_ptr = policy->h2g.data + policy->num_words; + + GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words); + *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) | + FIELD_PREP(GUC_KLV_0_LEN, len); + memcpy(klv_ptr, data, sizeof(u32) * len); + policy->num_words += 1 + len; + policy->count++; +} + +static int __guc_action_set_scheduling_policies(struct intel_guc *guc, + struct scheduling_policy *policy) +{ + int ret; + + ret = intel_guc_send(guc, (u32 *)&policy->h2g, + __guc_scheduling_policy_action_size(policy)); + if (ret < 0) + return ret; + + if (ret != policy->count) { + drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!", + ret, policy->count); + if (ret > policy->count) + return -EPROTO; + } + + return 0; +} + +static int guc_init_global_schedule_policy(struct intel_guc *guc) +{ + struct scheduling_policy policy; + struct intel_gt *gt = guc_to_gt(guc); + intel_wakeref_t wakeref; + int ret = 0; + + if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0)) + return 0; + + __guc_scheduling_policy_start_klv(&policy); + + with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref) { + u32 yield[] = { + GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION, + GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO, + }; + + __guc_scheduling_policy_add_klv(&policy, + GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD, + yield, ARRAY_SIZE(yield)); + + ret = __guc_action_set_scheduling_policies(guc, &policy); + if (ret) + i915_probe_error(gt->i915, + "Failed to configure global scheduling policies: %pe!\n", + ERR_PTR(ret)); + } + + return ret; +} + void intel_guc_submission_enable(struct intel_guc *guc) { + struct intel_gt *gt = guc_to_gt(guc); + + /* Enable and route to GuC */ + if (GRAPHICS_VER(gt->i915) >= 12) + intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, + GUC_SEM_INTR_ROUTE_TO_GUC | + GUC_SEM_INTR_ENABLE_ALL); + guc_init_lrc_mapping(guc); guc_init_engine_stats(guc); + guc_init_global_schedule_policy(guc); } void intel_guc_submission_disable(struct intel_guc *guc) diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index fb309ae43001,b91ad4aede1f..24aac2f32dd1 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@@ -339,6 -347,6 +347,7 @@@ bad fw_blobs[i].blob.patch); uc_fw->file_selected.path = NULL; ++ } } } diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c index 098955526b68,c481daa4bbce..38a0ba4a1b3f --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi st7701->dsi = dsi; st7701->desc = desc; - return mipi_dsi_attach(dsi); + ret = mipi_dsi_attach(dsi); + if (ret) + goto err_attach; + + return 0; + +err_attach: + drm_panel_remove(&st7701->panel); + return ret; } - static int st7701_dsi_remove(struct mipi_dsi_device *dsi) + static void st7701_dsi_remove(struct mipi_dsi_device *dsi) { struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); Commit list: commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f commit 6dc548745d5b5102e3c53dc5097296ac270b6c69 commit 859161b952a453b86362f168fadef72a8ba31a05 commit d72ac4bbf4cc8f6b50526ce400861f176659884f commit 1fd452c403ca2cd9dcbd8465f9f72be52e15ac1a commit 79abca2b399009eb8d12c652d0f0f7a9c7a06289 commit 96dc635d5538055cb6ccd7b6e9290dfcfc385f97 commit dc1dc76bd9a48c6aba3efae5eadb9a884043966e commit 356d2c8e76ebb1134a0685ce4b923d8201337475 commit 4c59b0805e9bf873fd3f5dca4fc53d8c220e39b4 commit e5bd7e3e4a68f0befe53f59954b25eec9a792d60 commit ba71593217b5b03c9e3385b268ff8613a71fc6ce commit 0a2486f85e0cfa6439116abb9078ab888a619746 commit 8aba4d30520ed656065eb36f0628109bdea385ee commit d093100b425df6fe400881f2e62c3f0be7bf18cf commit b92db7e4fe740daab858366faff1f992d53d3ff4 commit 0c05fcd3b45d6769c496fc6e2b88d18fc78ebe11 commit a6aa679a70e9d8fa4ad3f519c060db9bb186e21c commit 6de745238aa30529778a26622a430dfcb171b089 commit d395fb1999abb7eaa3fb5fd2107cae0f1e41e6d0 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commit a26a54fbe32b564ff868710d59fbe1a387a2cc7c commit f2e1aa267f12b82e03927d1e918d2844ddd3eea5 commit 3cb93f390453cde4d6afda1587aaa00e75e09617 commit a6e1775da04ab042bc9e2e42399fa25714c253da commit 602ad43c3cd8f15cbb25ce9bb494129edb2024ed commit ecb41b71ef90cf4741bcc3286b769dda746b67e6 commit 9e2c5c651a63baaa39005070481d39dcf5b0893a commit b65a648865c4a1e717c4f56f5025546b9553189a commit e57702069b26b8601a33fdc0c9bbe40c6bb9c72f commit ed14d225cc7c842f6d4d5a3009f71a44f5852d09 commit 2f3830544a89af2e72e7fd3d6ca44dd9cffec197 commit 3c1ea6a5f4f55d4e376675dda16945eb5d9bb4de commit a8899b8728013c7b2456f0bfa20e5fea85ee0fd1 commit 12b8b046e4c9de40fa59b6f067d6826f4e688f68 commit 8c115864501fc09932cdfec53d9ec1cde82b4a28 commit 04aa64375f48a5d430b5550d9271f8428883e550 commit 6f6cb1714365a07dbc66851879538df9f6969288 commit d3d6b1bf85aefe0ebc0624574b3bb62f0693914c commit 9a8cc8cabc1e351614fd7f9e774757a5143b6fe8 commit c082fbd687ad70a92e0a8be486a7555a66f03079 commit bdaa78c6aa861f0e8c612a0b2272423d92f0071c commit c290db013742e98fe5b64073bc2dd8c8a2ac9e4c commit 24013314be6ee4ee456114a671e9fa3461323de8 commit 09bf649a74573cb596e211418a4f8008f265c5a9 commit 6e90293618ed476d6b11f82ce724efbb9e9a071b commit bc21fe9a5844c5bc8f7ec319b11d2671a94eb867 commit aeffc8fb2174f017a10df114bc312f899904dc68 commit c4252650a8c4770b669398fe7270ed8c94fc0eba Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
display/skl_universal_plane.o \
display/skl_watermark.o
drm/i915: move modesetting core code under display/ Now that we have a new subdirectory for display code, continue by moving modesetting core code. display/intel_frontbuffer.h sticks out like a sore thumb, otherwise this is, again, a surprisingly clean operation. v2: - don't move intel_sideband.[ch] (Ville) - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-3-jani.nikula@intel.com
2019-06-13 08:44:16 +00:00
i915-$(CONFIG_ACPI) += \
display/intel_acpi.o \
display/intel_opregion.o
i915-$(CONFIG_DRM_FBDEV_EMULATION) += \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
display/intel_fbdev.o \
display/intel_fbdev_fb.o
i915-$(CONFIG_DEBUG_FS) += \
display/intel_display_debugfs.o \
display/intel_display_debugfs_params.o \
display/intel_pipe_crc.o
drm/i915: Go OCD on the Makefile Chris suggested to split things up a bit into the different parts of the driver and also sort it all correctly, with the hope that we're trying to organize things a bit better eventually. It should also help newcomers to orient themselves a bit better. v2: - Move intel_pm.c to the core - to make things perfect we should split out the modeset related pm features (psr/fbc) into a separate file. Maybe something Rodrigo can do once the PSR patches have settled. - Split the modesetting sections into core and encoders/outputs. intel_ddi.c is a bit funky since it has core hsw+ support and ddi output support. Whatever. v3: Failed to git add ... v4: Really go ocd, i.e. spelling fix in a comment from Jani. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-07 08:17:21 +00:00
# modesetting output/encoder code
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
i915-y += \
display/dvo_ch7017.o \
display/dvo_ch7xxx.o \
display/dvo_ivch.o \
display/dvo_ns2501.o \
display/dvo_sil164.o \
display/dvo_tfp410.o \
drm/i915: Introduce g4x_dp.c Move the g4x+ DP code into a new file. This will leave mostly platform agnostic code in intel_dp.c. Well, the misplaced phy test stuff pretty much ruins that, but let's squint real hard for now. v2: Add comment exlaining which platforms are covered (Daniel) Leave intel_dp_unused_lane_mask() be since it is pretty generic Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210318161015.22070-6-ville.syrjala@linux.intel.com
2021-03-18 16:10:13 +00:00
display/g4x_dp.o \
drm/i915: Introduce g4x_hdmi.c Extract the g4x+ HDMI low level code to its own file, leaving intel_hdmi.c to deal with higher level issues. The infoframe support I decided to leave in intel_hdmi.c since I think we need to move that as a whole to its own file. It is after all used also for DP SDPs, so no longer HDMI specific. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210318161015.22070-7-ville.syrjala@linux.intel.com
2021-03-18 16:10:14 +00:00
display/g4x_hdmi.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/icl_dsi.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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commit aa464957f7e660abd554f2546a588f6533720e21 commit 78fed39af1af5d702089fe53076c524646e64997 commit a2fbfd517117157e99160ff1b39b171872dcba07 commit fc74881c28d314b10efac016ef49df4ff40b8b97 commit bf67014d6bda16a72deea11dbbff2a97c705ca92 commit 19e66d512e4182a0461530fa3159638e0f55d97e commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5 commit 7807bf28fe02a76bf112916c6b9194f282f5e43c commit 67f74302f45d5d862f22ced3297624e50ac352f0 commit 4d625a97a7e96be016382e3bb0a3cead05fec153 commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c commit d46f329a3f6048e04736e86cb13c880645048792 commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1 commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464 commit ebae8973884ee9ac703b3bfe34cabbb118b18538 commit 2eb82577a16d4c8eb31e4ed520649850bb95b223 commit d97e631af2db84c8c9d63abf68d487d0bb559e4c commit a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
display/intel_backlight.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_crt.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_cx0_phy.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_ddi.o \
drm/i915: refactor ddi translations into a separate file (v2) Ville suggested this, these tables are probably better being standalone. This fixes up the cnl/bxt interfaces to be like the others, the intel one I left alone since it has a few extra entrypoints. v2: add back missing rocketlake bits. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com> [Jani: made some functions static] Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/def9eed2581d71863ccdf35f323b525facc2482c.1612467466.git.jani.nikula@intel.com
2021-02-04 19:43:18 +00:00
display/intel_ddi_buf_trans.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
display/intel_display_device.o \
Merge DRM changes from upstream v5.16..v5.17 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v5.17 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/Makefile drivers/gpu/drm/i915/gem/i915_gem_pages.c drivers/gpu/drm/i915/gt/intel_gt.c drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c Conflict resolution: diff --cc drivers/gpu/drm/Makefile index 0dff40bb863c,ec2ef2cce11c..301a44dc18e3 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@@ -127,3 -134,8 +134,4 @@@ obj-$(CONFIG_DRM_TIDSS) += tidss obj-y += xlnx/ obj-y += gud/ obj-$(CONFIG_DRM_HYPERV) += hyperv/ + obj-$(CONFIG_DRM_SPRD) += sprd/ - -# Enable shims for the RHEL DRM backport -subdir-ccflags-y += -DRH_DRM_BACKPORT -drm-y += drm_backport.o Commit list: commit 107fe904302092c683cf5462b4af3cb3cfa40998 commit a1a98689301b9af0313e4c1ba44558e8b67ff76e commit befe5404a00b3b1547c944738df4a9229909bdc9 commit 8a12b170558aabb31cc98fda0da6a56b518cadaa commit 334f74ee85dc26a50c1a2b0da82517595191f92f commit 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commit 08783aa7693f55619859f4f63f384abf17cb58c5 commit 26d3474348293dc752c55fe6d41282199f73714c commit 62929726ef0ec72cbbe9440c5d125d4278b99894 commit f1ef17011c765495c876fa75435e59eecfdc1ee4 commit c9585249c245e23580a2c3edbc8f14d9d7173f12 commit 8fdb19679722a02fe21642d39710c701d2ed567a commit 804f468853179b9b58af05c153c411931aa5b310 commit 3755d35ee1d2454b20b8a1e20d790e56201678a4 commit 40ce1121c1d76daf9048a86e36c83e469281b9fd commit fc1b6ef7bfb3d1d4df868b1c3e0480cacda6cd81 commit a8253684eb4b30abd3faf055bc475c23da748dc6 commit 3c3384050d68570f9de0fec9e58824decfefba7a Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:15:52 +00:00
display/intel_display_trace.o \
Merge DRM changes from upstream v6.0.8..v6.1 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.1 2160457 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c drivers/gpu/drm/amd/amdgpu/amdgpu_job.c drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c drivers/gpu/drm/amd/amdkfd/kfd_migrate.c drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/ast/ast_mode.c drivers/gpu/drm/i915/display/intel_display.c drivers/gpu/drm/i915/gt/intel_gt_sysfs.c drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc.c drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c drivers/gpu/drm/i915/gt/uc/intel_guc_log.c drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c drivers/gpu/drm/i915/gvt/kvmgt.c drivers/gpu/drm/mgag200/mgag200_pll.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index ecb8db731081,253ea6b159df..6ebed4d58ced --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@@ -162,6 -162,7 +162,8 @@@ #define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10) #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11) #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) ++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11) + #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14) #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001 diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c @@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque */ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx) { - uint8_t i; - int j; ++ + int i, j; struct dc_stream_state *stream = NULL; struct dc_plane_state *plane = NULL; uint32_t cursor_size = 0; @@@ -237,24 -236,24 +237,27 @@@ mblk_width = DCN3_2_MBLK_WIDTH; mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE; ++ /* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) - * FLOOR(vp_x_start, blk_width) * * mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c */ mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + - pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + + pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); ++ /* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) - * FLOOR(vp_y_start, blk_height) * * mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c */ mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + - pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) + + pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); ++ num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) * ((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height); diff --cc drivers/gpu/drm/ast/ast_mode.c index b93181a42048,1bc0220e6783..ae5a4cce972f --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@@ -42,9 -40,8 +42,8 @@@ #include <drm/drm_fourcc.h> #include <drm/drm_gem_atomic_helper.h> #include <drm/drm_gem_framebuffer_helper.h> -#include <drm/drm_gem_vram_helper.h> +#include <drm/drm_gem_shmem_helper.h> #include <drm/drm_managed.h> - #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> @@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_crtc_state *crtc_state; - struct ast_crtc_state *ast_crtc_state; + struct drm_device *dev = plane->dev; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_crtc_state *new_crtc_state = NULL; + struct ast_crtc_state *new_ast_crtc_state; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, false, true); - if (ret) + if (ret) { return ret; + } else if (!new_plane_state->visible) { + if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */ + return -EINVAL; + else + return 0; + } - if (!new_plane_state->visible) - return 0; - - ast_crtc_state = to_ast_crtc_state(crtc_state); + new_ast_crtc_state = to_ast_crtc_state(new_crtc_state); - ast_crtc_state->format = new_plane_state->fb->format; + new_ast_crtc_state->format = new_plane_state->fb->format; return 0; } @@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); - struct drm_framebuffer *fb = new_plane_state->fb; - struct drm_crtc_state *crtc_state; + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); + struct drm_framebuffer *new_fb = new_plane_state->fb; + struct drm_crtc_state *new_crtc_state = NULL; int ret; - if (!new_plane_state->crtc) - return 0; - - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + if (new_plane_state->crtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, true, true); - if (ret) + if (ret || !new_plane_state->visible) return ret; - if (!new_plane_state->visible) - return 0; - - if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT) + if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT) return -EINVAL; return 0; diff --cc drivers/gpu/drm/i915/display/intel_display.c index bd629f2da6eb,de77054195c6..d3bfa2a675b8 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9 else if (DISPLAY_VER(i915) >= 11) pipes = BIT(PIPE_B) | BIT(PIPE_C); else ++ pipes = 0; - return pipes & RUNTIME_INFO(i915)->pipe_mask; + return pipes & INTEL_INFO(i915)->display.pipe_mask; } static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c @@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj return !strncmp(kobj->name, "gt", 2); } - static struct intel_gt *kobj_to_gt(struct kobject *kobj) - { - return container_of(kobj, struct intel_gt, sysfs_gt); - } - -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name) { - struct kobject *kobj = &dev->kobj; - /* * We are interested at knowing from where the interface * has been called, whether it's called from gt/ or from diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h index 6bee2c6a894d,6232923a420d..c3a123faee98 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h @@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g struct kobject *dir, const char *name); + static inline struct intel_gt *kobj_to_gt(struct kobject *kobj) + { + return container_of(kobj, struct intel_gt, sysfs_gt); + } + void intel_gt_sysfs_register(struct intel_gt *gt); void intel_gt_sysfs_unregister(struct intel_gt *gt); -struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev, +struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj, const char *name); #endif /* SYSFS_GT_H */ diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe NULL }; + static ssize_t + default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.min_freq); + } + + static struct kobj_attribute default_min_freq_mhz = + __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL); + + static ssize_t + default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) + { + struct intel_gt *gt = kobj_to_gt(kobj->parent); + + return sysfs_emit(buf, "%u\n", gt->defaults.max_freq); + } + + static struct kobj_attribute default_max_freq_mhz = + __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL); + + static const struct attribute * const rps_defaults_attrs[] = { + &default_min_freq_mhz.attr, + &default_max_freq_mhz.attr, + NULL + }; + -static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj, - const struct attribute * const *attrs) +static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj) { + const struct attribute * const *attrs; + struct attribute *vlv_attr; int ret; if (GRAPHICS_VER(gt->i915) < 6) diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 070cec4ff8a4,3955292483a6..d3ac73c3559f --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc /* hsdes: 1809175790 */ if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine->gt, + cs, GEN12_GFX_CCS_AUX_NV); + + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c index 1b6479b5bd32,a821e3d405db..21cd1a4e1823 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_ if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14013392000:dg2_g11 */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); + } - /* Wa_16011620976:dg2_g11 */ - wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_G11(i915) || IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); + } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14012419201:dg2 */ diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 844dee09a321,1db59eeb34db..1ac0e66d39e5 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i return 0; } +struct scheduling_policy { + /* internal data */ + u32 max_words, num_words; + u32 count; + /* API data */ + struct guc_update_scheduling_policy h2g; +}; + +static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy) +{ + u32 *start = (void *)&policy->h2g; + u32 *end = policy->h2g.data + policy->num_words; + size_t delta = end - start; + + return delta; +} + +static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy) +{ + policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV; + policy->max_words = ARRAY_SIZE(policy->h2g.data); + policy->num_words = 0; + policy->count = 0; + + return policy; +} + +static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy, + u32 action, u32 *data, u32 len) +{ + u32 *klv_ptr = policy->h2g.data + policy->num_words; + + GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words); + *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) | + FIELD_PREP(GUC_KLV_0_LEN, len); + memcpy(klv_ptr, data, sizeof(u32) * len); + policy->num_words += 1 + len; + policy->count++; +} + +static int __guc_action_set_scheduling_policies(struct intel_guc *guc, + struct scheduling_policy *policy) +{ + int ret; + + ret = intel_guc_send(guc, (u32 *)&policy->h2g, + __guc_scheduling_policy_action_size(policy)); + if (ret < 0) + return ret; + + if (ret != policy->count) { + drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!", + ret, policy->count); + if (ret > policy->count) + return -EPROTO; + } + + return 0; +} + +static int guc_init_global_schedule_policy(struct intel_guc *guc) +{ + struct scheduling_policy policy; + struct intel_gt *gt = guc_to_gt(guc); + intel_wakeref_t wakeref; + int ret = 0; + + if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0)) + return 0; + + __guc_scheduling_policy_start_klv(&policy); + + with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref) { + u32 yield[] = { + GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION, + GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO, + }; + + __guc_scheduling_policy_add_klv(&policy, + GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD, + yield, ARRAY_SIZE(yield)); + + ret = __guc_action_set_scheduling_policies(guc, &policy); + if (ret) + i915_probe_error(gt->i915, + "Failed to configure global scheduling policies: %pe!\n", + ERR_PTR(ret)); + } + + return ret; +} + void intel_guc_submission_enable(struct intel_guc *guc) { + struct intel_gt *gt = guc_to_gt(guc); + + /* Enable and route to GuC */ + if (GRAPHICS_VER(gt->i915) >= 12) + intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES, + GUC_SEM_INTR_ROUTE_TO_GUC | + GUC_SEM_INTR_ENABLE_ALL); + guc_init_lrc_mapping(guc); guc_init_engine_stats(guc); + guc_init_global_schedule_policy(guc); } void intel_guc_submission_disable(struct intel_guc *guc) diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index fb309ae43001,b91ad4aede1f..24aac2f32dd1 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@@ -339,6 -347,6 +347,7 @@@ bad fw_blobs[i].blob.patch); uc_fw->file_selected.path = NULL; ++ } } } diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c index 098955526b68,c481daa4bbce..38a0ba4a1b3f --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi st7701->dsi = dsi; st7701->desc = desc; - return mipi_dsi_attach(dsi); + ret = mipi_dsi_attach(dsi); + if (ret) + goto err_attach; + + return 0; + +err_attach: + drm_panel_remove(&st7701->panel); + return ret; } - static int st7701_dsi_remove(struct mipi_dsi_device *dsi) + static void st7701_dsi_remove(struct mipi_dsi_device *dsi) { struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); Commit list: commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f commit 6dc548745d5b5102e3c53dc5097296ac270b6c69 commit 859161b952a453b86362f168fadef72a8ba31a05 commit d72ac4bbf4cc8f6b50526ce400861f176659884f commit 1fd452c403ca2cd9dcbd8465f9f72be52e15ac1a commit 79abca2b399009eb8d12c652d0f0f7a9c7a06289 commit 96dc635d5538055cb6ccd7b6e9290dfcfc385f97 commit dc1dc76bd9a48c6aba3efae5eadb9a884043966e commit 356d2c8e76ebb1134a0685ce4b923d8201337475 commit 4c59b0805e9bf873fd3f5dca4fc53d8c220e39b4 commit e5bd7e3e4a68f0befe53f59954b25eec9a792d60 commit ba71593217b5b03c9e3385b268ff8613a71fc6ce commit 0a2486f85e0cfa6439116abb9078ab888a619746 commit 8aba4d30520ed656065eb36f0628109bdea385ee commit d093100b425df6fe400881f2e62c3f0be7bf18cf commit b92db7e4fe740daab858366faff1f992d53d3ff4 commit 0c05fcd3b45d6769c496fc6e2b88d18fc78ebe11 commit a6aa679a70e9d8fa4ad3f519c060db9bb186e21c commit 6de745238aa30529778a26622a430dfcb171b089 commit d395fb1999abb7eaa3fb5fd2107cae0f1e41e6d0 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commit a26a54fbe32b564ff868710d59fbe1a387a2cc7c commit f2e1aa267f12b82e03927d1e918d2844ddd3eea5 commit 3cb93f390453cde4d6afda1587aaa00e75e09617 commit a6e1775da04ab042bc9e2e42399fa25714c253da commit 602ad43c3cd8f15cbb25ce9bb494129edb2024ed commit ecb41b71ef90cf4741bcc3286b769dda746b67e6 commit 9e2c5c651a63baaa39005070481d39dcf5b0893a commit b65a648865c4a1e717c4f56f5025546b9553189a commit e57702069b26b8601a33fdc0c9bbe40c6bb9c72f commit ed14d225cc7c842f6d4d5a3009f71a44f5852d09 commit 2f3830544a89af2e72e7fd3d6ca44dd9cffec197 commit 3c1ea6a5f4f55d4e376675dda16945eb5d9bb4de commit a8899b8728013c7b2456f0bfa20e5fea85ee0fd1 commit 12b8b046e4c9de40fa59b6f067d6826f4e688f68 commit 8c115864501fc09932cdfec53d9ec1cde82b4a28 commit 04aa64375f48a5d430b5550d9271f8428883e550 commit 6f6cb1714365a07dbc66851879538df9f6969288 commit d3d6b1bf85aefe0ebc0624574b3bb62f0693914c commit 9a8cc8cabc1e351614fd7f9e774757a5143b6fe8 commit c082fbd687ad70a92e0a8be486a7555a66f03079 commit bdaa78c6aa861f0e8c612a0b2272423d92f0071c commit c290db013742e98fe5b64073bc2dd8c8a2ac9e4c commit 24013314be6ee4ee456114a671e9fa3461323de8 commit 09bf649a74573cb596e211418a4f8008f265c5a9 commit 6e90293618ed476d6b11f82ce724efbb9e9a071b commit bc21fe9a5844c5bc8f7ec319b11d2671a94eb867 commit aeffc8fb2174f017a10df114bc312f899904dc68 commit c4252650a8c4770b669398fe7270ed8c94fc0eba Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
display/intel_dkl_phy.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_dp.o \
drm/i915/dp: split out aux functionality to intel_dp_aux.c Split out the DP aux functionality to a new intel_dp_aux.[ch]. This is a surprisingly clean cut. v2: - Remove intel_dp_pack_aux declaration from intel_dp.h (Anshuman) - Fixed some whitespace/comment checkpatch warnings Cc: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-4-jani.nikula@intel.com
2021-01-20 10:18:34 +00:00
display/intel_dp_aux.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_dp_aux_backlight.o \
drm/i915: Factor out HDCP shim functions from dp for use by dp_mst These functions are all the same for dp and dp_mst, so move them into a dedicated file for both sst and mst to use. Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-11-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-12-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-12-sean@poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-12-sean@poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-12-sean@poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-12-sean@poorly.run #v6 Link: https://patchwork.freedesktop.org/patch/msgid/20200623155907.22961-13-sean@poorly.run #v7 Changes in v2: -None Changes in v3: -Created intel_dp_hdcp.c for the shared functions to live (Ville) Changes in v4: -Rebased on new drm logging change Changes in v5: -None Changes in v6: -None Changes in v7: -Rebased patch Changes in v8: -None Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200818153910.27894-13-sean@poorly.run
2020-08-18 15:39:00 +00:00
display/intel_dp_hdcp.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_dp_link_training.o \
display/intel_dp_mst.o \
Merge DRM changes from upstream v6.12..v6.13 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.13 RHEL-75951 JIRA: https://issues.redhat.com/browse/RHEL-75951 Conflicts: drivers/dma-buf/udmabuf.c drivers/gpu/drm/Kconfig drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c drivers/gpu/drm/amd/display/Kconfig drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c drivers/gpu/drm/amd/display/dc/inc/core_types.h drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_syncobj.c drivers/gpu/drm/i915/display/intel_display_trace.h drivers/gpu/drm/i915/i915_trace.h drivers/gpu/drm/i915/i915_utils.h drivers/gpu/drm/panthor/panthor_device.h drivers/gpu/drm/xe/xe_devcoredump.c drivers/gpu/drm/xe/xe_devcoredump_types.h drivers/gpu/drm/xe/xe_guc_log.c drivers/gpu/drm/xe/xe_hw_engine.c drivers/gpu/drm/xe/xe_pci.c drivers/gpu/drm/xe/xe_wa.c drivers/gpu/drm/xe/xe_wa_oob.rules include/drm/intel/xe_pciids.h Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index 7f8cbb07a24f,772fc7625639..7c1f72832160 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -211,15 -209,48 +209,53 @@@ config DRM_DEBUG_MODESET_LOC If in doubt, say "N". + config DRM_CLIENT + bool + depends on DRM + help + Enables support for DRM clients. DRM drivers that need + struct drm_client_dev and its interfaces should select this + option. Drivers that support the default clients should + select DRM_CLIENT_SELECTION instead. + + config DRM_CLIENT_LIB + tristate + depends on DRM + select DRM_KMS_HELPER if DRM_FBDEV_EMULATION + select FB_CORE if DRM_FBDEV_EMULATION + help + This option enables the DRM client library and selects all + modules and components according to the enabled clients. + + config DRM_CLIENT_SELECTION + tristate + depends on DRM + select DRM_CLIENT_LIB if DRM_FBDEV_EMULATION + help + Drivers that support in-kernel DRM clients have to select this + option. + + config DRM_CLIENT_SETUP + bool + depends on DRM_CLIENT_SELECTION + help + Enables the DRM client selection. DRM drivers that support the + default clients should select DRM_CLIENT_SELECTION instead. + + menu "Supported DRM clients" + depends on DRM_CLIENT_SELECTION + config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" - depends on DRM + depends on DRM_CLIENT_SELECTION + select DRM_CLIENT + select DRM_CLIENT_SETUP select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT ++ select FB_SYS_IMAGEBLIT default FB help Choose this option if you have a need for the legacy fbdev diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bd0dab9811d1,cd4fac120834..d73f84c53e76 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -33,11 -35,11 +35,10 @@@ #include <linux/iommu.h> #include <linux/pci.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_event.h> #include <drm/drm_crtc_helper.h> - #include <drm/drm_fb_helper.h> #include <drm/drm_probe_helper.h> #include <drm/amdgpu_drm.h> #include <linux/device.h> @@@ -4494,16 -4584,18 +4617,15 @@@ fence_driver_init if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); - px = amdgpu_device_supports_px(ddev); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(ddev)) { + px = true; vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, px); - - if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + } - if (adev->gmc.xgmi.pending_reset) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --cc drivers/gpu/drm/display/drm_dp_mst_topology.c index f0c6d50d8c33,dc4446d589e7..6bff2d5eb59c --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@@ -4184,10 -4188,10 +4191,21 @@@ static int drm_dp_mst_handle_up_req(str out_put_primary: drm_dp_mst_topology_put_mstb(mst_primary); out_clear_reply: - memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx)); - return 0; + reset_msg_rx_state(&mgr->up_req_recv); + return ret; + } + ++static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) ++{ ++ mutex_lock(&mgr->lock); ++ if (mgr->reset_rx_state) { ++ mgr->reset_rx_state = false; ++ reset_msg_rx_state(&mgr->down_rep_recv); ++ reset_msg_rx_state(&mgr->up_req_recv); ++ } ++ mutex_unlock(&mgr->lock); +} + static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --cc drivers/gpu/drm/drm_syncobj.c index 4fcfc0b9b386,4f2ab8a7b50f..0058689f69fa --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@@ -712,19 -712,17 +712,17 @@@ static int drm_syncobj_fd_to_handle(str int fd, u32 *handle) { struct drm_syncobj *syncobj; - struct fd f = fdget(fd); + CLASS(fd, f)(fd); int ret; - if (!f.file) + if (fd_empty(f)) return -EINVAL; - if (f.file->f_op != &drm_syncobj_file_fops) { - fdput(f); + if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - } /* take a reference to put in the idr */ - syncobj = fd_file(f)->private_data; + syncobj = f.file->private_data; drm_syncobj_get(syncobj); idr_preload(GFP_KERNEL); diff --cc drivers/gpu/drm/hyperv/hyperv_drm_drv.c index 7ef4d7ea5468,e0953777a206..34d8d5ef2a62 --- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c @@@ -7,10 -8,9 +8,10 @@@ #include <linux/hyperv.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/screen_info.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_shmem.h> #include <drm/drm_gem_shmem_helper.h> diff --cc drivers/gpu/drm/i915/display/intel_display_trace.h index fbd3f83df807,9bd8f1e505b0..eeb73303e2e0 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@@ -61,10 -102,14 +102,14 @@@ TRACE_EVENT(intel_pipe_disable ), TP_fast_assign( - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc *it__; - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - for_each_intel_crtc(&dev_priv->drm, it__) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, it__) { __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); } @@@ -90,8 -132,8 +132,8 @@@ TRACE_EVENT(intel_crtc_flip_done ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -114,8 -156,8 +156,8 @@@ TRACE_EVENT(intel_pipe_crc ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); @@@ -141,9 -183,9 +183,9 @@@ TRACE_EVENT(intel_cpu_fifo_underrun ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = pipe; + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -166,9 -208,9 +208,9 @@@ TRACE_EVENT(intel_pch_fifo_underrun TP_fast_assign( enum pipe pipe = pch_transcoder; - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - __entry->pipe = pipe; + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -192,8 -234,12 +234,12 @@@ TRACE_EVENT(intel_memory_cxsr TP_fast_assign( struct intel_crtc *crtc; - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - for_each_intel_crtc(&dev_priv->drm, crtc) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, crtc) { __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); } @@@ -232,8 -276,8 +276,8 @@@ TRACE_EVENT(g4x_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; @@@ -279,8 -323,8 +323,8 @@@ TRACE_EVENT(vlv_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->level = wm->level; @@@ -316,8 -360,8 +360,8 @@@ TRACE_EVENT(vlv_fifo_size ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->sprite0_start = sprite0_start; @@@ -345,9 -389,9 +389,9 @@@ TRACE_EVENT(intel_plane_async_flip ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, __dev_name_kms(plane)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; @@@ -373,9 -417,9 +417,9 @@@ TRACE_EVENT(intel_plane_update_noarm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -404,9 -448,9 +448,9 @@@ TRACE_EVENT(intel_plane_update_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -433,9 -477,9 +477,9 @@@ TRACE_EVENT(intel_plane_disable_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); - __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; ++ __assign_str(name, plane->base.name); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -458,11 -502,12 +502,12 @@@ TRACE_EVENT(intel_fbc_activate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -485,11 -530,12 +530,12 @@@ TRACE_EVENT(intel_fbc_deactivate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -512,11 -558,12 +558,12 @@@ TRACE_EVENT(intel_fbc_nuke ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -538,8 -585,8 +585,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_star ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -561,8 -608,8 +608,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_end ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -586,8 -633,8 +633,8 @@@ TRACE_EVENT(intel_pipe_update_start ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->min = crtc->debug.min_vbl; @@@ -614,8 -661,8 +661,8 @@@ TRACE_EVENT(intel_pipe_update_vblank_ev ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = crtc->debug.start_vbl_count; __entry->scanline = crtc->debug.scanline_start; __entry->min = crtc->debug.min_vbl; @@@ -640,8 -687,8 +687,8 @@@ TRACE_EVENT(intel_pipe_update_end ), TP_fast_assign( - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = frame; __entry->scanline = scanline_end; ), diff --cc drivers/gpu/drm/xe/Makefile index b578ef68bc34,bc7a04ce69fd..21a1ecca0fea --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@@ -145,10 -147,9 +147,9 @@@ endi # i915 Display compat #defines and #includes subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ - -I$(src)/display/ext \ - -I$(src)/compat-i915-headers \ + -I$(srctree)/$(src)/display/ext \ + -I$(srctree)/$(src)/compat-i915-headers \ -I$(srctree)/drivers/gpu/drm/i915/display/ \ - -Ddrm_i915_gem_object=xe_bo \ -Ddrm_i915_private=xe_device # Rule to build SOC code shared with i915 diff --cc drivers/gpu/drm/xe/xe_gt_topology.c index 3e113422b88d,df2042db7ee6..f504b1012493 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@@ -129,8 -129,8 +129,20 @@@ static voi load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) { struct xe_device *xe = gt_to_xe(gt); - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3); + u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); + ++ /* ++ * PTL platforms with media version 30.00 do not provide proper values ++ * for the media GT's L3 bank registers. Skip the readout since we ++ * don't have any way to obtain real values. ++ * ++ * This may get re-described as an official workaround in the future, ++ * but there's no tracking number assigned yet so we use a custom ++ * OOB workaround descriptor. ++ */ ++ if (XE_WA(gt, no_media_l3)) ++ return; + /* * PTL platforms with media version 30.00 do not provide proper values * for the media GT's L3 bank registers. Skip the readout since we diff --cc drivers/gpu/drm/xe/xe_guc_log.c index be47780ec2a7,df4cfb698cdb..38db790f254b --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@@ -5,11 -5,14 +5,15 @@@ #include "xe_guc_log.h" + #include <linux/fault-inject.h> + #include <drm/drm_managed.h> +#include <linux/vmalloc.h> + #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_devcoredump.h" + #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_map.h" Commit list: commit 3973a8d052829dcc5193fb6330dcd13c2b7127ca commit 7a5115ba1d691bd14db91d2fcc3ce0b056574ce9 commit c7d84a45f4266e9ff4c61eddde4acbfddb8f6b57 commit eb4accc5234525e2cb2b720187ccaf6db99b705f commit 3742c20958a5b02ecba08d71036bae3e7b9d21b3 commit 2872a57c7ad427d428c6d12e95e55b32bdc8e3b8 commit 9c75b16cabc69adbbfdc9d219df87c9173f0da0a commit 3a8d97611b564b5b25f68c90b543056fc9ae0bec commit 9b79594aa470fd5fe2173d281fd604d11ec8e902 commit e8653e63e834e4c7de60b81b8b24deb7bdd3bf56 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commit 5db89168c408871d306e9fb669e494a1444da8ee commit b26de02cf903b5182588c0df91a6e1b512f7d3f3 commit 79a21fc921d7aafaf69d00b4938435b81bf66022 commit fa6493440f084c5ba8e30dce84158cbfeac86311 commit cf8182d33798966146c7eaab7209b606939a17c5 commit b1231ff7ea0689d04040a44864c265bc11612fa8 commit cfaf51adaf4e0b1850c84e05c81e879dd571c17c commit 9b1c673a1648cc3501a3b7719db2bec931cf00f7 commit 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d Signed-off-by: Robert Foss <rfoss@redhat.com>
2025-04-01 09:44:50 +00:00
display/intel_dp_test.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_dsi.o \
display/intel_dsi_dcs_backlight.o \
display/intel_dsi_vbt.o \
display/intel_dvo.o \
Merge DRM changes from upstream v6.10..v6.11 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.11 RHEL-53570 JIRA: https://issues.redhat.com/browse/RHEL-53570 Conflicts: drivers/gpu/drm/vmwgfx/vmwgfx_msg_x86.h Conflict resolution: diff --cc drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index 323c33c9c37aa,c6b669866fed1..349a0ef6fd1fc --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@@ -16,14 -16,10 +16,10 @@@ #include <linux/gpio/consumer.h> #include <linux/delay.h> #include <linux/module.h> -#include <linux/of.h> +#include <linux/of_device.h> #include <linux/regulator/consumer.h> - #define JD9365DA_INIT_CMD_LEN 2 - - struct jadard_init_cmd { - u8 data[JD9365DA_INIT_CMD_LEN]; - }; + struct jadard; struct jadard_panel_desc { const struct drm_display_mode mode; Commit list: commit 869e54d4d54b1b0ee16c98c2149f5785eea08c02 commit 06e7139a034f26804904368fe4af2ceb70724756 commit 8f21f82d8b7652e11e6800612e34547bffdc7fd2 commit 1cb4db30cf685709584743d8bf8a0db2eac620c9 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commit 94c4aa266111262c96c98f822d1bccc494786fee commit bb7e19bd6cb68e08272e08acb814b9342ad5a43d commit 690e516e9869791bcac00ad5a351d953a928044b commit 135be1dc46c64c454f2828dbb7f239d035f47180 Signed-off-by: Robert Foss <rfoss@redhat.com>
2024-11-21 22:32:33 +00:00
display/intel_encoder.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_gmbus.o \
display/intel_hdmi.o \
display/intel_lspcon.o \
display/intel_lvds.o \
display/intel_panel.o \
Merge DRM changes from upstream v6.12..v6.13 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.13 RHEL-75951 JIRA: https://issues.redhat.com/browse/RHEL-75951 Conflicts: drivers/dma-buf/udmabuf.c drivers/gpu/drm/Kconfig drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c drivers/gpu/drm/amd/display/Kconfig drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c drivers/gpu/drm/amd/display/dc/inc/core_types.h drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_syncobj.c drivers/gpu/drm/i915/display/intel_display_trace.h drivers/gpu/drm/i915/i915_trace.h drivers/gpu/drm/i915/i915_utils.h drivers/gpu/drm/panthor/panthor_device.h drivers/gpu/drm/xe/xe_devcoredump.c drivers/gpu/drm/xe/xe_devcoredump_types.h drivers/gpu/drm/xe/xe_guc_log.c drivers/gpu/drm/xe/xe_hw_engine.c drivers/gpu/drm/xe/xe_pci.c drivers/gpu/drm/xe/xe_wa.c drivers/gpu/drm/xe/xe_wa_oob.rules include/drm/intel/xe_pciids.h Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index 7f8cbb07a24f,772fc7625639..7c1f72832160 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -211,15 -209,48 +209,53 @@@ config DRM_DEBUG_MODESET_LOC If in doubt, say "N". + config DRM_CLIENT + bool + depends on DRM + help + Enables support for DRM clients. DRM drivers that need + struct drm_client_dev and its interfaces should select this + option. Drivers that support the default clients should + select DRM_CLIENT_SELECTION instead. + + config DRM_CLIENT_LIB + tristate + depends on DRM + select DRM_KMS_HELPER if DRM_FBDEV_EMULATION + select FB_CORE if DRM_FBDEV_EMULATION + help + This option enables the DRM client library and selects all + modules and components according to the enabled clients. + + config DRM_CLIENT_SELECTION + tristate + depends on DRM + select DRM_CLIENT_LIB if DRM_FBDEV_EMULATION + help + Drivers that support in-kernel DRM clients have to select this + option. + + config DRM_CLIENT_SETUP + bool + depends on DRM_CLIENT_SELECTION + help + Enables the DRM client selection. DRM drivers that support the + default clients should select DRM_CLIENT_SELECTION instead. + + menu "Supported DRM clients" + depends on DRM_CLIENT_SELECTION + config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" - depends on DRM + depends on DRM_CLIENT_SELECTION + select DRM_CLIENT + select DRM_CLIENT_SETUP select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE + select FB_DEFERRED_IO + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT ++ select FB_SYS_IMAGEBLIT default FB help Choose this option if you have a need for the legacy fbdev diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bd0dab9811d1,cd4fac120834..d73f84c53e76 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@@ -33,11 -35,11 +35,10 @@@ #include <linux/iommu.h> #include <linux/pci.h> #include <linux/pci-p2pdma.h> -#include <linux/apple-gmux.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_event.h> #include <drm/drm_crtc_helper.h> - #include <drm/drm_fb_helper.h> #include <drm/drm_probe_helper.h> #include <drm/amdgpu_drm.h> #include <linux/device.h> @@@ -4494,16 -4584,18 +4617,15 @@@ fence_driver_init if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); - px = amdgpu_device_supports_px(ddev); - - if (px || (!dev_is_removable(&adev->pdev->dev) && - apple_gmux_detect(NULL, NULL))) + if (amdgpu_device_supports_px(ddev)) { + px = true; vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, px); - - if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); + } - if (adev->gmc.xgmi.pending_reset) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --cc drivers/gpu/drm/display/drm_dp_mst_topology.c index f0c6d50d8c33,dc4446d589e7..6bff2d5eb59c --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@@ -4184,10 -4188,10 +4191,21 @@@ static int drm_dp_mst_handle_up_req(str out_put_primary: drm_dp_mst_topology_put_mstb(mst_primary); out_clear_reply: - memset(&mgr->up_req_recv, 0, sizeof(struct drm_dp_sideband_msg_rx)); - return 0; + reset_msg_rx_state(&mgr->up_req_recv); + return ret; + } + ++static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) ++{ ++ mutex_lock(&mgr->lock); ++ if (mgr->reset_rx_state) { ++ mgr->reset_rx_state = false; ++ reset_msg_rx_state(&mgr->down_rep_recv); ++ reset_msg_rx_state(&mgr->up_req_recv); ++ } ++ mutex_unlock(&mgr->lock); +} + static void update_msg_rx_state(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --cc drivers/gpu/drm/drm_syncobj.c index 4fcfc0b9b386,4f2ab8a7b50f..0058689f69fa --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@@ -712,19 -712,17 +712,17 @@@ static int drm_syncobj_fd_to_handle(str int fd, u32 *handle) { struct drm_syncobj *syncobj; - struct fd f = fdget(fd); + CLASS(fd, f)(fd); int ret; - if (!f.file) + if (fd_empty(f)) return -EINVAL; - if (f.file->f_op != &drm_syncobj_file_fops) { - fdput(f); + if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - } /* take a reference to put in the idr */ - syncobj = fd_file(f)->private_data; + syncobj = f.file->private_data; drm_syncobj_get(syncobj); idr_preload(GFP_KERNEL); diff --cc drivers/gpu/drm/hyperv/hyperv_drm_drv.c index 7ef4d7ea5468,e0953777a206..34d8d5ef2a62 --- a/drivers/gpu/drm/hyperv/hyperv_drm_drv.c +++ b/drivers/gpu/drm/hyperv/hyperv_drm_drv.c @@@ -7,10 -8,9 +8,10 @@@ #include <linux/hyperv.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/screen_info.h> - #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> + #include <drm/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_shmem.h> #include <drm/drm_gem_shmem_helper.h> diff --cc drivers/gpu/drm/i915/display/intel_display_trace.h index fbd3f83df807,9bd8f1e505b0..eeb73303e2e0 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@@ -61,10 -102,14 +102,14 @@@ TRACE_EVENT(intel_pipe_disable ), TP_fast_assign( - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc *it__; - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - for_each_intel_crtc(&dev_priv->drm, it__) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, it__) { __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); } @@@ -90,8 -132,8 +132,8 @@@ TRACE_EVENT(intel_crtc_flip_done ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -114,8 -156,8 +156,8 @@@ TRACE_EVENT(intel_pipe_crc ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); @@@ -141,9 -183,9 +183,9 @@@ TRACE_EVENT(intel_cpu_fifo_underrun ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = pipe; + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -166,9 -208,9 +208,9 @@@ TRACE_EVENT(intel_pch_fifo_underrun TP_fast_assign( enum pipe pipe = pch_transcoder; - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - __entry->pipe = pipe; + __entry->pipe_name = pipe_name(pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -192,8 -234,12 +234,12 @@@ TRACE_EVENT(intel_memory_cxsr TP_fast_assign( struct intel_crtc *crtc; - __assign_str(dev); + __assign_str(dev, __dev_name_i915(dev_priv)); - for_each_intel_crtc(&dev_priv->drm, crtc) { + memset(__entry->frame, 0, + sizeof(__entry->frame[0]) * I915_MAX_PIPES); + memset(__entry->scanline, 0, + sizeof(__entry->scanline[0]) * I915_MAX_PIPES); + for_each_intel_crtc(display->drm, crtc) { __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); } @@@ -232,8 -276,8 +276,8 @@@ TRACE_EVENT(g4x_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; @@@ -279,8 -323,8 +323,8 @@@ TRACE_EVENT(vlv_wm ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->level = wm->level; @@@ -316,8 -360,8 +360,8 @@@ TRACE_EVENT(vlv_fifo_size ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->sprite0_start = sprite0_start; @@@ -345,9 -389,9 +389,9 @@@ TRACE_EVENT(intel_plane_async_flip ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, __dev_name_kms(plane)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; @@@ -373,9 -417,9 +417,9 @@@ TRACE_EVENT(intel_plane_update_noarm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -404,9 -448,9 +448,9 @@@ TRACE_EVENT(intel_plane_update_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); @@@ -433,9 -477,9 +477,9 @@@ TRACE_EVENT(intel_plane_disable_arm ), TP_fast_assign( - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); - __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; ++ __assign_str(name, plane->base.name); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -458,11 -502,12 +502,12 @@@ TRACE_EVENT(intel_fbc_activate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -485,11 -530,12 +530,12 @@@ TRACE_EVENT(intel_fbc_deactivate ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -512,11 -558,12 +558,12 @@@ TRACE_EVENT(intel_fbc_nuke ), TP_fast_assign( - struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(plane->base.dev), + struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); - __assign_str(dev); - __assign_str(name); + __assign_str(dev, __dev_name_kms(plane)); + __assign_str(name, plane->base.name); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -538,8 -585,8 +585,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_star ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -561,8 -608,8 +608,8 @@@ TRACE_EVENT(intel_crtc_vblank_work_end ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); ), @@@ -586,8 -633,8 +633,8 @@@ TRACE_EVENT(intel_pipe_update_start ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->min = crtc->debug.min_vbl; @@@ -614,8 -661,8 +661,8 @@@ TRACE_EVENT(intel_pipe_update_vblank_ev ), TP_fast_assign( - __assign_str(dev); + __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = crtc->debug.start_vbl_count; __entry->scanline = crtc->debug.scanline_start; __entry->min = crtc->debug.min_vbl; @@@ -640,8 -687,8 +687,8 @@@ TRACE_EVENT(intel_pipe_update_end ), TP_fast_assign( - __assign_str(dev, __dev_name_kms(crtc)); - __entry->pipe = crtc->pipe; - __assign_str(dev); ++ __assign_str(dev, __dev_name_kms(crtc)); + __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = frame; __entry->scanline = scanline_end; ), diff --cc drivers/gpu/drm/xe/Makefile index b578ef68bc34,bc7a04ce69fd..21a1ecca0fea --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@@ -145,10 -147,9 +147,9 @@@ endi # i915 Display compat #defines and #includes subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ - -I$(src)/display/ext \ - -I$(src)/compat-i915-headers \ + -I$(srctree)/$(src)/display/ext \ + -I$(srctree)/$(src)/compat-i915-headers \ -I$(srctree)/drivers/gpu/drm/i915/display/ \ - -Ddrm_i915_gem_object=xe_bo \ -Ddrm_i915_private=xe_device # Rule to build SOC code shared with i915 diff --cc drivers/gpu/drm/xe/xe_gt_topology.c index 3e113422b88d,df2042db7ee6..f504b1012493 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@@ -129,8 -129,8 +129,20 @@@ static voi load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) { struct xe_device *xe = gt_to_xe(gt); - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3); + u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); + ++ /* ++ * PTL platforms with media version 30.00 do not provide proper values ++ * for the media GT's L3 bank registers. Skip the readout since we ++ * don't have any way to obtain real values. ++ * ++ * This may get re-described as an official workaround in the future, ++ * but there's no tracking number assigned yet so we use a custom ++ * OOB workaround descriptor. ++ */ ++ if (XE_WA(gt, no_media_l3)) ++ return; + /* * PTL platforms with media version 30.00 do not provide proper values * for the media GT's L3 bank registers. Skip the readout since we diff --cc drivers/gpu/drm/xe/xe_guc_log.c index be47780ec2a7,df4cfb698cdb..38db790f254b --- a/drivers/gpu/drm/xe/xe_guc_log.c +++ b/drivers/gpu/drm/xe/xe_guc_log.c @@@ -5,11 -5,14 +5,15 @@@ #include "xe_guc_log.h" + #include <linux/fault-inject.h> + #include <drm/drm_managed.h> +#include <linux/vmalloc.h> + #include "regs/xe_guc_regs.h" #include "xe_bo.h" #include "xe_devcoredump.h" + #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_gt_printk.h" #include "xe_map.h" Commit list: commit 3973a8d052829dcc5193fb6330dcd13c2b7127ca commit 7a5115ba1d691bd14db91d2fcc3ce0b056574ce9 commit c7d84a45f4266e9ff4c61eddde4acbfddb8f6b57 commit eb4accc5234525e2cb2b720187ccaf6db99b705f commit 3742c20958a5b02ecba08d71036bae3e7b9d21b3 commit 2872a57c7ad427d428c6d12e95e55b32bdc8e3b8 commit 9c75b16cabc69adbbfdc9d219df87c9173f0da0a commit 3a8d97611b564b5b25f68c90b543056fc9ae0bec commit 9b79594aa470fd5fe2173d281fd604d11ec8e902 commit e8653e63e834e4c7de60b81b8b24deb7bdd3bf56 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commit 5db89168c408871d306e9fb669e494a1444da8ee commit b26de02cf903b5182588c0df91a6e1b512f7d3f3 commit 79a21fc921d7aafaf69d00b4938435b81bf66022 commit fa6493440f084c5ba8e30dce84158cbfeac86311 commit cf8182d33798966146c7eaab7209b606939a17c5 commit b1231ff7ea0689d04040a44864c265bc11612fa8 commit cfaf51adaf4e0b1850c84e05c81e879dd571c17c commit 9b1c673a1648cc3501a3b7719db2bec931cf00f7 commit 9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d Signed-off-by: Robert Foss <rfoss@redhat.com>
2025-04-01 09:44:50 +00:00
display/intel_pfit.o \
drm/i915/pps: abstract panel power sequencer from intel_dp.c In a long overdue refactoring, split out all panel sequencer code from intel_dp.c to new intel_pps.[ch]. The first part is mostly just code movement as-is, without cleanups or functional changes. We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from pps code. v2: Rebase. Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/14cc59d5734432ad976cd49ff8efce8fa413e5b2.1610127741.git.jani.nikula@intel.com
2021-01-08 17:44:09 +00:00
display/intel_pps.o \
drm/i915/xelpd: Add rc_qp_table for rcparams calculation Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by the VESA C model for DSC 1.1 v2: - Add include guard to header (Jani) - Move the big tables to a .c file (Chris, Jani, Lucas) v3: - Make tables 'static const' and add lookup functions to index into them. (Jani) v3.1: - Include missing .h file. Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210519000625.3184321-3-lucas.demarchi@intel.com
2021-05-19 00:06:10 +00:00
display/intel_qp_tables.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_sdvo.o \
Merge DRM changes from upstream v5.14..v5.15 This commit was generated using: rhdrm-merge-drm v5.15 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: Makefile drivers/gpu/drm/drm_gem_atomic_helper.c drivers/gpu/drm/drm_gem_framebuffer_helper.c drivers/gpu/drm/gud/gud_pipe.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c include/drm/drm_gem_atomic_helper.h include/drm/drm_gem_framebuffer_helper.h Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment } } #endif /* CONFIG_DMA_API_DEBUG */ - return sg_table; } -EXPORT_SYMBOL_GPL(dma_buf_map_attachment); +EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF); /** * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd goto free; if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) - adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); } +#ifdef CONFIG_X86_MCE_AMD + if ((adev->asic_type == CHIP_ALDEBARAN) && + (adev->gmc.xgmi.connected_to_cpu)) + amdgpu_register_bad_pages_mca_notifier(); +#endif + return 0; free: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) #define I915_BO_ALLOC_VOLATILE BIT(1) - #define I915_BO_ALLOC_STRUCT_PAGE BIT(2) - #define I915_BO_ALLOC_CPU_CLEAR BIT(3) + #define I915_BO_ALLOC_CPU_CLEAR BIT(2) + #define I915_BO_ALLOC_USER BIT(3) #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ - I915_BO_ALLOC_STRUCT_PAGE | \ - I915_BO_ALLOC_CPU_CLEAR) + I915_BO_ALLOC_CPU_CLEAR | \ + I915_BO_ALLOC_USER) #define I915_BO_READONLY BIT(4) #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ +#define I915_BO_WAS_BOUND_BIT 6 - /* - * Is the object to be mapped as read-only to the GPU - * Only honoured if hardware has relevant pte bit + /** + * @mem_flags - Mutable placement-related flags + * + * These are flags that indicate specifics of the memory region + * the object is currently in. As such they are only stable + * either under the object lock or if the object is pinned. + */ + unsigned int mem_flags; + #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */ + #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */ + /** + * @cache_level: The desired GTT caching level. + * + * See enum i915_cache_level for possible values, along with what + * each does. */ unsigned int cache_level:3; - unsigned int cache_coherent:2; + /** + * @cache_coherent: + * + * Track whether the pages are coherent with the GPU if reading or + * writing through the CPU caches. The largely depends on the + * @cache_level setting. + * + * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom + * platforms, coherency must be explicitly requested with some special + * GTT caching bits(see enum i915_cache_level). When enabling coherency + * it does come at a performance and power cost on such platforms. On + * the flip side the kernel does not need to manually flush any buffers + * which need to be coherent with the GPU, if the object is not coherent + * i.e @cache_coherent is zero. + * + * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory + * access will automatically snoop the CPU caches(even with CACHE_NONE). + * The one exception is when dealing with the display engine, like with + * scanout surfaces. To handle this the kernel will always flush the + * surface out of the CPU caches when preparing it for scanout. Also + * note that since scanout surfaces are only ever read by the display + * engine we only need to care about flushing any writes through the CPU + * cache, reads on the other hand will always be coherent. + * + * Something strange here is why @cache_coherent is not a simple + * boolean, i.e coherent vs non-coherent. The reasoning for this is back + * to the display engine not being fully coherent. As a result scanout + * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT. + * In the case of seeing I915_CACHE_NONE the kernel makes the assumption + * that this is likely a scanout surface, and will set @cache_coherent + * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared + * LLC. The kernel uses this to always flush writes through the CPU + * cache as early as possible, where it can, in effect keeping + * @cache_dirty clean, so we can potentially avoid stalling when + * flushing the surface just before doing the scanout. This does mean + * we might unnecessarily flush non-scanout objects in some places, but + * the default assumption is that all normal objects should be using + * I915_CACHE_LLC, at least on platforms with the shared LLC. + * + * Supported values: + * + * I915_BO_CACHE_COHERENT_FOR_READ: + * + * On shared LLC platforms, we use this for special scanout surfaces, + * where the display engine is not coherent with the CPU cache. As such + * we need to ensure we flush any writes before doing the scanout. As an + * optimisation we try to flush any writes as early as possible to avoid + * stalling later. + * + * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC + * platforms, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ + * + * While for normal objects that are fully coherent, including special + * scanout surfaces marked as I915_CACHE_WT, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ | + * I915_BO_CACHE_COHERENT_FOR_WRITE + * + * And then for objects that are not coherent at all we use: + * + * cache_coherent = 0 + * + * I915_BO_CACHE_COHERENT_FOR_WRITE: + * + * When writing through the CPU cache, the GPU is still coherent. Note + * that this also implies I915_BO_CACHE_COHERENT_FOR_READ. + */ #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) + unsigned int cache_coherent:2; + + /** + * @cache_dirty: + * + * Track if we are we dirty with writes through the CPU cache for this + * object. As a result reading directly from main memory might yield + * stale data. + * + * This also ties into whether the kernel is tracking the object as + * coherent with the GPU, as per @cache_coherent, as it determines if + * flushing might be needed at various points. + * + * Another part of @cache_dirty is managing flushing when first + * acquiring the pages for system memory, at this point the pages are + * considered foreign, so the default assumption is that the cache is + * dirty, for example the page zeroing done by the kernel might leave + * writes though the CPU cache, or swapping-in, while the actual data in + * main memory is potentially stale. Note that this is a potential + * security issue when dealing with userspace objects and zeroing. Now, + * whether we actually need apply the big sledgehammer of flushing all + * the pages on acquire depends on if @cache_coherent is marked as + * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent + * for both reads and writes though the CPU cache. + * + * Note that on shared LLC platforms we still apply the heavy flush for + * I915_CACHE_NONE objects, under the assumption that this is going to + * be used for scanout. + * + * Update: On some hardware there is now also the 'Bypass LLC' MOCS + * entry, which defeats our @cache_coherent tracking, since userspace + * can freely bypass the CPU cache when touching the pages with the GPU, + * where the kernel is completely unaware. On such platform we need + * apply the sledgehammer-on-acquire regardless of the @cache_coherent. + */ unsigned int cache_dirty:1; /** diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c index b9aaf640f372,6109cd9e3399..e7efd9ede8e4 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de struct nvkm_client *client; struct nvkm_device *device; - drm_dev_unregister(dev); + drm_dev_unplug(dev); - dev->irq_enabled = false; client = nvxx_client(&drm->client.base); device = nvkm_device_find(client->device); diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c index f9d399ea628d,e50fb82a3030..2aceac7856e2 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c @@@ -28,9 -28,10 +28,10 @@@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/mem_encrypt.h> +#include <linux/cc_platform.h> #include <asm/hypervisor.h> + #include <drm/drm_ioctl.h> #include "vmwgfx_drv.h" #include "vmwgfx_msg_x86.h" @@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st unsigned long msg_len = strlen(msg); /* HB port can't access encrypted memory. */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_high; + u32 channel_id = (channel->channel_id << 16); si = (uintptr_t) msg; di = channel->cookie_low; @@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str unsigned long si, di, eax, ebx, ecx, edx; /* HB port can't access encrypted memory */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_low; + u32 channel_id = (channel->channel_id << 16); si = channel->cookie_high; di = (uintptr_t) reply; Commit list: commit 241a9e233e7cf1001d09426c9fc520768f8961bf commit 4154fa0e2688118ba3dbc67aa834435463f9ea68 commit 3faea9939a3d1eb5a40f3f6100c24792865b6445 commit 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commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7 commit fcf918ffd3b35e288097036c04af7446b2c6f2f1 commit 9761ffb8f1090289b908590039e2c363cc35cf45 commit 6e6f96630805874fa80b0067e1a57aafc06225f6 commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2 commit defbbcd99fa68cb7feed453662048baa87e9a441 commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5 commit 54149d13f369e1ab02f36b91feee02069184c1d8 commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e commit 19928833e8f8fa5ee687c451437ce674f19d6c09 commit 79516af3497a5b89acb09f4a644f61d6c69e5f16 commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626 commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
display/intel_snps_phy.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/intel_tv.o \
display/intel_vdsc.o \
drm/i915/display/vrr: Create VRR file and add VRR capability check We create a new file for all VRR related helpers. Also add a function to check vrr capability based on platform support, DPCD bits and EDID monitor range. v2: * Remove author (Jani N) * Define HAS_VRR (Jani N) * Ensure intel_dp can be obtained from conn (Jani N) v3: * Fix the header indent (Manasi) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125200818.2015-1-manasi.d.navare@intel.com
2021-01-25 20:08:18 +00:00
display/intel_vrr.o \
drm/i915: move modesetting output/encoder code under display/ Add a new subdirectory for display code, and start off by moving modesetting output/encoder code. Judging by the include changes, this is a surprisingly clean operation. v2: - move intel_sdvo_regs.h too - use tabs for Makefile file lists and sort them Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190613084416.6794-2-jani.nikula@intel.com
2019-06-13 08:44:15 +00:00
display/vlv_dsi.o \
display/vlv_dsi_pll.o
drm/i915: Kconfig option to disable the legacy fbdev support Boots Just Fine (tm)! The only glitch seems to be that at least on Fedora the boot splash gets confused and doesn't display much at all. And since there's no ugly console flickering anymore in between, the flicker while switching between X servers (VT support is still enabled) is even more jarring. Also, I'm unsure whether we don't need to somehow kick out vgacon, now that nothing else gets in the way. But stuff seems to work, so I don't care. Also everything still works as well with VGA_CONSOLE=n Also the #ifdef mess needs a bit of a cleanup, follow-up patches will do just that. To keep the Kconfig tidy, extract all the i915 options into its own file. v2: - Rebase on top of the preliminary hw support option and the intel_drv.h cleanup. - Shut up warnings in i915_debugfs.c v3: Use the right CONFIG variable, spotted by Chon Ming. Cc: Lee, Chon Ming <chon.ming.lee@intel.com> Cc: David Herrmann <dh.herrmann@gmail.com> Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-10-09 07:18:51 +00:00
Merge DRM changes from upstream v6.8..v6.9 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.9 RHEL-24102 airlied: fix buddy test to use PAGE_SIZE for now backport s390x fb test fix fix i915 perf table sentinel (upstream removed need for these) JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/accel/drm_accel.c drivers/accel/habanalabs/common/command_submission.c drivers/accel/habanalabs/common/debugfs.c drivers/accel/habanalabs/common/device.c drivers/accel/habanalabs/common/firmware_if.c drivers/accel/habanalabs/common/habanalabs.h drivers/accel/habanalabs/common/hw_queue.c drivers/accel/habanalabs/common/hwmon.c drivers/accel/habanalabs/common/mmu/Makefile drivers/accel/habanalabs/common/mmu/mmu.c drivers/accel/habanalabs/common/mmu/mmu_v1.c drivers/accel/habanalabs/common/mmu/mmu_v2_hr.c drivers/accel/habanalabs/common/security.c drivers/accel/habanalabs/common/security.h drivers/accel/habanalabs/gaudi/gaudi.c drivers/accel/habanalabs/gaudi2/gaudi2.c drivers/accel/habanalabs/gaudi2/gaudi2P.h drivers/accel/habanalabs/goya/goya.c drivers/accel/habanalabs/goya/goya_coresight.c drivers/accel/habanalabs/include/hw_ip/mmu/mmu_general.h drivers/accel/ivpu/ivpu_debugfs.c drivers/accel/ivpu/ivpu_drv.c drivers/accel/ivpu/ivpu_drv.h drivers/accel/ivpu/ivpu_fw.c drivers/accel/ivpu/ivpu_fw_log.c drivers/accel/ivpu/ivpu_gem.c drivers/accel/ivpu/ivpu_gem.h drivers/accel/ivpu/ivpu_hw.h drivers/accel/ivpu/ivpu_hw_37xx.c drivers/accel/ivpu/ivpu_hw_40xx.c drivers/accel/ivpu/ivpu_ipc.c drivers/accel/ivpu/ivpu_job.c drivers/accel/ivpu/ivpu_mmu.c drivers/accel/ivpu/ivpu_pm.c drivers/accel/ivpu/vpu_boot_api.h drivers/accel/ivpu/vpu_jsm_api.h drivers/accel/qaic/mhi_controller.c drivers/accel/qaic/qaic.h drivers/accel/qaic/qaic_data.c drivers/accel/qaic/qaic_drv.c drivers/gpu/drm/i915/display/intel_crtc.c drivers/gpu/drm/mgag200/mgag200_drv.c drivers/gpu/drm/mgag200/mgag200_mode.c drivers/gpu/drm/panel/panel-ilitek-ili9341.c drivers/gpu/drm/tegra/sor.c Conflict resolution: diff --cc drivers/gpu/drm/Kconfig index ea46a61af148,5a0c476361c3..c43e8a298618 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@@ -81,8 -81,7 +80,8 @@@ config DRM_KUNIT_TES select DRM_EXEC select DRM_EXPORT_FOR_TESTS if m select DRM_GEM_SHMEM_HELPER - select DRM_KMS_HELPER select DRM_KUNIT_TEST_HELPERS ++ select DRM_KMS_HELPER select DRM_LIB_RANDOM select PRIME_NUMBERS default KUNIT_ALL_TESTS diff --cc drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 324b46f78b32,1e6cc0bfc432..a0d088e43699 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@@ -3347,10 -3349,13 +3349,13 @@@ static int kfd_mmio_mmap(struct kfd_nod if (vma->vm_end - vma->vm_start != PAGE_SIZE) return -EINVAL; + if (PAGE_SIZE > 4096) + return -EINVAL; + address = dev->adev->rmmio_remap.bus_addr; - vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | - VM_DONTDUMP | VM_PFNMAP); + vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | + VM_DONTDUMP | VM_PFNMAP; vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 73a561af13d1,25593f6aae7d..22b80004574f --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -580,42 -512,13 +512,14 @@@ void intel_pipe_update_start(struct int */ intel_psr_wait_for_idle_locked(new_crtc_state); - local_irq_disable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_disable(); - crtc->debug.min_vbl = min; - crtc->debug.max_vbl = max; + crtc->debug.min_vbl = evade.min; + crtc->debug.max_vbl = evade.max; trace_intel_pipe_update_start(crtc); - for (;;) { - /* - * prepare_to_wait() has a memory barrier, which guarantees - * other CPUs can see the task state update by the time we - * read the scanline. - */ - prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); - - scanline = intel_get_crtc_scanline(crtc); - if (scanline < min || scanline > max) - break; - - if (!timeout) { - drm_err(&dev_priv->drm, - "Potential atomic update failure on pipe %c\n", - pipe_name(crtc->pipe)); - break; - } - - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) - local_irq_enable(); - - timeout = schedule_timeout(timeout); - - if (!IS_ENABLED(CONFIG_PREEMPT_RT)) - local_irq_disable(); - } - - finish_wait(wq, &wait); + scanline = intel_vblank_evade(&evade); drm_crtc_vblank_put(&crtc->base); diff --cc drivers/gpu/drm/i915/i915_drv.h index f3be9033a93f,e81b3b2858ac..8ac1f870b911 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@@ -163,16 -163,8 +163,8 @@@ struct i915_gem_mm struct notifier_block oom_notifier; struct notifier_block vmap_notifier; - struct shrinker *shrinker; + struct shrinker shrinker; - #ifdef CONFIG_MMU_NOTIFIER - /** - * notifier_lock for mmu notifiers, memory may not be allocated - * while holding this lock. - */ - rwlock_t notifier_lock; - #endif - /* shrinker accounting, also useful for userland debugging */ u64 shrink_memory; u32 shrink_count; diff --cc drivers/gpu/drm/i915/intel_runtime_pm.c index 860b51b56a92,d4e844128826..38e42b20aedf --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@@ -246,8 -246,11 +246,8 @@@ static intel_wakeref_t __intel_runtime_ * function, since the power state is undefined. This applies * atm to the late/early system suspend/resume handlers. */ - if ((ignore_usecount && - pm_runtime_get_if_active(rpm->kdev) <= 0) || - (!ignore_usecount && - pm_runtime_get_if_in_use(rpm->kdev) <= 0)) - return 0; + if (pm_runtime_get_if_active(rpm->kdev, ignore_usecount) <= 0) - return 0; ++ return 0; } intel_runtime_pm_acquire(rpm, true); diff --cc drivers/gpu/drm/tegra/sor.c index 89afa6e808b8,bad3b8fcc726..d0ab8b46cf5a --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@@ -16,10 -16,11 +16,11 @@@ #include <soc/tegra/pmc.h> -#include <drm/display/drm_dp_helper.h> -#include <drm/display/drm_scdc_helper.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_debugfs.h> + +#include <drm/display/drm_dp_helper.h> + #include <drm/drm_edid.h> #include <drm/drm_eld.h> #include <drm/drm_file.h> #include <drm/drm_panel.h> diff --cc drivers/video/Makefile index 831c9fa57a6c,831c9fa57a6c..db6568e69be7 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@@ -2,8 -2,8 +2,7 @@@ obj-$(CONFIG_APERTURE_HELPERS) += aperture.o obj-$(CONFIG_VGASTATE) += vgastate.o --obj-$(CONFIG_VIDEO_CMDLINE) += cmdline.o --obj-$(CONFIG_VIDEO_NOMODESET) += nomodeset.o ++obj-$(CONFIG_VIDEO_CMDLINE) += cmdline.o nomodeset.o obj-$(CONFIG_HDMI) += hdmi.o obj-$(CONFIG_VT) += console/ diff --cc redhat/configs/common/generic/CONFIG_DRM_DEBUG_MM index 000000000000,000000000000..117f02c9e72a new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_DEBUG_MM @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_DEBUG_MM is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE index 000000000000,000000000000..f41d366c6b7e new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_I915_DP_TUNNEL index 000000000000,000000000000..fd15321b5596 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_I915_DP_TUNNEL @@@ -1,0 -1,0 +1,1 @@@ ++CONFIG_DRM_I915_DP_TUNNEL=y diff --cc redhat/configs/common/generic/CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE index 000000000000,000000000000..f18775160d7a new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_IMX8MP_HDMI_PVI index 000000000000,000000000000..a2b6a8b10206 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_IMX8MP_HDMI_PVI @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_IMX8MP_HDMI_PVI is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_MGAG200_IOBURST_WORKAROUND index 000000000000,000000000000..24b7b124437c new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_MGAG200_IOBURST_WORKAROUND @@@ -1,0 -1,0 +1,1 @@@ ++CONFIG_DRM_MGAG200_IOBURST_WORKAROUND=y diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A index 000000000000,000000000000..6d37b899099e new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_HIMAX_HX83112A index 000000000000,000000000000..e5411775710c new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_HIMAX_HX83112A @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set diff --cc redhat/configs/common/generic/CONFIG_DRM_PANEL_NOVATEK_NT36672E index 000000000000,000000000000..1511cd4623a8 new file mode 100644 --- /dev/null +++ b/redhat/configs/common/generic/CONFIG_DRM_PANEL_NOVATEK_NT36672E @@@ -1,0 -1,0 +1,1 @@@ ++# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set Commit list: commit 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commit fa68a34ec31b75915463435056493efa388f1b79 commit be4a2a81b6b90d1a47eaeaace4cc8e2cb57b96c7 commit 8d2c930735f850e5be6860aeb39b27ac73ca192f commit 06fbf84f46d20ca3d67f742de2a0a055fbdd2bec commit b61821bb32c5577272408e1b05e6a0879a64257f Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-05-14 00:10:15 +00:00
i915-$(CONFIG_DRM_I915_DP_TUNNEL) += \
display/intel_dp_tunnel.o
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit fa072c0d9240233a281097f1f2a965441654eaa2 commit a388b41a426ebd84ecd8ab12d6aaae7e06344a5b commit a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0 commit 8fa1c7cd1fe9cdfc426a603e1f1eecd3f463c487 commit 31f6a06f0c543b43a38fab10f39e5fc45ad62aa2 commit bc725dc1a8317abb2403b3a906106dbe0d4d4422 commit 8015bee0bfec6920f2441e5adc77e6ac2b65be8b commit 7a61a6aa59e479ee22a859fe4054973d3aa6c640 commit 6f4f8aef7e4220a3369b40a94f694ecc014adf13 commit 942d654171bdaf41bc5c298857c5a342031d8154 commit 29292bc6cc3785d3da6b733a413e387282664f71 commit d541697e8043b7b5d8e1f39b1c046dc140406e82 commit 94232d1637c5675f19a434e5118d0d6718ee310a commit 5fb2e673c76d27436b02cef6c6f9669e106c1b1b commit 0deee706f116778429d03131efb7d29273442d9c commit 04da42b4cc9429d8fff854d144f80396cbdecb46 commit 5067ec645ece12421d802e0dd9510e89122efcc2 commit bfcda58ba1555ac0596d851ae6d748cdebff1af7 commit c39fc2aca32a93d88e4e90ec6f2148b3491ad88f commit 5234105ea8ad0c2655b2cac398c3ae564528eff1 commit 87706a67ad57725470a0512d26ea2aaca700e2d5 commit 5621e0652dc9eeb2be2f7784ceca50ddce1ff025 commit 98a4784e201c22b1bab08b602ccfbe02d9108bec commit 1f3f5eb3b084e91f223d548b0646e8adeeff0779 commit d3e6d002ed203d8beb66cfdf7eed948ed963ef94 commit 514bec3387426f42e88a49bf62f9b0f5eb528b9e commit f2e71d2c6bbb9ebf3e3dfdf533ba2cab413842aa commit 192a4444abc88d0e95966a4bb5085d58bed03162 commit 8d3265a76fcf9f5c5064ecef563ec672d60902d4 commit a1196dac2f504f89bc7941e8c63db50f1fe713f3 commit ffc02c67bf8d4909bd9571fbd14104381fe36b21 commit b662c19654ca7fdb1dadd304ca3e26024fc89635 commit 8d68a0ac9f3f308967bbdf3af37de818a6ed321d commit 9e4db199e66d427c50458f4d72734cc4f0b92948 commit 6ce33a8a45496d4eca27b45ab9b8c2436c657495 commit 80683bf48afcdbebbaf51057e71b2701aa07826d commit 0226ba393eb1a90d63955cc407340c5d506ecacf commit d208d875667e2a29beeec5d475f4b6b164b632fa commit 81de3e296b10a13e5c9f13172825b0d8d9495c68 commit 88b02ebca8b6ea7457bed6809b1dd575420b7544 commit 3db2420422a5912d97966e0176050bb0fc9aa63e commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-y += \
i915_perf.o
drm/i915: Move OA files to separate folder OA files look to be auto-generated so we can keep them all in dedicated subdirectory. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190626123826.39760-1-michal.wajdeczko@intel.com
2019-06-26 12:38:26 +00:00
drm/i915/pxp: load the pxp module when we have a gsc-loaded huc Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2041690 Upstream Status: git://anongit.freedesktop.org/drm/drm commit c5be8fc973830675a6463836e32b9a6e47852447 Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> AuthorDate: Tue Sep 27 17:41:37 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Mon Oct 3 11:29:12 2022 -0700 The mei_pxp module is required to send the command to load authenticate the HuC to the GSC even if pxp is not in use for protected content management. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220928004145.745803-8-daniele.ceraolospurio@intel.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2022-11-28 15:00:47 +00:00
# Protected execution platform (PXP) support. Base support is required for HuC
i915-y += \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
pxp/intel_pxp.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
pxp/intel_pxp_huc.o \
pxp/intel_pxp_tee.o
drm/i915/pxp: load the pxp module when we have a gsc-loaded huc Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2041690 Upstream Status: git://anongit.freedesktop.org/drm/drm commit c5be8fc973830675a6463836e32b9a6e47852447 Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> AuthorDate: Tue Sep 27 17:41:37 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Mon Oct 3 11:29:12 2022 -0700 The mei_pxp module is required to send the command to load authenticate the HuC to the GSC even if pxp is not in use for protected content management. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220928004145.745803-8-daniele.ceraolospurio@intel.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2022-11-28 15:00:47 +00:00
i915-$(CONFIG_DRM_I915_PXP) += \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_debugfs.o \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
pxp/intel_pxp_gsccs.o \
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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commit aa464957f7e660abd554f2546a588f6533720e21 commit 78fed39af1af5d702089fe53076c524646e64997 commit a2fbfd517117157e99160ff1b39b171872dcba07 commit fc74881c28d314b10efac016ef49df4ff40b8b97 commit bf67014d6bda16a72deea11dbbff2a97c705ca92 commit 19e66d512e4182a0461530fa3159638e0f55d97e commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5 commit 7807bf28fe02a76bf112916c6b9194f282f5e43c commit 67f74302f45d5d862f22ced3297624e50ac352f0 commit 4d625a97a7e96be016382e3bb0a3cead05fec153 commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c commit d46f329a3f6048e04736e86cb13c880645048792 commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1 commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464 commit ebae8973884ee9ac703b3bfe34cabbb118b18538 commit 2eb82577a16d4c8eb31e4ed520649850bb95b223 commit d97e631af2db84c8c9d63abf68d487d0bb559e4c commit a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
pxp/intel_pxp_irq.o \
pxp/intel_pxp_pm.o \
drm/i915/pxp: load the pxp module when we have a gsc-loaded huc Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2041690 Upstream Status: git://anongit.freedesktop.org/drm/drm commit c5be8fc973830675a6463836e32b9a6e47852447 Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> AuthorDate: Tue Sep 27 17:41:37 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Mon Oct 3 11:29:12 2022 -0700 The mei_pxp module is required to send the command to load authenticate the HuC to the GSC even if pxp is not in use for protected content management. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220928004145.745803-8-daniele.ceraolospurio@intel.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2022-11-28 15:00:47 +00:00
pxp/intel_pxp_session.o
Merge DRM changes from upstream v5.15..v5.16 This commit was generated using: rhdrm-merge-drm v5.16 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c drivers/gpu/drm/drm_connector.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/i915_gem_object_types.h drivers/gpu/drm/i915/gt/intel_gt_types.h drivers/gpu/drm/i915/intel_uncore.c Conflict resolution: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ I915_BO_ALLOC_CPU_CLEAR | \ - I915_BO_ALLOC_USER) - #define I915_BO_READONLY BIT(4) - #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ - #define I915_BO_WAS_BOUND_BIT 6 - + I915_BO_ALLOC_USER | \ + I915_BO_ALLOC_PM_VOLATILE | \ + I915_BO_ALLOC_PM_EARLY) + #define I915_BO_READONLY BIT(6) + #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */ + #define I915_BO_PROTECTED BIT(8) ++#define I915_BO_WAS_BOUND_BIT 9 /** * @mem_flags - Mutable placement-related flags * diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h index 9fbcbcc6c35d,14216cc471b1..f20687796490 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@@ -72,8 -73,8 +73,10 @@@ struct intel_gt struct intel_uc uc; + struct mutex tlb_invalidate_lock; + + struct i915_wa_list wa_list; + struct intel_gt_timelines { spinlock_t lock; /* protects active_list */ struct list_head active_list; diff --cc drivers/gpu/drm/i915/intel_uncore.c index de8d0558389c,e072054adac5..e21c779cb487 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu continue; } - fw_domains_put(uncore, domain->mask); + if (delayed && + !(domain->uncore->fw_domains_timer & domain->mask)) + fw_domain_arm_timer(domain); + else - uncore->funcs.force_wake_put(uncore, domain->mask); ++ fw_domains_put(uncore, domain->mask); } } @@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct return; spin_lock_irqsave(&uncore->lock, irqflags); - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); + spin_unlock_irqrestore(&uncore->lock, irqflags); +} + +void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, + enum forcewake_domains fw_domains) +{ + unsigned long irqflags; + - if (!uncore->funcs.force_wake_put) ++ if (!uncore->fw_get_funcs) + return; + + spin_lock_irqsave(&uncore->lock, irqflags); + __intel_uncore_forcewake_put(uncore, fw_domains, true); spin_unlock_irqrestore(&uncore->lock, irqflags); } @@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked { lockdep_assert_held(&uncore->lock); - if (!uncore->funcs.force_wake_put) + if (!uncore->fw_get_funcs) return; - __intel_uncore_forcewake_put(uncore, fw_domains); + __intel_uncore_forcewake_put(uncore, fw_domains, false); } void assert_forcewakes_inactive(struct intel_uncore *uncore) Commit list: commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734 commit bc33e71f00a7491810cac9e1335ca97e889d5620 commit 39afa4104bedf214e5779ef20655665723ad48cd commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc commit 0bb50de156d8280e53884adf1d5a04d6108f90e7 commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5 commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819 commit 70418a68713c13da3f36c388087d0220b456a430 commit fa9899dad3ed84a8b6433467670d4cacd9b873bc commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7 commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0 commit 01da701b77d498ed2625483c58bd73000e2767e3 commit c5589bb5dccb0c5cb74910da93663f489589f3ce commit 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a07f8b9983543d465b50870ab4f845d4d710ed3f commit 33735c1c8d0223170d79dbe166976d9cd7339c7a commit 33bb63915fee190102cae7d6576bc51a0bc342b2 commit ee2698cf79cc759a397c61086c758d4cc85938bf commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7 commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd commit eaa090538e8d21801c6d5f94590c3799e6a528b5 commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4 Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
drm/i915: Allow disabling error capture We currently capture the GPU state after we detect a hang. This is vital for us to both triage and debug hangs in the wild (post-mortem debugging). However, it comes at the cost of running some potentially dangerous code (since it has to make very few assumption about the state of the driver) that is quite resource intensive. This patch introduces both a method to disable error capture at runtime (for users who hit bugs at runtime and need a workaround) and to disable error capture at compiletime (for realtime users who want to minimise any possible latency, and never require error capture, saving ~30k of code). The cost is that we now have to be wary of (and test!) a kconfig flag and a module parameter. The effect of the module parameter is easy to verify through code inspection and runtime testing, but a kconfig flag needs regular compile checking. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch Link: http://patchwork.freedesktop.org/patch/msgid/20161012090522.367-2-chris@chris-wilson.co.uk
2016-10-12 09:05:18 +00:00
# Post-mortem debug and GPU hang state capture
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += \
i915_gpu_error.o
drm/i915: Provide a hook for selftests Some pieces of code are independent of hardware but are very tricky to exercise through the normal userspace ABI or via debugfs hooks. Being able to create mock unit tests and execute them through CI is vital. Start by adding a central point where we can execute unit tests and a parameter to enable them. This is disabled by default as the expectation is that these tests will occasionally explode. To facilitate integration with igt, any parameter beginning with i915.igt__ is interpreted as a subtest executable independently via igt/drv_selftest. Two classes of selftests are recognised: mock unit tests and integration tests. Mock unit tests are run as soon as the module is loaded, before the device is probed. At that point there is no driver instantiated and all hw interactions must be "mocked". This is very useful for writing universal tests to exercise code not typically run on a broad range of architectures. Alternatively, you can hook into the live selftests and run when the device has been instantiated - hw interactions are real. v2: Add a macro for compiling conditional code for mock objects inside real objects. v3: Differentiate between mock unit tests and late integration test. v4: List the tests in natural order, use igt to sort after modparam. v5: s/late/live/ v6: s/unsigned long/unsigned int/ v7: Use igt_ prefixes for long helpers. v8: Deobfuscate macros overriding functions, stop using -I$(src) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-1-chris@chris-wilson.co.uk
2017-02-13 17:15:12 +00:00
i915-$(CONFIG_DRM_I915_SELFTEST) += \
Merge DRM changes from upstream v5.14..v5.15 This commit was generated using: rhdrm-merge-drm v5.15 2043115 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115 Conflicts: Makefile drivers/gpu/drm/drm_gem_atomic_helper.c drivers/gpu/drm/drm_gem_framebuffer_helper.c drivers/gpu/drm/gud/gud_pipe.c drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c include/drm/drm_gem_atomic_helper.h include/drm/drm_gem_framebuffer_helper.h Conflict resolution: diff --cc drivers/dma-buf/dma-buf.c index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment } } #endif /* CONFIG_DMA_API_DEBUG */ - return sg_table; } -EXPORT_SYMBOL_GPL(dma_buf_map_attachment); +EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF); /** * dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd goto free; if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) - adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); + adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); } +#ifdef CONFIG_X86_MCE_AMD + if ((adev->asic_type == CHIP_ALDEBARAN) && + (adev->gmc.xgmi.connected_to_cpu)) + amdgpu_register_bad_pages_mca_notifier(); +#endif + return 0; free: diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object unsigned long flags; #define I915_BO_ALLOC_CONTIGUOUS BIT(0) #define I915_BO_ALLOC_VOLATILE BIT(1) - #define I915_BO_ALLOC_STRUCT_PAGE BIT(2) - #define I915_BO_ALLOC_CPU_CLEAR BIT(3) + #define I915_BO_ALLOC_CPU_CLEAR BIT(2) + #define I915_BO_ALLOC_USER BIT(3) #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \ I915_BO_ALLOC_VOLATILE | \ - I915_BO_ALLOC_STRUCT_PAGE | \ - I915_BO_ALLOC_CPU_CLEAR) + I915_BO_ALLOC_CPU_CLEAR | \ + I915_BO_ALLOC_USER) #define I915_BO_READONLY BIT(4) #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */ +#define I915_BO_WAS_BOUND_BIT 6 - /* - * Is the object to be mapped as read-only to the GPU - * Only honoured if hardware has relevant pte bit + /** + * @mem_flags - Mutable placement-related flags + * + * These are flags that indicate specifics of the memory region + * the object is currently in. As such they are only stable + * either under the object lock or if the object is pinned. + */ + unsigned int mem_flags; + #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */ + #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */ + /** + * @cache_level: The desired GTT caching level. + * + * See enum i915_cache_level for possible values, along with what + * each does. */ unsigned int cache_level:3; - unsigned int cache_coherent:2; + /** + * @cache_coherent: + * + * Track whether the pages are coherent with the GPU if reading or + * writing through the CPU caches. The largely depends on the + * @cache_level setting. + * + * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom + * platforms, coherency must be explicitly requested with some special + * GTT caching bits(see enum i915_cache_level). When enabling coherency + * it does come at a performance and power cost on such platforms. On + * the flip side the kernel does not need to manually flush any buffers + * which need to be coherent with the GPU, if the object is not coherent + * i.e @cache_coherent is zero. + * + * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory + * access will automatically snoop the CPU caches(even with CACHE_NONE). + * The one exception is when dealing with the display engine, like with + * scanout surfaces. To handle this the kernel will always flush the + * surface out of the CPU caches when preparing it for scanout. Also + * note that since scanout surfaces are only ever read by the display + * engine we only need to care about flushing any writes through the CPU + * cache, reads on the other hand will always be coherent. + * + * Something strange here is why @cache_coherent is not a simple + * boolean, i.e coherent vs non-coherent. The reasoning for this is back + * to the display engine not being fully coherent. As a result scanout + * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT. + * In the case of seeing I915_CACHE_NONE the kernel makes the assumption + * that this is likely a scanout surface, and will set @cache_coherent + * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared + * LLC. The kernel uses this to always flush writes through the CPU + * cache as early as possible, where it can, in effect keeping + * @cache_dirty clean, so we can potentially avoid stalling when + * flushing the surface just before doing the scanout. This does mean + * we might unnecessarily flush non-scanout objects in some places, but + * the default assumption is that all normal objects should be using + * I915_CACHE_LLC, at least on platforms with the shared LLC. + * + * Supported values: + * + * I915_BO_CACHE_COHERENT_FOR_READ: + * + * On shared LLC platforms, we use this for special scanout surfaces, + * where the display engine is not coherent with the CPU cache. As such + * we need to ensure we flush any writes before doing the scanout. As an + * optimisation we try to flush any writes as early as possible to avoid + * stalling later. + * + * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC + * platforms, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ + * + * While for normal objects that are fully coherent, including special + * scanout surfaces marked as I915_CACHE_WT, we use: + * + * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ | + * I915_BO_CACHE_COHERENT_FOR_WRITE + * + * And then for objects that are not coherent at all we use: + * + * cache_coherent = 0 + * + * I915_BO_CACHE_COHERENT_FOR_WRITE: + * + * When writing through the CPU cache, the GPU is still coherent. Note + * that this also implies I915_BO_CACHE_COHERENT_FOR_READ. + */ #define I915_BO_CACHE_COHERENT_FOR_READ BIT(0) #define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1) + unsigned int cache_coherent:2; + + /** + * @cache_dirty: + * + * Track if we are we dirty with writes through the CPU cache for this + * object. As a result reading directly from main memory might yield + * stale data. + * + * This also ties into whether the kernel is tracking the object as + * coherent with the GPU, as per @cache_coherent, as it determines if + * flushing might be needed at various points. + * + * Another part of @cache_dirty is managing flushing when first + * acquiring the pages for system memory, at this point the pages are + * considered foreign, so the default assumption is that the cache is + * dirty, for example the page zeroing done by the kernel might leave + * writes though the CPU cache, or swapping-in, while the actual data in + * main memory is potentially stale. Note that this is a potential + * security issue when dealing with userspace objects and zeroing. Now, + * whether we actually need apply the big sledgehammer of flushing all + * the pages on acquire depends on if @cache_coherent is marked as + * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent + * for both reads and writes though the CPU cache. + * + * Note that on shared LLC platforms we still apply the heavy flush for + * I915_CACHE_NONE objects, under the assumption that this is going to + * be used for scanout. + * + * Update: On some hardware there is now also the 'Bypass LLC' MOCS + * entry, which defeats our @cache_coherent tracking, since userspace + * can freely bypass the CPU cache when touching the pages with the GPU, + * where the kernel is completely unaware. On such platform we need + * apply the sledgehammer-on-acquire regardless of the @cache_coherent. + */ unsigned int cache_dirty:1; /** diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c index b9aaf640f372,6109cd9e3399..e7efd9ede8e4 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de struct nvkm_client *client; struct nvkm_device *device; - drm_dev_unregister(dev); + drm_dev_unplug(dev); - dev->irq_enabled = false; client = nvxx_client(&drm->client.base); device = nvkm_device_find(client->device); diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c index f9d399ea628d,e50fb82a3030..2aceac7856e2 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c @@@ -28,9 -28,10 +28,10 @@@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> -#include <linux/mem_encrypt.h> +#include <linux/cc_platform.h> #include <asm/hypervisor.h> + #include <drm/drm_ioctl.h> #include "vmwgfx_drv.h" #include "vmwgfx_msg_x86.h" @@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st unsigned long msg_len = strlen(msg); /* HB port can't access encrypted memory. */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_high; + u32 channel_id = (channel->channel_id << 16); si = (uintptr_t) msg; di = channel->cookie_low; @@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str unsigned long si, di, eax, ebx, ecx, edx; /* HB port can't access encrypted memory */ - if (hb && !mem_encrypt_active()) { + if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) { unsigned long bp = channel->cookie_low; + u32 channel_id = (channel->channel_id << 16); si = channel->cookie_high; di = (uintptr_t) reply; Commit list: commit 241a9e233e7cf1001d09426c9fc520768f8961bf commit 4154fa0e2688118ba3dbc67aa834435463f9ea68 commit 3faea9939a3d1eb5a40f3f6100c24792865b6445 commit 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commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7 commit fcf918ffd3b35e288097036c04af7446b2c6f2f1 commit 9761ffb8f1090289b908590039e2c363cc35cf45 commit 6e6f96630805874fa80b0067e1a57aafc06225f6 commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2 commit defbbcd99fa68cb7feed453662048baa87e9a441 commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5 commit 54149d13f369e1ab02f36b91feee02069184c1d8 commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e commit 19928833e8f8fa5ee687c451437ce674f19d6c09 commit 79516af3497a5b89acb09f4a644f61d6c69e5f16 commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626 commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
gem/selftests/i915_gem_client_blt.o \
drm/i915: Move more GEM objects under gem/ Continuing the theme of separating out the GEM clutter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-8-chris@chris-wilson.co.uk
2019-05-28 09:29:49 +00:00
gem/selftests/igt_gem_utils.o \
drm/i915: Provide a hook for selftests Some pieces of code are independent of hardware but are very tricky to exercise through the normal userspace ABI or via debugfs hooks. Being able to create mock unit tests and execute them through CI is vital. Start by adding a central point where we can execute unit tests and a parameter to enable them. This is disabled by default as the expectation is that these tests will occasionally explode. To facilitate integration with igt, any parameter beginning with i915.igt__ is interpreted as a subtest executable independently via igt/drv_selftest. Two classes of selftests are recognised: mock unit tests and integration tests. Mock unit tests are run as soon as the module is loaded, before the device is probed. At that point there is no driver instantiated and all hw interactions must be "mocked". This is very useful for writing universal tests to exercise code not typically run on a broad range of architectures. Alternatively, you can hook into the live selftests and run when the device has been instantiated - hw interactions are real. v2: Add a macro for compiling conditional code for mock objects inside real objects. v3: Differentiate between mock unit tests and late integration test. v4: List the tests in natural order, use igt to sort after modparam. v5: s/late/live/ v6: s/unsigned long/unsigned int/ v7: Use igt_ prefixes for long helpers. v8: Deobfuscate macros overriding functions, stop using -I$(src) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-1-chris@chris-wilson.co.uk
2017-02-13 17:15:12 +00:00
selftests/i915_random.o \
drm/i915/selftests: Refactor common flush_test() Pull igt_flush_test() out into its own library before copying and pasting the code for a third time. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180505091014.26126-1-chris@chris-wilson.co.uk
2018-05-05 09:10:13 +00:00
selftests/i915_selftest.o \
drm/i915/selftests: Move igt_atomic_section[] out of the header Move the definition of the igt_atomic_section[] into a C file, leaving the declaration in the header so as not to upset headertest! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200103104516.1757103-1-chris@chris-wilson.co.uk
2020-01-03 10:45:15 +00:00
selftests/igt_atomic.o \
drm/i915/selftests: Extract spinner code Pull out spinner code to a standalone file to enable it to be shortly used by other and new test cases. Plain code movement - no functional changes. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181130080254.15383-1-tvrtko.ursulin@linux.intel.com
2018-11-30 08:02:53 +00:00
selftests/igt_flush_test.o \
drm/i915/selftests: Refactor common live_test framework Before adding yet another copy of struct live_test and its handler, refactor the existing code into a common framework for live selftests. For many live selftests, we want to know if the GPU hung or otherwise misbehaved during the execution of the test (beyond any infraction in the behaviour under test), live_test provides this by comparing the GPU state before and after, alerting if it unexpectedly changed (e.g. the reset counter changed). It also ensures that the GPU is idle before and after the test, so that residual code running on the GPU is flushed before testing. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190121222117.23305-5-chris@chris-wilson.co.uk
2019-01-21 22:20:47 +00:00
selftests/igt_live_test.o \
drm/i915/selftests: Wrap vm_mmap() around GEM objects Provide a utility function to create a vma corresponding to an mmap() of our device. And use it to exercise the equivalent of userspace performing a GTT mmap of our objects. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191107180601.30815-4-chris@chris-wilson.co.uk
2019-11-07 18:06:00 +00:00
selftests/igt_mmap.o \
drm/i915/selftests: Add tests for GT and engine workaround verification Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is not affecting workarounds not belonging to itself.) v2: * Rebase for series refactoring. * Add spinner for actual engine reset! * Add idle reset test as well. (Chris Wilson) * Share existing global_reset_lock. (Chris Wilson) v3: * intel_engine_verify_workarounds can be static. * API rename. (Chris Wilson) * Move global reset lock out of the loop. (Chris Wilson) v4: * Add missing rpm puts. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181203125014.3219-5-tvrtko.ursulin@linux.intel.com
2018-12-03 12:50:11 +00:00
selftests/igt_reset.o \
drm/i915/selftests: Move gpu energy measurement into its own little lib Move the handy utility to measure the GPU energy consumption using RAPL msr into a common lib so that it can be reused easily. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200417152018.13079-1-chris@chris-wilson.co.uk
2020-04-17 15:20:17 +00:00
selftests/igt_spinner.o \
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
selftests/intel_scheduler_helpers.o \
drm/i915/selftests: Move gpu energy measurement into its own little lib Move the handy utility to measure the GPU energy consumption using RAPL msr into a common lib so that it can be reused easily. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200417152018.13079-1-chris@chris-wilson.co.uk
2020-04-17 15:20:17 +00:00
selftests/librapl.o
drm/i915: Allow disabling error capture We currently capture the GPU state after we detect a hang. This is vital for us to both triage and debug hangs in the wild (post-mortem debugging). However, it comes at the cost of running some potentially dangerous code (since it has to make very few assumption about the state of the driver) that is quite resource intensive. This patch introduces both a method to disable error capture at runtime (for users who hit bugs at runtime and need a workaround) and to disable error capture at compiletime (for realtime users who want to minimise any possible latency, and never require error capture, saving ~30k of code). The cost is that we now have to be wary of (and test!) a kconfig flag and a module parameter. The effect of the module parameter is easy to verify through code inspection and runtime testing, but a kconfig flag needs regular compile checking. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch Link: http://patchwork.freedesktop.org/patch/msgid/20161012090522.367-2-chris@chris-wilson.co.uk
2016-10-12 09:05:18 +00:00
drm/i915: Introduce a PV INFO page structure for Intel GVT-g. Introduce a PV INFO structure, to facilitate the Intel GVT-g technology, which is a GPU virtualization solution with mediated pass-through. This page contains the shared information between i915 driver and the host emulator. For now, this structure utilizes an area of 4K bytes on HSW GPU's unused MMIO space. Future hardware will have the reserved window architecturally defined, and layout of the page will be added in future BSpec. The i915 driver load routine detects if it is running in a VM by reading the contents of this PV INFO page. Thereafter a flag, vgpu.active is set, and intel_vgpu_active() is used by checking this flag to conclude if GPU is virtualized with Intel GVT-g. By now, intel_vgpu_active() will return true, only when the driver is running as a guest in the Intel GVT-g enhanced environment on HSW platform. v2: take Chris' comments: - call the i915_check_vgpu() in intel_uncore_init() - sanitize i915_check_vgpu() by adding BUILD_BUG_ON() and debug info take Daniel's comments: - put the definition of PV INFO into a new header - i915_vgt_if.h other changes: - access mmio regs by readq/readw in i915_check_vgpu() v3: take Daniel's comments: - move the i915/vgt interfaces into a new i915_vgpu.c - update makefile - add kerneldoc to functions which are non-static - add a DOC: section describing some of the high-level design - update drm docbook other changes: - rename i915_vgt_if.h to i915_vgpu.h v4: take Tvrtko's comments: - fix a typo in commit message - add debug message when vgt version mismatches - rename low_gmadr/high_gmadr to mappable/non-mappable in PV INFO structure Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Jike Song <jike.song@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-10 11:05:47 +00:00
# virtual gpu code
Merge DRM changes from upstream v6.7..v6.8 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.8 RHEL-24102 JIRA: https://issues.redhat.com/browse/RHEL-24102 Conflicts: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h drivers/gpu/drm/amd/display/dc/link/link_factory.c drivers/gpu/drm/bridge/ti-tpd12s015.c drivers/gpu/drm/display/drm_dp_mst_topology.c drivers/gpu/drm/drm_vm.c drivers/gpu/drm/i915/display/intel_dp_mst.c drivers/gpu/drm/panel/panel-edp.c drivers/gpu/drm/tegra/sor.c drivers/gpu/drm/tests/drm_buddy_test.c drivers/gpu/drm/tests/drm_mm_test.c Conflict resolution: Commit list: commit 501069dad5214fafe1b8ba38fa26a5d07df784c3 commit 3594d00b71eea66d183b310c19aa5a6bf4206e62 commit f17c08a6046f0c9383a61d7009216b0ad3369db4 commit 26eb4fcf2349b3dc02ee6f96925419eb7b3026d0 commit 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commit 27a6c49394b1a203beeb94752c9a1d6318f24ddf commit bae67893578d608e35691dcdfa90c4957debf1d3 commit 9671761792156f2339627918bafcd713a8a6f777 commit bbfaf2aea7164db59739728d62d9cc91d64ff856 commit 1fa8d07ae1a5fa4e87de42c338e8fc27f46d8bb6 commit f581dbb34c39d23a05d77f09c65915022fafaaeb commit 741922e7fbfddfd2dff29e24fc24b2b565db3369 commit bfc7746a044c2648d81522a31089be9b816b8ebc commit 7c548869f5f52db65b40d619c833bbafbc5cedba commit 1d492944d3d06047793fa2e7606868f6d7480f87 commit 3f4d8aac6e768c2215ce68275256971c2f54f0c8 commit 72fa02fdf83306c52bc1eede28359e3fa32a151a commit 9ee485bdda68d6d3f5728cbe3150eb9013d7d22b commit e5ca263508f7e9d2cf711edf3258d11ca087885c commit 06b7ef70b1f29de685ea80f0c1b8f0a0b0e16d18 commit cb2b7d6f8c96414e1ab63c5f6e89d1c66a8b1078 commit 20dfa63d7379408edfcae8bda8ef5ea44d7b357f commit 86bf8cfda6d2a6720fa2e6e676c98f0882c9d3d7 commit 2f910859724b53f1cd3579246e3d9bebb16d78b8 commit 9d3f8a723c7950e56e0b95ab84b572caee29e065 commit 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commit 8188cae3cc3d8018ec97ca9ab8caa3acc69a056d commit 01bb1ae35006e473138c90711bad1a6b614a1823 commit 45046af3d0c2d6f4f1953f7f07cd1b34ffc86498 commit aa5fe428d52aa65fa1c928c00c4cdb131529736b commit f060e461ea3ef75fa17fd3f943934fe8af51206d commit f7916c47f66d778817068d86e5c9b5e511e23c86 commit f6ecfdad359a01c7fd8a3bcfde3ef0acdf107e6e commit 72e6d668773fd19f78a6e8017347b08a5cccaaeb commit 9dfc46c87cdc8f5a42a71de247a744a6b8188980 commit d6a209dd76e5ceb5d536e0a1a707ffcf64f95cef commit 0b385be4c3ccd5636441923d7cad5eda6b4651cb commit daf8739c3322a762ce84f240f50e0c39181a41ab commit 95bf25bb9ed5dedb7fb39f76489f7d6843ab0475 commit 26d2b757fff02bbe971abc39071e263aa0cab924 commit 0848814aa296ca13e4f03848f35d2d29fc7fc30c commit 984318aaf7b6516d03a2971a4a37bab4ea648461 commit 317f86dc1b8e219e799271042a17d56a95a935bc commit 6601c15c8a0680edb0d23a13151adb8023959149 commit e9098cc9aef13bd56e821f628c83f709d3347af1 commit 937844d661354bf142dc1c621396fdab10ecbacc commit 0dafaf659cc463f2db0af92003313a8bc46781cd commit a4e7596e209783a7be2727d6b947cbd863c2bbcb commit 4ece8fc439c370b1aec26a44b9f94fb214068d42 commit 3a397b131d16305792dc940057e5df84a5b4247c commit b3cdb1928fa81c3e3d2111f9376c455958f86678 commit 83c34dcbe0e947495961e5f6efaadb67004071b5 commit b7cc4ff787a572edf2c55caeffaa88cd801eb135 Signed-off-by: Dave Airlie <airlied@redhat.com>
2024-04-04 07:23:03 +00:00
i915-y += \
i915_vgpu.o
drm/i915: Introduce a PV INFO page structure for Intel GVT-g. Introduce a PV INFO structure, to facilitate the Intel GVT-g technology, which is a GPU virtualization solution with mediated pass-through. This page contains the shared information between i915 driver and the host emulator. For now, this structure utilizes an area of 4K bytes on HSW GPU's unused MMIO space. Future hardware will have the reserved window architecturally defined, and layout of the page will be added in future BSpec. The i915 driver load routine detects if it is running in a VM by reading the contents of this PV INFO page. Thereafter a flag, vgpu.active is set, and intel_vgpu_active() is used by checking this flag to conclude if GPU is virtualized with Intel GVT-g. By now, intel_vgpu_active() will return true, only when the driver is running as a guest in the Intel GVT-g enhanced environment on HSW platform. v2: take Chris' comments: - call the i915_check_vgpu() in intel_uncore_init() - sanitize i915_check_vgpu() by adding BUILD_BUG_ON() and debug info take Daniel's comments: - put the definition of PV INFO into a new header - i915_vgt_if.h other changes: - access mmio regs by readq/readw in i915_check_vgpu() v3: take Daniel's comments: - move the i915/vgt interfaces into a new i915_vgpu.c - update makefile - add kerneldoc to functions which are non-static - add a DOC: section describing some of the high-level design - update drm docbook other changes: - rename i915_vgt_if.h to i915_vgpu.h v4: take Tvrtko's comments: - fix a typo in commit message - add debug message when vgt version mismatches - rename low_gmadr/high_gmadr to mappable/non-mappable in PV INFO structure Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com> Signed-off-by: Jike Song <jike.song@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-02-10 11:05:47 +00:00
drm/i915/gvt: better align the Makefile with i915 Makefile Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2124620 commit 7f0cf30187cdb1f04d905505ffde910cecf1b35e Author: Jani Nikula <jani.nikula@intel.com> Date: Wed Apr 13 15:25:39 2022 +0300 drm/i915/gvt: better align the Makefile with i915 Makefile Drop extra ccflags, drop extra intermediate variables, list object files one per line alphabetically. Cc: Zhi Wang <zhi.wang.linux@gmail.com> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/8bc0895376c077156a671e24ac6a5c75b7db4c9c.1649852517.git.jani.nikula@intel.com Reviewed-by: Zhi Wang <zhi.a.wang@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2022-08-02 20:41:59 +00:00
i915-$(CONFIG_DRM_I915_GVT) += \
intel_gvt.o \
intel_gvt_mmio_table.o
drm/i915: gvt: Introduce the basic architecture of GVT-g This patch introduces the very basic framework of GVT-g device model, includes basic prototypes, definitions, initialization. v12: - Call intel_gvt_init() in driver early initialization stage. (Chris) v8: - Remove the GVT idr and mutex in intel_gvt_host. (Joonas) v7: - Refine the URL link in Kconfig. (Joonas) - Refine the introduction of GVT-g host support in Kconfig. (Joonas) - Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas) - Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas) - Remove {alloc, free}_gvt_device() - Rename intel_gvt_{create, destroy}_gvt_device() - Expost intel_gvt_init_host() - Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas) v6: - Refine introduction in Kconfig. (Chris) - The exposed API functions will take struct intel_gvt * instead of void *. (Chris/Tvrtko) - Remove most memebers of strct intel_gvt_device_info. Will add them in the device model patches.(Chris) - Remove gvt_info() and gvt_err() in debug.h. (Chris) - Move GVT kernel parameter into i915_params. (Chris) - Remove include/drm/i915_gvt.h, as GVT-g will be built within i915. - Remove the redundant struct i915_gvt *, as the functions in i915 will directly take struct intel_gvt *. - Add more comments for reviewer. v5: Take Tvrtko's comments: - Fix the misspelled words in Kconfig - Let functions take drm_i915_private * instead of struct drm_device * - Remove redundant prints/local varible initialization v3: Take Joonas' comments: - Change file name i915_gvt.* to intel_gvt.* - Move GVT kernel parameter into intel_gvt.c - Remove redundant debug macros - Change error handling style - Add introductions for some stub functions - Introduce drm/i915_gvt.h. Take Kevin's comments: - Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c v2: - Introduce i915_gvt.c. It's necessary to introduce the stubs between i915 driver and GVT-g host, as GVT-g components is configurable in kernel config. When disabled, the stubs here do nothing. Take Joonas' comments: - Replace boolean return value with int. - Replace customized info/warn/debug macros with DRM macros. - Document all non-static functions like i915. - Remove empty and unused functions. - Replace magic number with marcos. - Set GVT-g in kernel config to "n" by default. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 12:07:00 +00:00
include $(src)/gvt/Makefile
drm/i915: Use remap_io_mapping() to prefault all PTE in a single pass Very old numbers indicate this is a 66% improvement when remapping the entire object for fence contention - due to the elimination of track_pfn_insert and its strcmp. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Testcase: igt/gem_fence_upload/performance Testcase: igt/gem_mmap_gtt Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160819155428.1670-6-chris@chris-wilson.co.uk
2016-08-19 15:54:28 +00:00
obj-$(CONFIG_DRM_I915) += i915.o
drm/i915/gvt: move the gvt code into kvmgt.ko Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2124620 commit 8b750bf744181ca3eadfb288830d2f42b04adc67 Author: Christoph Hellwig <hch@lst.de> Date: Mon Apr 11 16:13:35 2022 +0200 drm/i915/gvt: move the gvt code into kvmgt.ko Instead of having an option to build the gvt code into the main i915 module, just move it into the kvmgt.ko module. This only requires a new struct with three entries that the KVMGT modules needs to register with the main i915 module, and a proper list of GVT-enabled devices instead of global device pointer. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20220411141403.86980-7-hch@lst.de Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2022-08-02 20:42:22 +00:00
obj-$(CONFIG_DRM_I915_GVT_KVMGT) += kvmgt.o
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
# kernel-doc test
#
# Enable locally for CONFIG_DRM_I915_WERROR=y. See also scripts/Makefile.build
ifdef CONFIG_DRM_I915_WERROR
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
cmd_checkdoc = $(srctree)/scripts/kernel-doc -none -Werror $<
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
endif
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
# header test
# exclude some broken headers from the test coverage
no-header-test := \
drm/i915/gvt: make mpt.h self-contained Add necessary #includes and forward declarations to make the header compile on its own. Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/73958c4ed1d94aa581acd91f7d7e82785b13d07e.1607422863.git.jani.nikula@intel.com
2020-12-08 10:29:14 +00:00
display/intel_vbt_defs.h
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
kbuild: use always-y instead of extra-y As commit d0e628cd817f ("kbuild: doc: clarify the difference between extra-y and always-y") explained, extra-y should be used for listing the prerequisites of vmlinux. These targets are not related to vmlinux. always-y is a better fix. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2021-01-20 06:23:51 +00:00
always-$(CONFIG_DRM_I915_WERROR) += \
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
$(patsubst %.h,%.hdrtest, $(filter-out $(no-header-test), \
Revert "kbuild: use $(src) instead of $(srctree)/$(src) for source directory" This reverts commit b1992c3772e69a6fd0e3fc81cd4d2820c8b6eca0. JIRA: https://issues.redhat.com/browse/RHEL-76500 Upstream Status: RHEL-only It's a partial revert, only the changes in drivers/gpu/drm that were backported are reverted. This caused build error, if you try to build with "O=" Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2025-02-04 13:25:39 +00:00
$(shell cd $(srctree)/$(src) && find * -name '*.h')))
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
Merge DRM changes from upstream v6.3..v6.4 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.4 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c drivers/gpu/drm/amd/display/dc/core/dc.c drivers/gpu/drm/amd/display/dc/dc.h drivers/gpu/drm/amd/display/dc/dc_dp_types.h drivers/gpu/drm/amd/display/dc/dc_types.h drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/display/dc/inc/link.h drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c drivers/gpu/drm/amd/display/dc/link/link_detection.c drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c drivers/gpu/drm/drm_displayid.c drivers/gpu/drm/drm_fb_helper.c drivers/gpu/drm/gma500/framebuffer.c drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c drivers/gpu/drm/i915/gt/intel_workarounds.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c Conflict resolution: diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0eb51c3a69a7,7acd73e5004f..11e99e8ca7ba --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@@ -350,35 -348,46 +348,75 @@@ static inline bool is_dc_timing_adjust_ return false; } + static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, + int planes_count) + { + int i, j; + + for (i = 0, j = planes_count - 1; i < j; i++, j--) + swap(array_of_surface_update[i], array_of_surface_update[j]); + } + + /** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ + static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) + { + reverse_planes_order(array_of_surface_update, planes_count); + + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); + } + +/** + * update_planes_and_stream_adapter() - Send planes to be updated in DC + * + * DC has a generic way to update planes and stream via + * dc_update_planes_and_stream function; however, DM might need some + * adjustments and preparation before calling it. This function is a wrapper + * for the dc_update_planes_and_stream that does any required configuration + * before passing control to DC. + */ +static inline bool update_planes_and_stream_adapter(struct dc *dc, + int update_type, + int planes_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_surface_update *array_of_surface_update) +{ + /* + * Previous frame finished and HW is ready for optimization. + */ + if (update_type == UPDATE_TYPE_FAST) + dc_post_update_surfaces_to_stream(dc); + + return dc_update_planes_and_stream(dc, + array_of_surface_update, + planes_count, + stream, + stream_update); +} + /** * dm_pflip_high_irq() - Handle pageflip interrupt * @interrupt_params: ignored @@@ -7901,16 -7905,16 +7931,23 @@@ static void amdgpu_dm_commit_cursors(st */ for_each_old_plane_in_state(state, plane, old_plane_state, i) if (plane->type == DRM_PLANE_TYPE_CURSOR) - handle_cursor_update(plane, old_plane_state); + amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); + } + + static inline uint32_t get_mem_type(struct drm_framebuffer *fb) + { + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; } +static inline uint32_t get_mem_type(struct drm_framebuffer *fb) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); + + return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; +} + static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_state *dc_state, struct drm_device *dev, diff --cc drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 862cb0f93b7d,18e098568cb4..3f047c985406 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@@ -142,49 -134,347 +134,391 @@@ void dc_restore_link_res_map(const stru bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx) { - return link_update_dsc_config(pipe_ctx); + struct dc_link *link = pipe_ctx->stream->link; + + return link->dc->link_srv->update_dsc_config(pipe_ctx); + } + + bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) + { + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; + } + + bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) + { + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + } + + bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) + { + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; + } + + void dc_link_dp_handle_automated_test(struct dc_link *link) + { + link->dc->link_srv->dp_handle_automated_test(link); + } + + bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + enum dp_test_pattern_color_space test_pattern_color_space, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size) + { + return link->dc->link_srv->dp_set_test_pattern(link, test_pattern, + test_pattern_color_space, p_link_settings, + p_custom_pattern, cust_pattern_size); + } + + void dc_link_set_drive_settings(struct dc *dc, + struct link_training_settings *lt_settings, + struct dc_link *link) + { + struct link_resource link_res; + + dc->link_srv->get_cur_link_res(link, &link_res); + dc->link_srv->dp_set_drive_settings(link, &link_res, lt_settings); + } + + void dc_link_set_preferred_link_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link *link) + { + dc->link_srv->dp_set_preferred_link_settings(dc, link_setting, link); + } + + void dc_link_set_preferred_training_settings(struct dc *dc, + struct dc_link_settings *link_setting, + struct dc_link_training_overrides *lt_overrides, + struct dc_link *link, + bool skip_immediate_retrain) + { + dc->link_srv->dp_set_preferred_training_settings(dc, link_setting, + lt_overrides, link, skip_immediate_retrain); + } + + bool dc_dp_trace_is_initialized(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_is_initialized(link); + } + + void dc_dp_trace_set_is_logged_flag(struct dc_link *link, + bool in_detection, + bool is_logged) + { + link->dc->link_srv->dp_trace_set_is_logged_flag(link, in_detection, is_logged); + } + + bool dc_dp_trace_is_logged(struct dc_link *link, bool in_detection) + { + return link->dc->link_srv->dp_trace_is_logged(link, in_detection); + } + + unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_end_timestamp(link, in_detection); + } + + const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, + bool in_detection) + { + return link->dc->link_srv->dp_trace_get_lt_counts(link, in_detection); + } + + unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) + { + return link->dc->link_srv->dp_trace_get_link_loss_count(link); + } + + struct dc_sink *dc_link_add_remote_sink( + struct dc_link *link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data) + { + return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); + } + + void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) + { + link->dc->link_srv->remove_remote_sink(link, sink); + } + + int dc_link_aux_transfer_raw(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) + { + const struct dc *dc = ddc->link->dc; + + return dc->link_srv->aux_transfer_raw( + ddc, payload, operation_result); + } + + uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw) + { + return dc->link_srv->bw_kbps_from_raw_frl_link_rate_data(bw); + } + + bool dc_link_decide_edp_link_settings(struct dc_link *link, + struct dc_link_settings *link_setting, uint32_t req_bw) + { + return link->dc->link_srv->edp_decide_link_settings(link, link_setting, req_bw); + } + + + bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, + struct dc_link_settings *max_link_enc_cap) + { + return link->dc->link_srv->dp_get_max_link_enc_cap(link, max_link_enc_cap); + } + + enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( + const struct dc_link *link) + { + return link->dc->link_srv->mst_decide_link_encoding_format(link); + } + + const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link) + { + return link->dc->link_srv->dp_get_verified_link_cap(link); + } + + bool dc_link_is_dp_sink_present(struct dc_link *link) + { + return link->dc->link_srv->dp_is_sink_present(link); + } + + bool dc_link_is_fec_supported(const struct dc_link *link) + { + return link->dc->link_srv->dp_is_fec_supported(link); + } + + void dc_link_overwrite_extended_receiver_cap( + struct dc_link *link) + { + link->dc->link_srv->dp_overwrite_extended_receiver_cap(link); + } + + bool dc_link_should_enable_fec(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_enable_fec(link); + } + + int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( + struct dc_link *link, int peak_bw) + { + return link->dc->link_srv->dpia_handle_usb4_bandwidth_allocation_for_link(link, peak_bw); + } + + void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, uint8_t bw, uint8_t result) + { + link->dc->link_srv->dpia_handle_bw_alloc_response(link, bw, result); + } + + bool dc_link_check_link_loss_status( + struct dc_link *link, + union hpd_irq_data *hpd_irq_dpcd_data) + { + return link->dc->link_srv->dp_parse_link_loss_status(link, hpd_irq_dpcd_data); + } + + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link) + { + return link->dc->link_srv->dp_should_allow_hpd_rx_irq(link); + } + + void dc_link_dp_handle_link_loss(struct dc_link *link) + { + link->dc->link_srv->dp_handle_link_loss(link); + } + + enum dc_status dc_link_dp_read_hpd_rx_irq_data( + struct dc_link *link, + union hpd_irq_data *irq_data) + { + return link->dc->link_srv->dp_read_hpd_rx_irq_data(link, irq_data); + } + + bool dc_link_handle_hpd_rx_irq(struct dc_link *link, + union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work) + { + return link->dc->link_srv->dp_handle_hpd_rx_irq(link, out_hpd_irq_dpcd_data, + out_link_loss, defer_handling, has_left_work); + } + + void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on) + { + link->dc->link_srv->dpcd_write_rx_power_ctrl(link, on); + } + + enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, + struct dc_link_settings *link_setting) + { + return link->dc->link_srv->dp_decide_lttpr_mode(link, link_setting); + } + + void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd) + { + link->dc->link_srv->edp_panel_backlight_power_on(link, wait_for_hpd); + } + + int dc_link_get_backlight_level(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_backlight_level(link); + } + + bool dc_link_get_backlight_level_nits(struct dc_link *link, + uint32_t *backlight_millinits_avg, + uint32_t *backlight_millinits_peak) + { + return link->dc->link_srv->edp_get_backlight_level_nits(link, + backlight_millinits_avg, + backlight_millinits_peak); + } + + bool dc_link_set_backlight_level(const struct dc_link *link, + uint32_t backlight_pwm_u16_16, + uint32_t frame_ramp) + { + return link->dc->link_srv->edp_set_backlight_level(link, + backlight_pwm_u16_16, frame_ramp); + } + + bool dc_link_set_backlight_level_nits(struct dc_link *link, + bool isHDR, + uint32_t backlight_millinits, + uint32_t transition_time_in_ms) + { + return link->dc->link_srv->edp_set_backlight_level_nits(link, isHDR, + backlight_millinits, transition_time_in_ms); + } + + int dc_link_get_target_backlight_pwm(const struct dc_link *link) + { + return link->dc->link_srv->edp_get_target_backlight_pwm(link); + } + + bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state) + { + return link->dc->link_srv->edp_get_psr_state(link, state); + } + + bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active, + bool wait, bool force_static, const unsigned int *power_opts) + { + return link->dc->link_srv->edp_set_psr_allow_active(link, allow_active, wait, + force_static, power_opts); + } + + bool dc_link_setup_psr(struct dc_link *link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context) + { + return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context); + } + + bool dc_link_wait_for_t12(struct dc_link *link) + { + return link->dc->link_srv->edp_wait_for_t12(link); + } + + bool dc_link_get_hpd_state(struct dc_link *link) + { + return link->dc->link_srv->get_hpd_state(link); + } + + void dc_link_enable_hpd(const struct dc_link *link) + { + link->dc->link_srv->enable_hpd(link); + } + + void dc_link_disable_hpd(const struct dc_link *link) + { + link->dc->link_srv->disable_hpd(link); + } + + void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) + { + link->dc->link_srv->enable_hpd_filter(link, enable); + } + + bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count) + { + return dc->link_srv->validate_dpia_bandwidth(streams, count); } + +bool dc_is_oem_i2c_device_present( + struct dc *dc, + size_t slave_address) +{ + if (dc->res_pool->oem_device) + return dce_i2c_oem_device_present( + dc->res_pool, + dc->res_pool->oem_device, + slave_address); + + return false; +} + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd) +{ + + struct dc_link *link = dc->links[link_index]; + struct ddc_service *ddc = link->ddc; + + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); +} + +bool dc_submit_i2c_oem( + struct dc *dc, + struct i2c_command *cmd) +{ + struct ddc_service *ddc = dc->res_pool->oem_device; + + if (ddc) + return dce_i2c_submit_command( + dc->res_pool, + ddc->ddc_pin, + cmd); + + return false; +} + diff --cc drivers/gpu/drm/amd/display/dc/dc.h index 9307442dc225,30f0ba05a6e6..49ac369cc926 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@@ -1663,39 -1664,36 +1664,83 @@@ bool dc_is_oem_i2c_device_present /* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); - #endif + + /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ + bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); + /* handle DP specs define test automation sequence*/ + void dc_link_dp_handle_automated_test(struct dc_link *link); + + /* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ + void dc_link_dp_handle_link_loss(struct dc_link *link); + + /* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ + bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + ++/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. ++ * @link - link the hpd irq data associated with ++ * @hpd_irq_dpcd_data - input hpd irq data ++ * return - true if hpd irq data indicates a link lost ++ */ ++bool dc_link_check_link_loss_status(struct dc_link *link, ++ union hpd_irq_data *hpd_irq_dpcd_data); ++ ++/* Read hpd rx irq data from a given link ++ * @link - link where the hpd irq data should be read from ++ * @irq_data - output hpd irq data ++ * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data ++ * read has failed. ++ */ ++enum dc_status dc_link_dp_read_hpd_rx_irq_data( ++ struct dc_link *link, ++ union hpd_irq_data *irq_data); + +/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). + * + * TODO - When defer_handling is true the function will have a different purpose. + * It no longer does complete hpd rx irq handling. We should create a separate + * interface specifically for this case. + * + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. + */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, + bool defer_handling, bool *has_left_work); +/* handle DP specs define test automation sequence*/ +void dc_link_dp_handle_automated_test(struct dc_link *link); + +/* handle DP Link loss sequence and try to recover RX link loss with best + * effort + */ +void dc_link_dp_handle_link_loss(struct dc_link *link); + +/* Determine if hpd rx irq should be handled or ignored + * return true - hpd rx irq should be handled. + * return false - it is safe to ignore hpd rx irq event + */ +bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); + /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c index 91b59d858108,eeca16faf31a..35333daf4cd9 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c @@@ -297,12 -309,33 +307,32 @@@ void dcn32_determine_det_override(struc struct dc_plane_state *current_plane = NULL; uint8_t stream_count = 0; + int phy_pix_clk_mult, lower_mode_stream_index; + int phy_pix_clk[MAX_PIPES] = {0}; + bool use_new_det_override_algorithm = false; + for (i = 0; i < context->stream_count; i++) { /* Don't count SubVP streams for DET allocation */ - if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) + if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) { + phy_pix_clk[i] = context->streams[i]->phy_pix_clk; stream_count++; + } } + /* Check for special case with two displays, one with much higher pixel rate */ + if (stream_count == 2) { + ASSERT((phy_pix_clk[0] > 0) && (phy_pix_clk[1] > 0)); + if (phy_pix_clk[0] < phy_pix_clk[1]) { + lower_mode_stream_index = 0; + phy_pix_clk_mult = phy_pix_clk[1] / phy_pix_clk[0]; + } else { + lower_mode_stream_index = 1; + phy_pix_clk_mult = phy_pix_clk[0] / phy_pix_clk[1]; + } + + if (phy_pix_clk_mult >= DCN3_2_NEW_DET_OVERRIDE_MIN_MULTIPLIER) + use_new_det_override_algorithm = true; + } + if (stream_count > 0) { stream_segments = 18 / stream_count; for (i = 0; i < context->stream_count; i++) { diff --cc drivers/gpu/drm/amd/display/dc/link/link_detection.c index 8145d208512d,d471d58aba92..ee16d94b2b63 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@@ -1334,7 -1331,7 +1331,6 @@@ const struct dc_link_status *link_get_s return &link->link_status; } -- static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) { if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { diff --cc drivers/gpu/drm/bridge/tc358767.c index 232e23a1bfcc,91f7cb56a654..d6349af4f1b6 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@@ -1896,12 -1896,12 +1896,12 @@@ static int tc_mipi_dsi_host_attach(stru "failed to create dsi device\n"); tc->dsi = dsi; - dsi->lanes = dsi_lanes; dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - ret = mipi_dsi_attach(dsi); + ret = devm_mipi_dsi_attach(dev, dsi); if (ret < 0) { dev_err(dev, "failed to attach dsi to host: %d\n", ret); return ret; diff --cc drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8035e50f7422,3aeede6aee4d..ae367d473200 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@@ -2467,7 -2462,7 +2462,7 @@@ gen8_dispatch_bsd_engine(struct drm_i91 /* Check whether the file_priv has already selected one ring. */ if ((int)file_priv->bsd_engine < 0) file_priv->bsd_engine = - prandom_u32_max(num_vcs_engines(dev_priv)); - get_random_u32_below(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); ++ prandom_u32_max(dev_priv->engine_uabi_class_count[I915_ENGINE_CLASS_VIDEO]); return file_priv->bsd_engine; } Commit list: commit cbf143b282c64e59559cc8351c0b5b1ab4bbdcbe commit d33a54e3991dfce88b4fc6d9c3360951c2c5660d commit d703a0f45a70e6ed4749780ed5efb2d1ec042297 commit e566507bf2f460967f53030ef84b67ef26dcaf8e commit 851a4a77a9f6441bd73625fe6dbc29c814ae681f commit 18d2f6d956d0a39d5a27b0512aee17cb253f5788 commit 413ebc4803f025c64ec80de07c50e65e2f59ae89 commit 19ff997ffc43cb203fb7d6ac169b69e26c7dcbfb commit 249a4f5e663ccd1c1b1d11db68020e488a020791 commit 357513233d6456c9f99e34794897efd4ae907e83 commit 6d8d5c6b643062a0dfc7632f7a73057e75fca057 commit 680d0c7960f12fc3852c70b2bab278cc5e70b88a commit 7b775d36589390eaf19ceada78141c60ed1c7c84 commit f3783aa6b871ffece27388076d2c200a22bdb162 commit c886118bd8f574a635dda176b2460c03c28b1177 commit 0d6e08c72474043d7e686c32f25b735bfcdc9daa commit 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commit a92b7d26c743b9dc06d520f863d624e94978a1d9 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-01 05:07:01 +00:00
cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; \
Merge DRM changes from upstream v6.4..v6.5 NOTE: This commit does not compile due to missing RHEL-specific fix-ups, which are split out into separate Git commits following this one. If git bisect selected this commit, run "git bisect skip" and try again. Repeat this until it selects a commit which compiles. This commit was generated using: rhdrm-merge-drm v6.5 RHEL-1350 JIRA: https://issues.redhat.com/browse/RHEL-1350 Conflicts: drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c drivers/gpu/drm/bridge/tc358768.c drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c drivers/gpu/drm/i915/gt/uc/intel_uc.c drivers/gpu/drm/vkms/vkms_composer.c drivers/gpu/drm/vkms/vkms_formats.c Conflict resolution: diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e1d699992cef,ec1ec08d4058..a4086ef92924 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@@ -2378,8 -2471,7 +2471,11 @@@ int amdgpu_vm_ioctl(struct drm_device * union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; - int r; + ++ /* No valid flags defined yet */ ++ if (args->in.flags) ++ return -EINVAL; + /* No valid flags defined yet */ if (args->in.flags) return -EINVAL; diff --cc drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index fe2752ec67f7,709ac885ca6d..e2829454b7c7 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@@ -985,11 -991,11 +989,11 @@@ static const struct dev_pagemap_ops svm /* Each VRAM page uses sizeof(struct page) on system memory */ #define SVM_HMM_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) - int svm_migrate_init(struct amdgpu_device *adev) + int kgd2kfd_init_zone_device(struct amdgpu_device *adev) { - struct kfd_dev *kfddev = adev->kfd.dev; + struct amdgpu_kfd_dev *kfddev = &adev->kfd; struct dev_pagemap *pgmap; - struct resource *res = NULL; + struct resource *res; unsigned long size; void *r; diff --cc drivers/gpu/drm/i915/display/intel_crtc.c index 72d90edd9518,182c6dd64f47..e7083689cf4d --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@@ -696,10 -703,10 +707,11 @@@ void intel_pipe_update_end(struct intel * FIXME Should be synchronized with the start of vblank somehow... */ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)) - intel_crtc_update_active_timings(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state, + new_crtc_state->vrr.enable); - local_irq_enable(); + if (!IS_ENABLED(CONFIG_PREEMPT_RT)) + local_irq_enable(); if (intel_vgpu_active(dev_priv)) return; diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 5f75df549e75,9477c2422321..d26e24193a37 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1364,19 -1364,14 +1364,18 @@@ gen12_emit_indirect_ctx_rcs(const struc IS_DG2_G11(ce->engine->i915)) cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); - /* hsdes: 1809175790 */ - if (!HAS_FLAT_CCS(ce->engine->i915)) - cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(ce->engine, cs); /* Wa_16014892111 */ - if (IS_DG2(ce->engine->i915)) + if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || + IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) || + IS_DG2(ce->engine->i915)) cs = dg2_emit_draw_watermark_setting(cs); + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) + cs = dg2_emit_draw_watermark_setting(cs); + return cs; } diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c index 967eee5dc31b,fa70defcb5b2..9cc33c117883 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@@ -293,25 -296,24 +296,35 @@@ void intel_huc_init_early(struct intel_ } if (GRAPHICS_VER(i915) >= 11) { - huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO; - huc->status.mask = HUC_LOAD_SUCCESSFUL; - huc->status.value = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL; + } else { + huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2; + huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED; + } + + if (IS_DG2(i915)) { + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO; + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL; } else { - huc->status.reg = HUC_STATUS2; - huc->status.mask = HUC_FW_VERIFIED; - huc->status.value = HUC_FW_VERIFIED; + huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS5(MTL_GSC_HECI1_BASE); + huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI_FWSTS5_HUC_AUTH_DONE; + huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI_FWSTS5_HUC_AUTH_DONE; } + + /* + * Initialize fence to be complete as this is expected to be complete + * unless there is a delayed HuC reload in progress. + */ + i915_sw_fence_init(&huc->delayed_load.fence, + sw_fence_dummy_notify); + i915_sw_fence_commit(&huc->delayed_load.fence); + + hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + huc->delayed_load.timer.function = huc_delayed_load_timer_callback; } #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") diff --cc drivers/gpu/drm/vkms/vkms_formats.c index b11342026485,5945da0beba6..02bad87a75c2 --- a/drivers/gpu/drm/vkms/vkms_formats.c +++ b/drivers/gpu/drm/vkms/vkms_formats.c @@@ -109,8 -118,15 +118,16 @@@ void vkms_compose_row(struct line_buffe u8 *src_pixels = get_packed_src_addr(frame_info, y); int limit = min_t(size_t, drm_rect_width(&frame_info->dst), stage_buffer->n_pixels); - for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) - plane->pixel_read(src_pixels, &out_pixels[x]); + for (size_t x = 0; x < limit; x++, src_pixels += frame_info->cpp) { + int x_pos = get_x_position(frame_info, limit, x); + + if (drm_rotation_90_or_270(frame_info->rotation)) + src_pixels = get_packed_src_addr(frame_info, x + frame_info->rotated.y1) + + frame_info->cpp * y; + + plane->pixel_read(src_pixels, &out_pixels[x_pos]); + } } /* Commit list: commit ddb24fc525ddaf35130d96478f3f18682a9d5926 commit ddb78a51fac65e8db2316ded59e27ab621aea856 commit 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commit 2872144aec04baa7e43ecd2a60f7f0be3aa843fd commit e0d25c591ac676ece0e1ad6bbd72a159b9355598 commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e commit 14abdfae508228a7307f7491b5c4215ae70c6542 commit f9e96bf1905479f18e83a3a4c314a8dfa56ede2c commit a94e7ccfc400c024976f3c2f31689ed843498b7c commit 1dcc437427bbcebc8381226352f7ade08a271191 commit ce22e89eb0f541b9998f67bd51d311275a3ee51a commit 59fe2029b9e05cd490eaf972053dd86f96f77869 Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-09-04 08:27:27 +00:00
$(srctree)/scripts/kernel-doc -none -Werror $<; touch $@
drm/i915: reimplement header test feature I implemented a small build rule in drivers/gpu/drm/i915/Makefile without relying on the special header-test-y syntax that was removed in commit fcbb8461fd23 ("kbuild: remove header compile test"). I excluded some headers from the test coverage. I hope somebody intrested can take a closer look at them. Dummy subdir Makefiles can be removed altogether as single target build use case is now covered by commit 394053f4a4b3 ("kbuild: make single targets work more correctly"). v2 by Jani: - add selftests/i915_perf_selftests.h to no-header-test - add .gitignore for *.hdrtest Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191219155652.2666-3-jani.nikula@intel.com
2019-12-19 15:56:52 +00:00
$(obj)/%.hdrtest: $(src)/%.h FORCE
$(call if_changed_dep,hdrtest)