License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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# SPDX-License-Identifier: GPL-2.0
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2008-05-29 00:09:59 +00:00
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#
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# Makefile for the drm device driver. This driver provides support for the
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# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
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2017-10-24 18:15:47 +00:00
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# Add a set of useful warning flags and enable -Werror for CI to prevent
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# trivial mistakes from creeping in. We have to do this piecemeal as we reject
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# any patch that isn't warning clean, so turning on -Wall -Wextra (or W=1) we
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# need to filter out dubious warnings. Still it is our interest
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# to keep running locally with W=1 C=1 until we are completely clean.
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#
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# Note the danger in using -Wall -Wextra is that when CI updates gcc we
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# will most likely get a sudden build breakage... Hopefully we will fix
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# new warnings before CI updates!
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2018-06-25 22:59:34 +00:00
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subdir-ccflags-y := -Wall -Wextra
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2022-05-23 17:17:03 +00:00
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subdir-ccflags-y += -Wno-format-security
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
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commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464
commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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subdir-ccflags-y += -Wno-unused-parameter
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subdir-ccflags-y += -Wno-type-limits
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subdir-ccflags-y += -Wno-missing-field-initializers
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subdir-ccflags-y += -Wno-sign-compare
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2022-05-23 17:17:03 +00:00
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subdir-ccflags-y += -Wno-shift-negative-value
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2018-02-08 16:16:39 +00:00
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subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable)
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2020-04-26 21:42:15 +00:00
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subdir-ccflags-y += $(call cc-disable-warning, frame-address)
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2017-10-24 18:15:47 +00:00
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subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror
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# Fine grained warnings disable
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2017-10-30 17:29:27 +00:00
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CFLAGS_i915_pci.o = $(call cc-disable-warning, override-init)
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kbuild: change *FLAGS_<basetarget>.o to take the path relative to $(obj)
Kbuild provides per-file compiler flag addition/removal:
CFLAGS_<basetarget>.o
CFLAGS_REMOVE_<basetarget>.o
AFLAGS_<basetarget>.o
AFLAGS_REMOVE_<basetarget>.o
CPPFLAGS_<basetarget>.lds
HOSTCFLAGS_<basetarget>.o
HOSTCXXFLAGS_<basetarget>.o
The <basetarget> is the filename of the target with its directory and
suffix stripped.
This syntax comes into a trouble when two files with the same basename
appear in one Makefile, for example:
obj-y += foo.o
obj-y += dir/foo.o
CFLAGS_foo.o := <some-flags>
Here, the <some-flags> applies to both foo.o and dir/foo.o
The real world problem is:
scripts/kconfig/util.c
scripts/kconfig/lxdialog/util.c
Both files are compiled into scripts/kconfig/mconf, but only the
latter should be given with the ncurses flags.
It is more sensible to use the relative path to the Makefile, like this:
obj-y += foo.o
CFLAGS_foo.o := <some-flags>
obj-y += dir/foo.o
CFLAGS_dir/foo.o := <other-flags>
At first, I attempted to replace $(basetarget) with $*. The $* variable
is replaced with the stem ('%') part in a pattern rule. This works with
most of cases, but does not for explicit rules.
For example, arch/ia64/lib/Makefile reuses rule_as_o_S in its own
explicit rules, so $* will be empty, resulting in ignoring the per-file
AFLAGS.
I introduced a new variable, target-stem, which can be used also from
explicit rules.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2019-08-30 04:34:01 +00:00
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CFLAGS_display/intel_fbdev.o = $(call cc-disable-warning, override-init)
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2017-10-24 18:15:47 +00:00
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2019-06-26 14:36:17 +00:00
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subdir-ccflags-y += -I$(srctree)/$(src)
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2019-04-24 17:48:39 +00:00
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2014-03-07 08:17:21 +00:00
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# Please keep these build lists sorted!
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# core driver code
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2022-05-23 17:15:52 +00:00
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i915-y += i915_driver.o \
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2022-11-02 15:27:09 +00:00
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i915_drm_client.o \
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2020-05-09 10:50:21 +00:00
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i915_config.o \
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2019-08-07 14:20:41 +00:00
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i915_getparam.o \
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2022-05-23 17:17:03 +00:00
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i915_ioctl.o \
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i915_irq.o \
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2021-01-11 22:52:20 +00:00
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i915_mitigations.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
commit 17917ff62443414569ea76e151e7a7ef44812264
commit 837f93247634b12e5eebb3d707405b701a4f3479
commit 867cf9cd73c3d31666e4b480aa4f52828d25ac94
commit 6eca310e8924ab98c73b81dfd39e7dd553ceddfd
commit 16c243e99d335e1ef3059871897119affc98b493
commit d098775ed44021293b1962dea61efb19297b8d02
commit 86441fa29e57940eeb00f35fefb1853c1fbe67bb
commit a3af0140663dc335e5c18277a61bb99bfcb60694
commit 26594678d00f94c62f2e43162bd6d10fd0b74917
commit a3a5f9d0fb15da90820254ba735491887cc12099
commit 213d5092776345ad5d6e2efa36a6bfbe9899e8b3
commit 2e53d7c1147a2751e959c53970c61b7ae33e1ecb
commit f425821b946847282708121600fffc20344183a0
commit cf3e3e86d77970211e0983130e896ae242601003
commit 0ea02bb8bc7a16446169bfae46938ea3a195db5d
commit aeb33699fc2c97994de0e9acb74d0fd319380614
commit 74c06c282ae63560fcf4073d1564f054d96285ec
commit cc5a3fc041f0104d97ac61b0423ec533d7a93214
commit a1e3667a9835e15101cf27731219fe2581dbf572
commit e0bbcc6233f7c664474287aaed8dcffd935a1869
commit a70e558c151043ce46a5e5999f4310e0b3551f57
commit 4c1b3d94bf632c1420a5d4108199f55a5655831d
commit d92223ead97cd697abe76c5b7a78160d6910a90d
commit 7a7a933edd6c3a6d5d64e08093f2d564104cefcd
commit a12be0277316ed923411c9c80b2899ee74d2b033
commit 74231041d14030f1ae6582b9233bfe782ac23e33
commit f674a218c610bea97c106ca8179b55b2a7a7528a
commit 8d9a8d9bd5034a88afef470664918aa914b1c3dc
commit b7d0949f6ce691131323fafabd48bf2f5074ae8d
commit baee602e5c0d00a7233fdb2b2bfd3ace4b5b8f29
commit 352a81b71ea0a3ce8f929aa60afe369d738a0c6a
commit 00f4471e42c871524c68ef1413d2fe53ce1d0a1b
commit bfd616ff9a2602ec66414438c3f9871a49fa1e16
commit ade0e676ecdcdd3428210684c76493722e09a791
commit c649432e86ca677d8762c5764a2832509ca8d449
commit 0e9d217b79371d726e53d4a1beef1743952383b7
commit 35c6367f516090a3086d37e7023b08608d555aba
commit b4b9731b02c3ce859d85dec17ec63f4bf3140bf4
commit 9c61e789546810ee63708568737cb990d2b86605
commit 440d0f12b52a920f4c78376b3ce7039ba59244c5
commit 413f52f146f148827dd7a61ca599143f60ae3e3c
commit c2a61865baa45b5d1dfc3e83da50bcd51d518786
commit b91e3c830f00814c0f5c2e3afaf63b48d8ccb9d3
commit aae74ff9caa8de9a45ae2e46068c417817392a26
commit bdb8d06dfefd666d5981d884b535b04105869fcc
commit 8c209f42cb3a209c366bae2956c98d8ed0514773
commit ad5fd900a69b1ae24e6b22506dea637b6bbbdb55
commit 544021e3f2aa3c4c6c5aabc58907e8bab69b3762
commit c865204e84a1a5c35e055b45971524efe4616e31
commit 88be9a0a06b73ecd85a688a7c174c941e9692e92
commit f701b16d4cc535d24facdfdd21dc97a3691e5576
commit 38f28c0695c0413b701f67105bff2573c667492a
commit beb6a22911ff6f7e933670b43e4bda5be56bd8f9
commit 687c7d0fcf8014a006416d7dc7474a101a85bf00
commit d53ec322dc7de32a59bf1c2a56b93e90fc2f1c28
commit 13c2ceb6addb6b14468e09b75832c98909eed8e7
commit 151ec347b06a2fb6ecd2922475dca71a7af827a5
commit ebc9ac7c3dfe85e7e29af896c7fd1095129fd72c
commit c2aaa37dc18fb7191a0fd829a7a943f61c2821de
commit 46e4e5ffbc2af8a6f7935648ab286902b406a01d
commit 9f808288ba88ac2a9582118343d4ca7e3d95dd43
commit dc2408d86e5ae88ec981e1315f95b7d4d15169fe
commit a6c5b891252143ee9bc02f649282905954d6705c
commit 1c4dbe056dab0b7c2a2f42f4d393cc7b9bdb98ad
commit 5c43ec5d538a5fa1736d298e63a3f8ac03009eea
commit 3b86eb82dc2c9989ca6e53cb597a2a1390c64d12
commit 0dcd6fdf3b4be20995d8d35198ac252833613ab9
commit 3607e1e9ba7553e39b175fa14d10a48677083607
commit b4ef95309110122e05b0d17310b80a0abde881d9
commit cf586021642d8017cde111b7dd1ba86224e9da51
commit 563baae1875cbcac332086cca325cf55a0532b9e
commit 94ce0d65076cda511da843ae1893c819948a215a
commit 50331a7b50741035cc9335f863939d638b225e71
commit 57143f2e5b41f3e51b13d3c358e29a932334110d
commit 99919be74aa37537850a7b453f2a3e3260e0d50e
commit 5cd57f676bb946a00275408f0dd0d75dbc466d25
commit 6796c772850574ec0a9adc977e9889606b23d0f4
commit 932641f0323eec3fc42dfd303eb033f5dfa08e74
commit 0957e931df647511ecaf43883a7031004036f90d
commit 3193927421554757e6bee52f9c7e3937edefc589
commit f03ab6629c7b410d874151cf1d8570899a65fdda
commit b07a6483839a838dc7acff570174053dd544c039
commit 59bd8ae7d33c83c4a81835d4e922bdae17fd8522
commit e87138e05c803a78460a6b59fa75a05f92aa80fb
commit 3e28d37146db5dd49c469bc62a93ca791067d391
commit 074bb195bce1c86b66e5cd809d6663039d3abf42
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commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
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commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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i915_module.o \
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2014-03-07 08:17:21 +00:00
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i915_params.o \
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2016-06-24 13:00:26 +00:00
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i915_pci.o \
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2019-05-28 09:29:50 +00:00
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i915_scatterlist.o \
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2018-12-05 11:06:08 +00:00
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i915_suspend.o \
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2019-10-04 12:20:18 +00:00
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i915_switcheroo.o \
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2014-03-07 08:17:21 +00:00
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i915_sysfs.o \
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2019-08-08 13:42:43 +00:00
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i915_utils.o \
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2016-07-05 09:40:20 +00:00
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intel_device_info.o \
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2020-02-25 11:15:07 +00:00
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intel_dram.o \
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2019-10-08 16:01:14 +00:00
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intel_memory_region.o \
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2019-08-07 12:04:15 +00:00
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intel_pch.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
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commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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intel_pcode.o \
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2014-09-30 08:56:38 +00:00
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intel_pm.o \
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2021-06-02 08:38:08 +00:00
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intel_region_ttm.o \
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2018-04-10 16:12:46 +00:00
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intel_runtime_pm.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
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commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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intel_sbi.o \
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2021-03-26 13:21:32 +00:00
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intel_step.o \
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2019-06-13 08:44:16 +00:00
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intel_uncore.o \
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2020-02-12 14:40:57 +00:00
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intel_wakeref.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
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commit 271fd38ce56d6f143ddbd7bb999ad337d151b561
commit 244ee398855df2adc7d3ac5702b58424a5f684cc
commit 53af98c091bc42fd9ec64cfabc40da4e5f3aae93
commit 4d62555f624582e60be416fbc4772cd3fcd12b1a
commit cda0817b41bdd509c37036c482a60230a5063772
commit 0cc53cb450669cf1def4ff89e8cbcd8ec3c62380
commit 6946be2443cfd4755eb8e465c20e7cf33fb259b3
commit 8888e2fe9c77983a9644cd9bf0d23ca9023b16d4
commit c4ef8a73bfc84fad3de46b38f313c0b159103b28
commit fd08953b2de911f32c06aedbc8ad111c2fd0168b
commit 57961c4c1818a8a2cc5cd964a430581f77f7eb6a
commit d5c7255dc7ff6e1239d794b9c53029d83ced04ca
commit 692cd92e66ee10597676530573a495dc1d3bec6a
commit 7798a7369272b523646d6810ffe71012cf9f420a
commit fc026c8b926835b46509a2757732bfa38a2162f1
commit 6b54698aec0b59943f7e8a88151bdf208de990d0
commit 7e78781df491e4beb475bac22e6c44236a5002d7
commit 42abd0043e0c64fa64e99adba534c76b9b15e6b8
commit 61e29a0956bdb09eac8aca7d9add9f902baff08b
commit 679d94cd7d900871e5bc9cf780bd5b73af35ab42
commit a44f42ba7f1ad7d3c17bc7d91013fe814a53c5dc
commit da3b36a23bb72e9742bf2f1b3e5da9615480c789
commit 3e467e478ed3a9701bb588d648d6e0ccb82ced09
commit 1053b9c948e614473819a1a5bcaff6d44e680dcf
commit 7551f70ab93d0f3371b28e996f7583e3be1d9a72
commit e0570f0b6e2e88be7ef99d1194b153cb054a2107
commit 94ebc035456a4ccacfbbef60c444079a256623ad
commit ef548afe05f8d8c5af0fc44b035d5283156f8b03
commit 5ceaebcda9061c04f439c93961f0819878365c0f
commit c9beecc5c9626ab772160ab3f8e209abc09fa54d
commit fc2c456ea8329053685db179d30e3ff0c91e5066
commit 494f2e42ce4a9ddffb5d8c5b2db816425ef90397
commit 2da34b7bb59e1caa9a336e0e20a76b8b6a4abea2
commit 428890a3fec131521cc59aac0d3c48bde9d76b7b
commit 3abfe30d803e62cc75dec254eefab3b04d69219b
commit 72641d8d60401a5f1e1a0431ceaf928680d34418
commit 1152b16842c903dd7e2896088d5ff73f26443653
commit a687efed194bdc185fd7cb33920fe8b4e60ecb9e
commit e485382ea7eb4b81f4b59073cd831084820497de
commit 8581fd402a0cf80b5298e3b225e7a7bd8f110e69
commit b19926d4f3a660a8b76e5d989ffd1168e619a5c4
commit 9cdb54be3e463f5c0607fcac045d5a9c67575775
commit 6efcdadc157fcb2e9dfbcc797ed036df7498b35a
commit af6902ec415655236adea91826bd96ed0ab16f42
commit 0755c38eb007196a5f779298b4a5f46c4eec41d2
commit 842470c4e211f284a224842849b1fa81b130c154
commit 52255ef662a5d490678fbad64a735f88fcba564d
commit ded746bfc94398d2ee9de315a187677b207b2004
commit 2eb557d293f7455be699ffaaa4769ba4991aa2a3
commit 233bee7e365a3381e22bf17455b39298d8d9b095
commit 675a095789a2663fe02fdebd6023e29d7f1f51ac
commit 9b302ffe4e8d7e62f3170aa0097ff979880ba61d
commit 5cf06065bd1f7b94fbb80e7eeb033899f77ab5ba
commit fea3fdf975dd9f3e5248afaab8fe023db313f005
commit 53b3495273282aa844c4613d19c3b30558c70c84
commit f3a8076eb28cae1553958c629aecec479394bbe2
commit 841933d5b8aa853abe68e63827f68f50fab37226
commit dcd10d879a9d1d4e929d374c2f24aba8fac3252b
commit 7e4d2f30df3fb48f75ce9e96867d42bdddab83ac
commit 791255ca9fbe38042cfd55df5deb116dc11fef18
commit 17c65d6fca844ee72a651944d8ce721e9040bf70
commit aa464957f7e660abd554f2546a588f6533720e21
commit 78fed39af1af5d702089fe53076c524646e64997
commit a2fbfd517117157e99160ff1b39b171872dcba07
commit fc74881c28d314b10efac016ef49df4ff40b8b97
commit bf67014d6bda16a72deea11dbbff2a97c705ca92
commit 19e66d512e4182a0461530fa3159638e0f55d97e
commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6
commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20
commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5
commit 7807bf28fe02a76bf112916c6b9194f282f5e43c
commit 67f74302f45d5d862f22ced3297624e50ac352f0
commit 4d625a97a7e96be016382e3bb0a3cead05fec153
commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c
commit d46f329a3f6048e04736e86cb13c880645048792
commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1
commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee
commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464
commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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vlv_sideband.o \
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2020-02-12 14:40:57 +00:00
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vlv_suspend.o
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2019-04-24 17:48:39 +00:00
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# core library code
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i915-y += \
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i915_memcpy.o \
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i915_mm.o \
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i915_sw_fence.o \
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2019-08-21 19:16:06 +00:00
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i915_sw_fence_work.o \
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2019-04-24 17:48:39 +00:00
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i915_syncmap.o \
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i915_user_extensions.o
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2014-09-30 08:56:38 +00:00
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2014-03-07 08:17:21 +00:00
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i915-$(CONFIG_COMPAT) += i915_ioc32.o
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2019-12-05 15:43:40 +00:00
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i915-$(CONFIG_DEBUG_FS) += \
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i915_debugfs.o \
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i915_debugfs_params.o \
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2020-02-11 16:14:51 +00:00
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display/intel_display_debugfs.o \
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2019-12-05 15:43:40 +00:00
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display/intel_pipe_crc.o
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drm/i915/pmu: Expose a PMU interface for perf queries
From: Chris Wilson <chris@chris-wilson.co.uk>
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
From: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
The first goal is to be able to measure GPU (and invidual ring) busyness
without having to poll registers from userspace. (Which not only incurs
holding the forcewake lock indefinitely, perturbing the system, but also
runs the risk of hanging the machine.) As an alternative we can use the
perf event counter interface to sample the ring registers periodically
and send those results to userspace.
Functionality we are exporting to userspace is via the existing perf PMU
API and can be exercised via the existing tools. For example:
perf stat -a -e i915/rcs0-busy/ -I 1000
Will print the render engine busynnes once per second. All the performance
counters can be enumerated (perf list) and have their unit of measure
correctly reported in sysfs.
v1-v2 (Chris Wilson):
v2: Use a common timer for the ring sampling.
v3: (Tvrtko Ursulin)
* Decouple uAPI from i915 engine ids.
* Complete uAPI defines.
* Refactor some code to helpers for clarity.
* Skip sampling disabled engines.
* Expose counters in sysfs.
* Pass in fake regs to avoid null ptr deref in perf core.
* Convert to class/instance uAPI.
* Use shared driver code for rc6 residency, power and frequency.
v4: (Dmitry Rogozhkin)
* Register PMU with .task_ctx_nr=perf_invalid_context
* Expose cpumask for the PMU with the single CPU in the mask
* Properly support pmu->stop(): it should call pmu->read()
* Properly support pmu->del(): it should call stop(event, PERF_EF_UPDATE)
* Introduce refcounting of event subscriptions.
* Make pmu.busy_stats a refcounter to avoid busy stats going away
with some deleted event.
* Expose cpumask for i915 PMU to avoid multiple events creation of
the same type followed by counter aggregation by perf-stat.
* Track CPUs getting online/offline to migrate perf context. If (likely)
cpumask will initially set CPU0, CONFIG_BOOTPARAM_HOTPLUG_CPU0 will be
needed to see effect of CPU status tracking.
* End result is that only global events are supported and perf stat
works correctly.
* Deny perf driver level sampling - it is prohibited for uncore PMU.
v5: (Tvrtko Ursulin)
* Don't hardcode number of engine samplers.
* Rewrite event ref-counting for correctness and simplicity.
* Store initial counter value when starting already enabled events
to correctly report values to all listeners.
* Fix RC6 residency readout.
* Comments, GPL header.
v6:
* Add missing entry to v4 changelog.
* Fix accounting in CPU hotplug case by copying the approach from
arch/x86/events/intel/cstate.c. (Dmitry Rogozhkin)
v7:
* Log failure message only on failure.
* Remove CPU hotplug notification state on unregister.
v8:
* Fix error unwind on failed registration.
* Checkpatch cleanup.
v9:
* Drop the energy metric, it is available via intel_rapl_perf.
(Ville Syrjälä)
* Use HAS_RC6(p). (Chris Wilson)
* Handle unsupported non-engine events. (Dmitry Rogozhkin)
* Rebase for intel_rc6_residency_ns needing caller managed
runtime pm.
* Drop HAS_RC6 checks from the read callback since creating those
events will be rejected at init time already.
* Add counter units to sysfs so perf stat output is nicer.
* Cleanup the attribute tables for brevity and readability.
v10:
* Fixed queued accounting.
v11:
* Move intel_engine_lookup_user to intel_engine_cs.c
* Commit update. (Joonas Lahtinen)
v12:
* More accurate sampling. (Chris Wilson)
* Store and report frequency in MHz for better usability from
perf stat.
* Removed metrics: queued, interrupts, rc6 counters.
* Sample engine busyness based on seqno difference only
for less MMIO (and forcewake) on all platforms. (Chris Wilson)
v13:
* Comment spelling, use mul_u32_u32 to work around potential GCC
issue and somne code alignment changes. (Chris Wilson)
v14:
* Rebase.
v15:
* Rebase for RPS refactoring.
v16:
* Use the dynamic slot in the CPU hotplug state machine so that we are
free to setup our state as multi-instance. Previously we were re-using
the CPUHP_AP_PERF_X86_UNCORE_ONLINE slot which is neither used as
multi-instance, nor owned by our driver to start with.
* Register the CPU hotplug handlers after the PMU, otherwise the callback
will get called before the PMU is initialized which can end up in
perf_pmu_migrate_context with an un-initialized base.
* Added workaround for a probable bug in cpuhp core.
v17:
* Remove workaround for the cpuhp bug.
v18:
* Rebase for drm_i915_gem_engine_class getting upstream before us.
v19:
* Rebase. (trivial)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-2-tvrtko.ursulin@linux.intel.com
2017-11-21 18:18:45 +00:00
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i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o
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2014-03-07 08:17:21 +00:00
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2019-04-24 17:48:39 +00:00
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# "Graphics Technology" (aka we talk to the gpu)
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gt-y += \
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2020-06-01 07:24:12 +00:00
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gt/gen2_engine_cs.o \
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gt/gen6_engine_cs.o \
|
2020-01-07 13:40:09 +00:00
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gt/gen6_ppgtt.o \
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2020-03-06 00:09:57 +00:00
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gt/gen7_renderclear.o \
|
2020-12-09 23:36:18 +00:00
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gt/gen8_engine_cs.o \
|
2020-01-07 13:40:09 +00:00
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gt/gen8_ppgtt.o \
|
2019-04-24 17:48:39 +00:00
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gt/intel_breadcrumbs.o \
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gt/intel_context.o \
|
2020-01-31 10:45:42 +00:00
|
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gt/intel_context_sseu.o \
|
2019-04-24 17:48:39 +00:00
|
|
|
gt/intel_engine_cs.o \
|
2019-10-21 17:43:39 +00:00
|
|
|
gt/intel_engine_heartbeat.o \
|
drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-24 20:07:17 +00:00
|
|
|
gt/intel_engine_pm.o \
|
2019-08-06 12:43:00 +00:00
|
|
|
gt/intel_engine_user.o \
|
2020-12-09 23:36:17 +00:00
|
|
|
gt/intel_execlists_submission.o \
|
2020-01-07 13:40:09 +00:00
|
|
|
gt/intel_ggtt.o \
|
2020-03-16 11:38:43 +00:00
|
|
|
gt/intel_ggtt_fencing.o \
|
2019-06-21 07:07:41 +00:00
|
|
|
gt/intel_gt.o \
|
2020-04-30 11:18:12 +00:00
|
|
|
gt/intel_gt_buffer_pool.o \
|
2020-04-24 16:28:05 +00:00
|
|
|
gt/intel_gt_clock_utils.o \
|
Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
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commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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gt/intel_gt_debugfs.o \
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gt/intel_gt_engines_debugfs.o \
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2019-08-11 21:06:33 +00:00
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gt/intel_gt_irq.o \
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2022-11-02 15:48:10 +00:00
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gt/intel_gt_mcr.o \
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drm/i915: Invert the GEM wakeref hierarchy
In the current scheme, on submitting a request we take a single global
GEM wakeref, which trickles down to wake up all GT power domains. This
is undesirable as we would like to be able to localise our power
management to the available power domains and to remove the global GEM
operations from the heart of the driver. (The intent there is to push
global GEM decisions to the boundary as used by the GEM user interface.)
Now during request construction, each request is responsible via its
logical context to acquire a wakeref on each power domain it intends to
utilize. Currently, each request takes a wakeref on the engine(s) and
the engines themselves take a chipset wakeref. This gives us a
transition on each engine which we can extend if we want to insert more
powermangement control (such as soft rc6). The global GEM operations
that currently require a struct_mutex are reduced to listening to pm
events from the chipset GT wakeref. As we reduce the struct_mutex
requirement, these listeners should evaporate.
Perhaps the biggest immediate change is that this removes the
struct_mutex requirement around GT power management, allowing us greater
flexibility in request construction. Another important knock-on effect,
is that by tracking engine usage, we can insert a switch back to the
kernel context on that engine immediately, avoiding any extra delay or
inserting global synchronisation barriers. This makes tracking when an
engine and its associated contexts are idle much easier -- important for
when we forgo our assumed execution ordering and need idle barriers to
unpin used contexts. In the process, it means we remove a large chunk of
code whose only purpose was to switch back to the kernel context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
2019-04-24 20:07:17 +00:00
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gt/intel_gt_pm.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
commit 7b812171257d4b8d9ef69321134c72b647e1ce9c
commit 5918241f607616c0cd9565f575f4cd955fa435e0
commit 0707570248b8b13008d0fca7cc4f6e1848f0d64f
commit 3b4da8315addfe4661f3c25ea8a83097d965c67a
commit 2817efaeb608421d8f6fe7939826c35a852644e9
commit b2eb7d716426fe056596761cd371005d64e9caec
commit 32a4eb04d59ae8d5bb5baa5a8528e31094ae8e84
commit 992c238188a83befa0094a8c00bfead31aa302ed
commit d8959fb33890ba1956c142e83398e89812450ffc
commit f492283b157053e9555787262f058ae33096f568
commit ea5ea3d8a117517a75c2af30faa399671444a1ea
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commit 6fa701d13ae6925f267185b2469e49f384e450ec
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commit 7f16d0f3b8e2d13f940e944cd17044ca8eeb8b32
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commit c00e14cd4d3fbc5469d6e367371f9e4786a08c03
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commit 9e6dcf33eda91f49a6adac984115875773d11fba
commit 4b5777af5bb17398c7764c8f3b66f344b5a5cb6f
commit 8e6b13a7b298edec16fb05aca0200ad400c9d1ea
commit 3c6a4a02c92af14a0325ede88bdbccc0ccd19241
commit 63aef47b3eb52447716b2f2cf69eaca338e3576e
commit c9b6e94963bc3a53110f1c9cd7e5e4ae571413cd
commit 5359b745146aa596026addffd7843e1735db7bbd
commit 8c3363c67b885fe40f50a8010a0768c4fd1e4b95
commit 331de7db3012b8e8e8d77beebc8f743e288d4c42
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commit a2fbfd517117157e99160ff1b39b171872dcba07
commit fc74881c28d314b10efac016ef49df4ff40b8b97
commit bf67014d6bda16a72deea11dbbff2a97c705ca92
commit 19e66d512e4182a0461530fa3159638e0f55d97e
commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6
commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20
commit 64d16aca3d4f130f35bbf1120e15f58a62f743d5
commit 7807bf28fe02a76bf112916c6b9194f282f5e43c
commit 67f74302f45d5d862f22ced3297624e50ac352f0
commit 4d625a97a7e96be016382e3bb0a3cead05fec153
commit 0f9d36af8f211d296ffd23bdce61a72cdfbb1a3c
commit d46f329a3f6048e04736e86cb13c880645048792
commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1
commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee
commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464
commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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gt/intel_gt_pm_debugfs.o \
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2019-08-11 14:28:00 +00:00
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gt/intel_gt_pm_irq.o \
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2019-10-04 13:40:06 +00:00
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gt/intel_gt_requests.o \
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2022-11-02 15:27:09 +00:00
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gt/intel_gt_sysfs.o \
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gt/intel_gt_sysfs_pm.o \
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2020-01-07 13:40:09 +00:00
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gt/intel_gtt.o \
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2019-10-20 18:41:39 +00:00
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gt/intel_llc.o \
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gt/intel_lrc.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
commit 17917ff62443414569ea76e151e7a7ef44812264
commit 837f93247634b12e5eebb3d707405b701a4f3479
commit 867cf9cd73c3d31666e4b480aa4f52828d25ac94
commit 6eca310e8924ab98c73b81dfd39e7dd553ceddfd
commit 16c243e99d335e1ef3059871897119affc98b493
commit d098775ed44021293b1962dea61efb19297b8d02
commit 86441fa29e57940eeb00f35fefb1853c1fbe67bb
commit a3af0140663dc335e5c18277a61bb99bfcb60694
commit 26594678d00f94c62f2e43162bd6d10fd0b74917
commit a3a5f9d0fb15da90820254ba735491887cc12099
commit 213d5092776345ad5d6e2efa36a6bfbe9899e8b3
commit 2e53d7c1147a2751e959c53970c61b7ae33e1ecb
commit f425821b946847282708121600fffc20344183a0
commit cf3e3e86d77970211e0983130e896ae242601003
commit 0ea02bb8bc7a16446169bfae46938ea3a195db5d
commit aeb33699fc2c97994de0e9acb74d0fd319380614
commit 74c06c282ae63560fcf4073d1564f054d96285ec
commit cc5a3fc041f0104d97ac61b0423ec533d7a93214
commit a1e3667a9835e15101cf27731219fe2581dbf572
commit e0bbcc6233f7c664474287aaed8dcffd935a1869
commit a70e558c151043ce46a5e5999f4310e0b3551f57
commit 4c1b3d94bf632c1420a5d4108199f55a5655831d
commit d92223ead97cd697abe76c5b7a78160d6910a90d
commit 7a7a933edd6c3a6d5d64e08093f2d564104cefcd
commit a12be0277316ed923411c9c80b2899ee74d2b033
commit 74231041d14030f1ae6582b9233bfe782ac23e33
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commit 59be177a909ac320e5f4b2a461ac09e20f35b2d8
commit 5afa7898ab7a0ec9c28556a91df714bf3c2f725e
commit c21b105380cf86e829c68586ca1315cfc253ad8c
commit c938aed88f8259dc913b717a32319101c66e87a9
commit 672437486ee9da3ed0e774937e6d0dd570921b39
commit 4835ea6c173a8d8dfbfdbb21c4cd987d12681610
commit dd8cb18906d97b2916fde42d32d915ae363c7e55
commit 2ef8ea23942f4c2569930c34e7689a0cb1b232cc
commit 53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67
commit 772970620a839141835eaf2bc507d957b10adcca
commit 3e4c31e8f70251732529a10934355084c7fab0ac
commit a79f40cccd4644c32f6d5ae1ccf091a262e1dc57
commit 13047a092c6d3f23b7d684b5b3fe46b2b50423b9
commit 982f8ad666a1123028a077b6b009871a0dc9df26
commit 004d2719806fb8e355c1bccd538e82c04319d391
commit 74056092ff415e7e20ce2544689b32ee811c4f0b
commit 0db55f9a1bafbe3dac750ea669de9134922389b5
commit def0c3697287f6e85d5ac68b21302966c95474f9
commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7
commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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gt/intel_migrate.o \
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2019-10-24 10:03:44 +00:00
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gt/intel_mocs.o \
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2020-01-07 13:40:09 +00:00
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gt/intel_ppgtt.o \
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2019-09-27 11:08:49 +00:00
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gt/intel_rc6.o \
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2021-01-12 16:43:00 +00:00
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gt/intel_region_lmem.o \
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2019-07-04 09:19:25 +00:00
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gt/intel_renderstate.o \
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2019-04-24 17:48:39 +00:00
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gt/intel_reset.o \
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2019-10-24 10:03:44 +00:00
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gt/intel_ring.o \
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gt/intel_ring_submission.o \
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2019-10-24 21:16:41 +00:00
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gt/intel_rps.o \
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Merge DRM changes from upstream v6.0.8..v6.1
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.1 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/mgag200/mgag200_pll.c
Conflict resolution:
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ecb8db731081,253ea6b159df..6ebed4d58ced
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@@ -162,6 -162,7 +162,8 @@@
#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
+ #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque
*/
static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
{
- uint8_t i;
- int j;
++
+ int i, j;
struct dc_stream_state *stream = NULL;
struct dc_plane_state *plane = NULL;
uint32_t cursor_size = 0;
@@@ -237,24 -236,24 +237,27 @@@
mblk_width = DCN3_2_MBLK_WIDTH;
mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
++
/* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
* FLOOR(vp_x_start, blk_width)
*
* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c
*/
mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
- pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) +
+ pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) -
(pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
++
/* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
* FLOOR(vp_y_start, blk_height)
*
* mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c
*/
mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
- pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) +
+ pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) -
(pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
++
num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
diff --cc drivers/gpu/drm/ast/ast_mode.c
index b93181a42048,1bc0220e6783..ae5a4cce972f
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@@ -42,9 -40,8 +42,8 @@@
#include <drm/drm_fourcc.h>
#include <drm/drm_gem_atomic_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
-#include <drm/drm_gem_vram_helper.h>
+#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_managed.h>
- #include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
@@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane
static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_crtc_state *crtc_state;
- struct ast_crtc_state *ast_crtc_state;
+ struct drm_device *dev = plane->dev;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_crtc_state *new_crtc_state = NULL;
+ struct ast_crtc_state *new_ast_crtc_state;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
false, true);
- if (ret)
+ if (ret) {
return ret;
+ } else if (!new_plane_state->visible) {
+ if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */
+ return -EINVAL;
+ else
+ return 0;
+ }
- if (!new_plane_state->visible)
- return 0;
-
- ast_crtc_state = to_ast_crtc_state(crtc_state);
+ new_ast_crtc_state = to_ast_crtc_state(new_crtc_state);
- ast_crtc_state->format = new_plane_state->fb->format;
+ new_ast_crtc_state->format = new_plane_state->fb->format;
return 0;
}
@@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_
static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_framebuffer *fb = new_plane_state->fb;
- struct drm_crtc_state *crtc_state;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_framebuffer *new_fb = new_plane_state->fb;
+ struct drm_crtc_state *new_crtc_state = NULL;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
true, true);
- if (ret)
+ if (ret || !new_plane_state->visible)
return ret;
- if (!new_plane_state->visible)
- return 0;
-
- if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
+ if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT)
return -EINVAL;
return 0;
diff --cc drivers/gpu/drm/i915/display/intel_display.c
index bd629f2da6eb,de77054195c6..d3bfa2a675b8
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9
else if (DISPLAY_VER(i915) >= 11)
pipes = BIT(PIPE_B) | BIT(PIPE_C);
else
++
pipes = 0;
- return pipes & RUNTIME_INFO(i915)->pipe_mask;
+ return pipes & INTEL_INFO(i915)->display.pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj
return !strncmp(kobj->name, "gt", 2);
}
- static struct intel_gt *kobj_to_gt(struct kobject *kobj)
- {
- return container_of(kobj, struct intel_gt, sysfs_gt);
- }
-
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name)
{
- struct kobject *kobj = &dev->kobj;
-
/*
* We are interested at knowing from where the interface
* has been called, whether it's called from gt/ or from
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
index 6bee2c6a894d,6232923a420d..c3a123faee98
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g
struct kobject *dir,
const char *name);
+ static inline struct intel_gt *kobj_to_gt(struct kobject *kobj)
+ {
+ return container_of(kobj, struct intel_gt, sysfs_gt);
+ }
+
void intel_gt_sysfs_register(struct intel_gt *gt);
void intel_gt_sysfs_unregister(struct intel_gt *gt);
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name);
#endif /* SYSFS_GT_H */
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe
NULL
};
+ static ssize_t
+ default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
+ }
+
+ static struct kobj_attribute default_min_freq_mhz =
+ __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
+
+ static ssize_t
+ default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
+ }
+
+ static struct kobj_attribute default_max_freq_mhz =
+ __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
+
+ static const struct attribute * const rps_defaults_attrs[] = {
+ &default_min_freq_mhz.attr,
+ &default_max_freq_mhz.attr,
+ NULL
+ };
+
-static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
- const struct attribute * const *attrs)
+static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
{
+ const struct attribute * const *attrs;
+ struct attribute *vlv_attr;
int ret;
if (GRAPHICS_VER(gt->i915) < 6)
diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4,3955292483a6..d3ac73c3559f
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc
/* hsdes: 1809175790 */
if (!HAS_FLAT_CCS(ce->engine->i915))
- cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
+ cs = gen12_emit_aux_table_inv(ce->engine->gt,
+ cs, GEN12_GFX_CCS_AUX_NV);
+
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+
return cs;
}
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b6479b5bd32,a821e3d405db..21cd1a4e1823
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ }
- /* Wa_16011620976:dg2_g11 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 844dee09a321,1db59eeb34db..1ac0e66d39e5
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i
return 0;
}
+struct scheduling_policy {
+ /* internal data */
+ u32 max_words, num_words;
+ u32 count;
+ /* API data */
+ struct guc_update_scheduling_policy h2g;
+};
+
+static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy)
+{
+ u32 *start = (void *)&policy->h2g;
+ u32 *end = policy->h2g.data + policy->num_words;
+ size_t delta = end - start;
+
+ return delta;
+}
+
+static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy)
+{
+ policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV;
+ policy->max_words = ARRAY_SIZE(policy->h2g.data);
+ policy->num_words = 0;
+ policy->count = 0;
+
+ return policy;
+}
+
+static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy,
+ u32 action, u32 *data, u32 len)
+{
+ u32 *klv_ptr = policy->h2g.data + policy->num_words;
+
+ GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words);
+ *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) |
+ FIELD_PREP(GUC_KLV_0_LEN, len);
+ memcpy(klv_ptr, data, sizeof(u32) * len);
+ policy->num_words += 1 + len;
+ policy->count++;
+}
+
+static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
+ struct scheduling_policy *policy)
+{
+ int ret;
+
+ ret = intel_guc_send(guc, (u32 *)&policy->h2g,
+ __guc_scheduling_policy_action_size(policy));
+ if (ret < 0)
+ return ret;
+
+ if (ret != policy->count) {
+ drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
+ ret, policy->count);
+ if (ret > policy->count)
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+static int guc_init_global_schedule_policy(struct intel_guc *guc)
+{
+ struct scheduling_policy policy;
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0))
+ return 0;
+
+ __guc_scheduling_policy_start_klv(&policy);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ u32 yield[] = {
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION,
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO,
+ };
+
+ __guc_scheduling_policy_add_klv(&policy,
+ GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD,
+ yield, ARRAY_SIZE(yield));
+
+ ret = __guc_action_set_scheduling_policies(guc, &policy);
+ if (ret)
+ i915_probe_error(gt->i915,
+ "Failed to configure global scheduling policies: %pe!\n",
+ ERR_PTR(ret));
+ }
+
+ return ret;
+}
+
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
+ guc_init_global_schedule_policy(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index fb309ae43001,b91ad4aede1f..24aac2f32dd1
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@@ -339,6 -347,6 +347,7 @@@ bad
fw_blobs[i].blob.patch);
uc_fw->file_selected.path = NULL;
++
}
}
}
diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 098955526b68,c481daa4bbce..38a0ba4a1b3f
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi
st7701->dsi = dsi;
st7701->desc = desc;
- return mipi_dsi_attach(dsi);
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_attach;
+
+ return 0;
+
+err_attach:
+ drm_panel_remove(&st7701->panel);
+ return ret;
}
- static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
+ static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
{
struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
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commit c4252650a8c4770b669398fe7270ed8c94fc0eba
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
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gt/intel_sa_media.o \
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2019-04-24 17:48:39 +00:00
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gt/intel_sseu.o \
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2020-07-08 00:39:52 +00:00
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gt/intel_sseu_debugfs.o \
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2019-06-21 07:08:10 +00:00
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gt/intel_timeline.o \
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Merge DRM changes from upstream v6.1..v6.2
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.2 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/dma-buf/dma-buf.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
drivers/gpu/drm/ast/ast_drv.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_huc.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st
init_waitqueue_head(&dmabuf->poll);
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
+ INIT_LIST_HEAD(&dmabuf->attachments);
if (!resv) {
- resv = (struct dma_resv *)&dmabuf[1];
- dma_resv_init(resv);
+ dmabuf->resv = (struct dma_resv *)&dmabuf[1];
+ dma_resv_init(dmabuf->resv);
+ } else {
+ dmabuf->resv = resv;
}
- dmabuf->resv = resv;
- file = dma_buf_getfile(dmabuf, exp_info->flags);
- if (IS_ERR(file)) {
- ret = PTR_ERR(file);
+ ret = dma_buf_stats_setup(dmabuf, file);
+ if (ret)
goto err_dmabuf;
- }
+ file->f_mode |= FMODE_LSEEK;
+ file->private_data = dmabuf;
+ file->f_path.dentry->d_fsdata = dmabuf;
dmabuf->file = file;
- mutex_init(&dmabuf->lock);
- INIT_LIST_HEAD(&dmabuf->attachments);
-
mutex_lock(&db_list.lock);
list_add(&dmabuf->list_node, &db_list.head);
mutex_unlock(&db_list.lock);
diff --cc drivers/gpu/drm/bridge/ite-it6505.c
index 99123eec4551,21a9b8422bda..c13fb0bc6260
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_
DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
debugfs_init(it6505);
+ pm_runtime_enable(dev);
+
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+
it6505->bridge.funcs = &it6505_bridge_funcs;
it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 21cd1a4e1823,a0740308555d..bf68f2330dd9
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+
+ /* Wa_18017747507:dg2 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ }
}
static void
diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 4d1cc383b681,410905da8e97..e8d1bd04d2a2
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@@ -291,16 -350,17 +361,55 @@@ out
}
void intel_huc_fini(struct intel_huc *huc)
+ {
+ /*
+ * the fence is initialized in init_early, so we need to clean it up
+ * even if HuC loading is off.
+ */
+ delayed_huc_load_fini(huc);
+
+ if (intel_uc_fw_is_loadable(&huc->fw))
+ intel_uc_fw_fini(&huc->fw);
+ }
+
++void intel_huc_suspend(struct intel_huc *huc)
+{
+ if (!intel_uc_fw_is_loadable(&huc->fw))
+ return;
+
++ /*
++ * in the unlikely case that we're suspending before the GSC has
++ * completed its loading sequence, just stop waiting. We'll restart
++ * on resume.
++ */
+ delayed_huc_load_complete(huc);
++}
+
- i915_sw_fence_fini(&huc->delayed_load.fence);
- intel_uc_fw_fini(&huc->fw);
++int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
++{
++ struct intel_gt *gt = huc_to_gt(huc);
++ int ret;
++
++ ret = __intel_wait_for_register(gt->uncore,
++ huc->status.reg,
++ huc->status.mask,
++ huc->status.value,
++ 2, 50, NULL);
++
++ /* mark the load process as complete even if the wait failed */
++ delayed_huc_load_complete(huc);
++
++ if (ret) {
++ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
++ return ret;
++ }
++
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
++ drm_info(>->i915->drm, "HuC authenticated\n");
++ return 0;
+}
+
void intel_huc_suspend(struct intel_huc *huc)
{
if (!intel_uc_fw_is_loadable(&huc->fw))
Commit list:
commit 78a033433a5ae4fee85511ee075bc9a48312c79e
commit e23a40040819a7a3fcda3c6cedaeff80ad20c231
commit 4b3823ff7fa5bd000aa73384ec1f611980d00855
commit f569ae759472fbe1f6fdddc7398360d43fdcc199
commit fe5979665f6408092ff6072dc894b74a192cbb53
commit 1551b9164f6194ffee78935d1ff515f697619483
commit 835a4d18353492577093eff7cb6fa866f6e7014f
commit 01f0ce3e859619ea84104d668a87ace924bd12df
commit 1bed8b07342069ebfbab6794e5ce3084c3eb9bc8
commit dd890d428fe157f661e19e17c12349c785a97d4b
commit 48176104003058e2ba540fd815ec46c350d65926
commit 14f2f9bf34b180aa90b2088836f5153cb56db95e
commit 1cec34442408a77ba5396b19725fed2c398005c3
commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2
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commit bff0d857053bdacbde1e0deea3b468de3a2b7234
commit 9045c0529c40c1a9227d58cfb494033c82274a7d
commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2
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commit 07a70f38e9c33b3c614668b12a847f9fe65a4e25
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commit 3d99597c6496b9319f7522e0d073afab314d518a
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commit 783f6f852cc061e59962e53aa9824aa785de0d8c
commit 559f701db082a26f057463e14480cdf3306b1d91
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commit 6c1a6d0b64e1a15016ba7450cce8629f94de56c7
commit c6ac406cd8ff610a2d5da298b1d3071acfcde7f0
commit 4693e852f19a1338a49e540fb99fe3b2898d8594
commit 9734a75cd99d448814e64feca133dc9a6e3f65f2
commit 1b7ac7989ad82f8df6365cd6338df0d9937e0119
commit e7d636476ba73e61460619bd8822e16af3cba509
commit 337d5b5edc3d03a30a972aead75cc6be5dcebbf6
commit 0ed904169f85efcf9f82bd960597aac46260537f
commit 777c1e01cb7e1947765fb0c3b9b71dab18e53e46
commit 7484a5bc153e81a1740c06ce037fd55b7638335c
commit bb2ff6c27bc9e1da4d3ec5e7b1d6b9df1092cb5a
commit d5a1224aa68c8b124a4c5c390186e571815ed390
commit 1a6897921f52ceb2c8665ef826e405bd96385159
commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8
commit 8f32378986218812083b127da5ba42d48297d7c4
commit 2a00299e7447395d0898e7c6214817c06a61a8e8
commit a2a04b515562bbb040e8ae3decae8c1e9ef05327
commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
|
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gt/intel_wopcm.o \
|
2020-02-28 13:17:10 +00:00
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gt/intel_workarounds.o \
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drm/i915/gt: Keep a no-frills swappable copy of the default context state
We need to keep the default context state around to instantiate new
contexts (aka golden rendercontext), and we also keep it pinned while
the engine is active so that we can quickly reset a hanging context.
However, the default contexts are large enough to merit keeping in
swappable memory as opposed to kernel memory, so we store them inside
shmemfs. Currently, we use the normal GEM objects to create the default
context image, but we can throw away all but the shmemfs file.
This greatly simplifies the tricky power management code which wants to
run underneath the normal GT locking, and we definitely do not want to
use any high level objects that may appear to recurse back into the GT.
Though perhaps the primary advantage of the complex GEM object is that
we aggressively cache the mapping, but here we are recreating the
vm_area everytime time we unpark. At the worst, we add a lightweight
cache, but first find a microbenchmark that is impacted.
Having started to create some utility functions to make working with
shmemfs objects easier, we can start putting them to wider use, where
GEM objects are overkill, such as storing persistent error state.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429172429.6054-1-chris@chris-wilson.co.uk
2020-04-29 17:24:29 +00:00
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gt/shmem_utils.o \
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2020-02-28 13:17:10 +00:00
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gt/sysfs_engines.o
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Merge DRM changes from upstream v6.1..v6.2
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.2 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/dma-buf/dma-buf.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
drivers/gpu/drm/ast/ast_drv.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_huc.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st
init_waitqueue_head(&dmabuf->poll);
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
+ INIT_LIST_HEAD(&dmabuf->attachments);
if (!resv) {
- resv = (struct dma_resv *)&dmabuf[1];
- dma_resv_init(resv);
+ dmabuf->resv = (struct dma_resv *)&dmabuf[1];
+ dma_resv_init(dmabuf->resv);
+ } else {
+ dmabuf->resv = resv;
}
- dmabuf->resv = resv;
- file = dma_buf_getfile(dmabuf, exp_info->flags);
- if (IS_ERR(file)) {
- ret = PTR_ERR(file);
+ ret = dma_buf_stats_setup(dmabuf, file);
+ if (ret)
goto err_dmabuf;
- }
+ file->f_mode |= FMODE_LSEEK;
+ file->private_data = dmabuf;
+ file->f_path.dentry->d_fsdata = dmabuf;
dmabuf->file = file;
- mutex_init(&dmabuf->lock);
- INIT_LIST_HEAD(&dmabuf->attachments);
-
mutex_lock(&db_list.lock);
list_add(&dmabuf->list_node, &db_list.head);
mutex_unlock(&db_list.lock);
diff --cc drivers/gpu/drm/bridge/ite-it6505.c
index 99123eec4551,21a9b8422bda..c13fb0bc6260
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_
DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
debugfs_init(it6505);
+ pm_runtime_enable(dev);
+
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+
it6505->bridge.funcs = &it6505_bridge_funcs;
it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 21cd1a4e1823,a0740308555d..bf68f2330dd9
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+
+ /* Wa_18017747507:dg2 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ }
}
static void
diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 4d1cc383b681,410905da8e97..e8d1bd04d2a2
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@@ -291,16 -350,17 +361,55 @@@ out
}
void intel_huc_fini(struct intel_huc *huc)
+ {
+ /*
+ * the fence is initialized in init_early, so we need to clean it up
+ * even if HuC loading is off.
+ */
+ delayed_huc_load_fini(huc);
+
+ if (intel_uc_fw_is_loadable(&huc->fw))
+ intel_uc_fw_fini(&huc->fw);
+ }
+
++void intel_huc_suspend(struct intel_huc *huc)
+{
+ if (!intel_uc_fw_is_loadable(&huc->fw))
+ return;
+
++ /*
++ * in the unlikely case that we're suspending before the GSC has
++ * completed its loading sequence, just stop waiting. We'll restart
++ * on resume.
++ */
+ delayed_huc_load_complete(huc);
++}
+
- i915_sw_fence_fini(&huc->delayed_load.fence);
- intel_uc_fw_fini(&huc->fw);
++int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
++{
++ struct intel_gt *gt = huc_to_gt(huc);
++ int ret;
++
++ ret = __intel_wait_for_register(gt->uncore,
++ huc->status.reg,
++ huc->status.mask,
++ huc->status.value,
++ 2, 50, NULL);
++
++ /* mark the load process as complete even if the wait failed */
++ delayed_huc_load_complete(huc);
++
++ if (ret) {
++ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
++ return ret;
++ }
++
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
++ drm_info(>->i915->drm, "HuC authenticated\n");
++ return 0;
+}
+
void intel_huc_suspend(struct intel_huc *huc)
{
if (!intel_uc_fw_is_loadable(&huc->fw))
Commit list:
commit 78a033433a5ae4fee85511ee075bc9a48312c79e
commit e23a40040819a7a3fcda3c6cedaeff80ad20c231
commit 4b3823ff7fa5bd000aa73384ec1f611980d00855
commit f569ae759472fbe1f6fdddc7398360d43fdcc199
commit fe5979665f6408092ff6072dc894b74a192cbb53
commit 1551b9164f6194ffee78935d1ff515f697619483
commit 835a4d18353492577093eff7cb6fa866f6e7014f
commit 01f0ce3e859619ea84104d668a87ace924bd12df
commit 1bed8b07342069ebfbab6794e5ce3084c3eb9bc8
commit dd890d428fe157f661e19e17c12349c785a97d4b
commit 48176104003058e2ba540fd815ec46c350d65926
commit 14f2f9bf34b180aa90b2088836f5153cb56db95e
commit 1cec34442408a77ba5396b19725fed2c398005c3
commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2
commit 429a09553559297cc4e021fff2253f4035d3be2e
commit bff0d857053bdacbde1e0deea3b468de3a2b7234
commit 9045c0529c40c1a9227d58cfb494033c82274a7d
commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2
commit fb7818989976317cc2e78008aa2df7b9fe423c86
commit 07a70f38e9c33b3c614668b12a847f9fe65a4e25
commit e5f415bfc5c2c94fbb124f8aabfc638168a44cf4
commit 3d99597c6496b9319f7522e0d073afab314d518a
commit c40bd3b14f72446115241563ee0ce7273aa04f35
commit 783f6f852cc061e59962e53aa9824aa785de0d8c
commit 559f701db082a26f057463e14480cdf3306b1d91
commit 958349ff710b79d85f35be73d1b09991f67b3423
commit 7d33fd02dd943c7f8003e95930d15d92529fe917
commit 45810b4c5c33f785053169f053f282fbfd04e93e
commit c2c7075225ef7366a1ccc1cf4b7205c391ec7c9b
commit 944ca7d8b12f9ed4abaa4e63223b62bd9b653b5c
commit 8146d588bfc822b5377dfc0a227af77a57f7177f
commit 71690148dbcf2331a54e40da26970402bd07a527
commit d09aa852585aa12e8ca0aff1425c9806a6f42772
commit 107ba1a2c705f4358f2602ec2f2fd821bb651f42
commit 60c0df33da03c5aebcc5fb46363a1b58c784570e
commit 6a08cbda458e824ac824dddc6a07ed50efd0af70
commit 10c8cbeebd81d2e01437d59a4e47dc3de5925113
commit 49fd54034a523a9241cd73cda6da485112bf4414
commit 5e800d92313497a5a9fc7053890e870888181192
commit 6f7dd8e7d9f6039aa5c286726a941cf5344a784d
commit d7e4a2574520950613d29370ddd41c54a041589a
commit 9c7183a326521769bbddf155ea8f16aa9473de0c
commit 2f0f603a377237c9359d96184e2a6d8ae8299c9f
commit ab6214f3c3dbabdb4409e84fe7c1c43cb79c6c56
commit 6ac2f04ba1c4a81ff1e205625eaeae1ead152720
commit 8648c6048d4dc4d9294b7e7617c220bf446be0e7
commit bde544e1d7017f3169b4d97b2e19c2d28066d87c
commit 543ba9d6873b47982aa32c88a18177427e51ae25
commit ed57cfd9d54a772a1b60de6dd9f4e90fdba72a4a
commit 6340120014e8a82263f38c724ea8f3611cc0d074
commit 59f13af3b645e647247de14cc06f0d04c5cc24ae
commit 2d28094b26be804369fcf92315123ff07f3d4e0e
commit 86570b7b126bd516aba770d1fc4c971c55c66dca
commit eddb4afcb6c533d3f75f5f1a77e292fece27570e
commit fea1beb60db55abc05b2def917bff8e40825d3ed
commit aa07d34d9f2fba6cad41c85ead441dde27882fd5
commit 073a12f45fb8e3b21c9e08c36a2528d9f9e38d83
commit 8a549e8d19f401a717f72cc035f5df6b4d128564
commit e731a2d2fa13eaa584f4730d619e8e89061e4f6e
commit c286558f58535cf97b717b946d6c96d774a09d17
commit e5cedf9859b29642f8908f7e8949d983c748e2d0
commit f28d42663eb063173f63ee294465d2f336da325f
commit a82796a2e332d108b2d3aff38509caad370f69b5
commit 86b972ef1091882d66672399c6f8ebdd12a3b707
commit d24e7855ef7242a045d20af9c2a58474fe238993
commit abf46db341bd87261d0b3128bac9bdc204570284
commit 1e88da4f6d8938bef42b3bc6e9c68c795b46ce0f
commit b801d71493bbb9ec8dd4526bbec41f709621cb97
commit eb89e83c152b122a94e79527d63cb7c79823c37e
commit 55cfeecc2197de68e9cc30f77c711dcbcdf27510
commit 3dbf20e483cf3f31e287ad3152ffadd15a482e4f
commit c09ae4edd11062cd147328c77926330596277097
commit ac4e8560248f8c33c11b96a05ad64cfd1eb39665
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commit 8da8e32e0b095613af2c2ce4b322240269164a8e
commit a89a96a586114f67598c6391c75678b4dba5c2da
commit 91c9651425fe955b1387f3637607dda005f3f710
commit a627455bbe50a111475d7a42beb58fa64bd96c83
commit f25d9f81a8e09ace4f04106995550bae1f522143
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commit c5be8fc973830675a6463836e32b9a6e47852447
commit 9058f9d795ea9ad59fd579249a6d724d78dfeaf8
commit 887a193b4fb13e886d34bea4a1d8711fd775c7cf
commit 087b681805f1de084f89f1041af67295aa981192
commit 27536e03271da3dafcdddf735102041a26ad5bd0
commit e6177ec586d19fc62bba833ca0f6939f1a750928
commit b76c14c8fb2af1e481d51a4eeab8e0c0594824c0
commit a70eebb80022148dfd4d5f60fffd1914ff8e3683
commit bd8eb086611a7eb6bd03da2f4c3bddc64d082201
commit b4c1b4ce5d273c9d2be360f6a655aeeb884f67e3
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commit bb2ff6c27bc9e1da4d3ec5e7b1d6b9df1092cb5a
commit d5a1224aa68c8b124a4c5c390186e571815ed390
commit 1a6897921f52ceb2c8665ef826e405bd96385159
commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8
commit 8f32378986218812083b127da5ba42d48297d7c4
commit 2a00299e7447395d0898e7c6214817c06a61a8e8
commit a2a04b515562bbb040e8ae3decae8c1e9ef05327
commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
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2022-11-02 15:27:09 +00:00
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# x86 intel-gtt module support
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2022-11-02 15:48:10 +00:00
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gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
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2019-07-04 09:19:25 +00:00
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# autogenerated null render state
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gt-y += \
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gt/gen6_renderstate.o \
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gt/gen7_renderstate.o \
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gt/gen8_renderstate.o \
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gt/gen9_renderstate.o
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2019-04-24 17:48:39 +00:00
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i915-y += $(gt-y)
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# GEM (Graphics Execution Management) code
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2019-05-28 09:29:44 +00:00
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gem-y += \
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2019-05-28 09:29:53 +00:00
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gem/i915_gem_busy.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_clflush.o \
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gem/i915_gem_context.o \
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2021-01-14 18:24:00 +00:00
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gem/i915_gem_create.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_dmabuf.o \
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2019-05-28 09:29:48 +00:00
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gem/i915_gem_domain.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_execbuffer.o \
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gem/i915_gem_internal.o \
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2019-05-28 09:29:45 +00:00
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gem/i915_gem_object.o \
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2019-10-25 15:37:22 +00:00
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gem/i915_gem_lmem.o \
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2019-05-28 09:29:47 +00:00
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gem/i915_gem_mman.o \
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2019-05-28 09:29:46 +00:00
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gem/i915_gem_pages.o \
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gem/i915_gem_phys.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_pm.o \
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2019-10-08 16:01:14 +00:00
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gem/i915_gem_region.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_shmem.o \
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gem/i915_gem_shrinker.o \
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gem/i915_gem_stolen.o \
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2019-05-28 09:29:54 +00:00
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gem/i915_gem_throttle.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_tiling.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
commit 17917ff62443414569ea76e151e7a7ef44812264
commit 837f93247634b12e5eebb3d707405b701a4f3479
commit 867cf9cd73c3d31666e4b480aa4f52828d25ac94
commit 6eca310e8924ab98c73b81dfd39e7dd553ceddfd
commit 16c243e99d335e1ef3059871897119affc98b493
commit d098775ed44021293b1962dea61efb19297b8d02
commit 86441fa29e57940eeb00f35fefb1853c1fbe67bb
commit a3af0140663dc335e5c18277a61bb99bfcb60694
commit 26594678d00f94c62f2e43162bd6d10fd0b74917
commit a3a5f9d0fb15da90820254ba735491887cc12099
commit 213d5092776345ad5d6e2efa36a6bfbe9899e8b3
commit 2e53d7c1147a2751e959c53970c61b7ae33e1ecb
commit f425821b946847282708121600fffc20344183a0
commit cf3e3e86d77970211e0983130e896ae242601003
commit 0ea02bb8bc7a16446169bfae46938ea3a195db5d
commit aeb33699fc2c97994de0e9acb74d0fd319380614
commit 74c06c282ae63560fcf4073d1564f054d96285ec
commit cc5a3fc041f0104d97ac61b0423ec533d7a93214
commit a1e3667a9835e15101cf27731219fe2581dbf572
commit e0bbcc6233f7c664474287aaed8dcffd935a1869
commit a70e558c151043ce46a5e5999f4310e0b3551f57
commit 4c1b3d94bf632c1420a5d4108199f55a5655831d
commit d92223ead97cd697abe76c5b7a78160d6910a90d
commit 7a7a933edd6c3a6d5d64e08093f2d564104cefcd
commit a12be0277316ed923411c9c80b2899ee74d2b033
commit 74231041d14030f1ae6582b9233bfe782ac23e33
commit f674a218c610bea97c106ca8179b55b2a7a7528a
commit 8d9a8d9bd5034a88afef470664918aa914b1c3dc
commit b7d0949f6ce691131323fafabd48bf2f5074ae8d
commit baee602e5c0d00a7233fdb2b2bfd3ace4b5b8f29
commit 352a81b71ea0a3ce8f929aa60afe369d738a0c6a
commit 00f4471e42c871524c68ef1413d2fe53ce1d0a1b
commit bfd616ff9a2602ec66414438c3f9871a49fa1e16
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commit 53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67
commit 772970620a839141835eaf2bc507d957b10adcca
commit 3e4c31e8f70251732529a10934355084c7fab0ac
commit a79f40cccd4644c32f6d5ae1ccf091a262e1dc57
commit 13047a092c6d3f23b7d684b5b3fe46b2b50423b9
commit 982f8ad666a1123028a077b6b009871a0dc9df26
commit 004d2719806fb8e355c1bccd538e82c04319d391
commit 74056092ff415e7e20ce2544689b32ee811c4f0b
commit 0db55f9a1bafbe3dac750ea669de9134922389b5
commit def0c3697287f6e85d5ac68b21302966c95474f9
commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7
commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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gem/i915_gem_ttm.o \
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2022-05-23 17:15:52 +00:00
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gem/i915_gem_ttm_move.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
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commit efd330b97855013c8b58185683ddfb75deab5fa9
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commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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gem/i915_gem_ttm_pm.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gem_userptr.o \
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2019-05-28 09:29:52 +00:00
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gem/i915_gem_wait.o \
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2019-05-28 09:29:49 +00:00
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gem/i915_gemfs.o
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2019-02-05 13:00:02 +00:00
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i915-y += \
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2019-05-28 09:29:44 +00:00
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$(gem-y) \
|
2019-02-05 13:00:02 +00:00
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i915_active.o \
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i915_cmd_parser.o \
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2022-05-23 17:15:52 +00:00
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i915_deps.o \
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2010-08-07 10:01:23 +00:00
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i915_gem_evict.o \
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2010-11-25 18:00:26 +00:00
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i915_gem_gtt.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
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commit 17917ff62443414569ea76e151e7a7ef44812264
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commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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i915_gem_ww.o \
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2014-03-07 08:17:21 +00:00
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i915_gem.o \
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2018-03-06 12:28:56 +00:00
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i915_query.o \
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2018-02-21 09:56:36 +00:00
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i915_request.o \
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2018-10-01 14:47:54 +00:00
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i915_scheduler.o \
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2009-08-25 10:15:50 +00:00
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i915_trace_points.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
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commit 2ef8ea23942f4c2569930c34e7689a0cb1b232cc
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commit 74056092ff415e7e20ce2544689b32ee811c4f0b
commit 0db55f9a1bafbe3dac750ea669de9134922389b5
commit def0c3697287f6e85d5ac68b21302966c95474f9
commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7
commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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|
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i915_ttm_buddy_manager.o \
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2016-11-11 10:43:54 +00:00
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i915_vma.o \
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Merge DRM changes from upstream v6.1..v6.2
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.2 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/dma-buf/dma-buf.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
drivers/gpu/drm/ast/ast_drv.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_huc.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st
init_waitqueue_head(&dmabuf->poll);
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
+ INIT_LIST_HEAD(&dmabuf->attachments);
if (!resv) {
- resv = (struct dma_resv *)&dmabuf[1];
- dma_resv_init(resv);
+ dmabuf->resv = (struct dma_resv *)&dmabuf[1];
+ dma_resv_init(dmabuf->resv);
+ } else {
+ dmabuf->resv = resv;
}
- dmabuf->resv = resv;
- file = dma_buf_getfile(dmabuf, exp_info->flags);
- if (IS_ERR(file)) {
- ret = PTR_ERR(file);
+ ret = dma_buf_stats_setup(dmabuf, file);
+ if (ret)
goto err_dmabuf;
- }
+ file->f_mode |= FMODE_LSEEK;
+ file->private_data = dmabuf;
+ file->f_path.dentry->d_fsdata = dmabuf;
dmabuf->file = file;
- mutex_init(&dmabuf->lock);
- INIT_LIST_HEAD(&dmabuf->attachments);
-
mutex_lock(&db_list.lock);
list_add(&dmabuf->list_node, &db_list.head);
mutex_unlock(&db_list.lock);
diff --cc drivers/gpu/drm/bridge/ite-it6505.c
index 99123eec4551,21a9b8422bda..c13fb0bc6260
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_
DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
debugfs_init(it6505);
+ pm_runtime_enable(dev);
+
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+
it6505->bridge.funcs = &it6505_bridge_funcs;
it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 21cd1a4e1823,a0740308555d..bf68f2330dd9
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+
+ /* Wa_18017747507:dg2 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ }
}
static void
diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 4d1cc383b681,410905da8e97..e8d1bd04d2a2
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@@ -291,16 -350,17 +361,55 @@@ out
}
void intel_huc_fini(struct intel_huc *huc)
+ {
+ /*
+ * the fence is initialized in init_early, so we need to clean it up
+ * even if HuC loading is off.
+ */
+ delayed_huc_load_fini(huc);
+
+ if (intel_uc_fw_is_loadable(&huc->fw))
+ intel_uc_fw_fini(&huc->fw);
+ }
+
++void intel_huc_suspend(struct intel_huc *huc)
+{
+ if (!intel_uc_fw_is_loadable(&huc->fw))
+ return;
+
++ /*
++ * in the unlikely case that we're suspending before the GSC has
++ * completed its loading sequence, just stop waiting. We'll restart
++ * on resume.
++ */
+ delayed_huc_load_complete(huc);
++}
+
- i915_sw_fence_fini(&huc->delayed_load.fence);
- intel_uc_fw_fini(&huc->fw);
++int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
++{
++ struct intel_gt *gt = huc_to_gt(huc);
++ int ret;
++
++ ret = __intel_wait_for_register(gt->uncore,
++ huc->status.reg,
++ huc->status.mask,
++ huc->status.value,
++ 2, 50, NULL);
++
++ /* mark the load process as complete even if the wait failed */
++ delayed_huc_load_complete(huc);
++
++ if (ret) {
++ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
++ return ret;
++ }
++
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
++ drm_info(>->i915->drm, "HuC authenticated\n");
++ return 0;
+}
+
void intel_huc_suspend(struct intel_huc *huc)
{
if (!intel_uc_fw_is_loadable(&huc->fw))
Commit list:
commit 78a033433a5ae4fee85511ee075bc9a48312c79e
commit e23a40040819a7a3fcda3c6cedaeff80ad20c231
commit 4b3823ff7fa5bd000aa73384ec1f611980d00855
commit f569ae759472fbe1f6fdddc7398360d43fdcc199
commit fe5979665f6408092ff6072dc894b74a192cbb53
commit 1551b9164f6194ffee78935d1ff515f697619483
commit 835a4d18353492577093eff7cb6fa866f6e7014f
commit 01f0ce3e859619ea84104d668a87ace924bd12df
commit 1bed8b07342069ebfbab6794e5ce3084c3eb9bc8
commit dd890d428fe157f661e19e17c12349c785a97d4b
commit 48176104003058e2ba540fd815ec46c350d65926
commit 14f2f9bf34b180aa90b2088836f5153cb56db95e
commit 1cec34442408a77ba5396b19725fed2c398005c3
commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2
commit 429a09553559297cc4e021fff2253f4035d3be2e
commit bff0d857053bdacbde1e0deea3b468de3a2b7234
commit 9045c0529c40c1a9227d58cfb494033c82274a7d
commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2
commit fb7818989976317cc2e78008aa2df7b9fe423c86
commit 07a70f38e9c33b3c614668b12a847f9fe65a4e25
commit e5f415bfc5c2c94fbb124f8aabfc638168a44cf4
commit 3d99597c6496b9319f7522e0d073afab314d518a
commit c40bd3b14f72446115241563ee0ce7273aa04f35
commit 783f6f852cc061e59962e53aa9824aa785de0d8c
commit 559f701db082a26f057463e14480cdf3306b1d91
commit 958349ff710b79d85f35be73d1b09991f67b3423
commit 7d33fd02dd943c7f8003e95930d15d92529fe917
commit 45810b4c5c33f785053169f053f282fbfd04e93e
commit c2c7075225ef7366a1ccc1cf4b7205c391ec7c9b
commit 944ca7d8b12f9ed4abaa4e63223b62bd9b653b5c
commit 8146d588bfc822b5377dfc0a227af77a57f7177f
commit 71690148dbcf2331a54e40da26970402bd07a527
commit d09aa852585aa12e8ca0aff1425c9806a6f42772
commit 107ba1a2c705f4358f2602ec2f2fd821bb651f42
commit 60c0df33da03c5aebcc5fb46363a1b58c784570e
commit 6a08cbda458e824ac824dddc6a07ed50efd0af70
commit 10c8cbeebd81d2e01437d59a4e47dc3de5925113
commit 49fd54034a523a9241cd73cda6da485112bf4414
commit 5e800d92313497a5a9fc7053890e870888181192
commit 6f7dd8e7d9f6039aa5c286726a941cf5344a784d
commit d7e4a2574520950613d29370ddd41c54a041589a
commit 9c7183a326521769bbddf155ea8f16aa9473de0c
commit 2f0f603a377237c9359d96184e2a6d8ae8299c9f
commit ab6214f3c3dbabdb4409e84fe7c1c43cb79c6c56
commit 6ac2f04ba1c4a81ff1e205625eaeae1ead152720
commit 8648c6048d4dc4d9294b7e7617c220bf446be0e7
commit bde544e1d7017f3169b4d97b2e19c2d28066d87c
commit 543ba9d6873b47982aa32c88a18177427e51ae25
commit ed57cfd9d54a772a1b60de6dd9f4e90fdba72a4a
commit 6340120014e8a82263f38c724ea8f3611cc0d074
commit 59f13af3b645e647247de14cc06f0d04c5cc24ae
commit 2d28094b26be804369fcf92315123ff07f3d4e0e
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commit fea1beb60db55abc05b2def917bff8e40825d3ed
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commit e731a2d2fa13eaa584f4730d619e8e89061e4f6e
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commit e5cedf9859b29642f8908f7e8949d983c748e2d0
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commit a82796a2e332d108b2d3aff38509caad370f69b5
commit 86b972ef1091882d66672399c6f8ebdd12a3b707
commit d24e7855ef7242a045d20af9c2a58474fe238993
commit abf46db341bd87261d0b3128bac9bdc204570284
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commit a89a96a586114f67598c6391c75678b4dba5c2da
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commit 0ed904169f85efcf9f82bd960597aac46260537f
commit 777c1e01cb7e1947765fb0c3b9b71dab18e53e46
commit 7484a5bc153e81a1740c06ce037fd55b7638335c
commit bb2ff6c27bc9e1da4d3ec5e7b1d6b9df1092cb5a
commit d5a1224aa68c8b124a4c5c390186e571815ed390
commit 1a6897921f52ceb2c8665ef826e405bd96385159
commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8
commit 8f32378986218812083b127da5ba42d48297d7c4
commit 2a00299e7447395d0898e7c6214817c06a61a8e8
commit a2a04b515562bbb040e8ae3decae8c1e9ef05327
commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
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i915_vma_resource.o
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2014-03-07 08:17:21 +00:00
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2015-08-12 14:43:36 +00:00
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# general-purpose microcontroller (GuC) support
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2019-07-13 10:00:11 +00:00
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i915-y += gt/uc/intel_uc.o \
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2020-03-26 18:11:20 +00:00
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gt/uc/intel_uc_debugfs.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_uc_fw.o \
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gt/uc/intel_guc.o \
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gt/uc/intel_guc_ads.o \
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2022-11-02 15:27:09 +00:00
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gt/uc/intel_guc_capture.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_guc_ct.o \
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2020-03-26 18:11:20 +00:00
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gt/uc/intel_guc_debugfs.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_guc_fw.o \
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2022-11-02 15:27:09 +00:00
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gt/uc/intel_guc_hwconfig.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_guc_log.o \
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2020-03-26 18:11:20 +00:00
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gt/uc/intel_guc_log_debugfs.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
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commit 0dd10a961f2aa39d02e9aa2194946713cb36d403
commit 714d9e4574d54596973ee3b0624ee4a16264d700
commit 248b061689a40f4fed05252ee2c89f87cf26d7d8
commit c026565fe9be813fe826f7e5533ed763283af5f0
commit f732e2e34aa08493fdd762f3daa4e5f16bbf1e45
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commit 0068dc8c96688b72cc99470530b384429129950c
commit e02083f0bcc250c0556ec9e6f7ddb74220c72572
commit af628cdd64e11f03181a5a19645768ed4687bda4
commit 82a59c7f456db9f2874e9f1e9cb4cc19e71e95c5
commit 97794170b696856483f74b47bfb6049780d2d3a0
commit b693e42921e0220c0d564c55c6cdc680b0f85390
commit b253c3026c29d4231099d3cf8d984d25787793af
commit d1d94b0129dccd226784633c60b7df90e8a051b5
commit a14bc107edd0c108bda2245e50daa22f91c95d20
commit 59be177a909ac320e5f4b2a461ac09e20f35b2d8
commit 5afa7898ab7a0ec9c28556a91df714bf3c2f725e
commit c21b105380cf86e829c68586ca1315cfc253ad8c
commit c938aed88f8259dc913b717a32319101c66e87a9
commit 672437486ee9da3ed0e774937e6d0dd570921b39
commit 4835ea6c173a8d8dfbfdbb21c4cd987d12681610
commit dd8cb18906d97b2916fde42d32d915ae363c7e55
commit 2ef8ea23942f4c2569930c34e7689a0cb1b232cc
commit 53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67
commit 772970620a839141835eaf2bc507d957b10adcca
commit 3e4c31e8f70251732529a10934355084c7fab0ac
commit a79f40cccd4644c32f6d5ae1ccf091a262e1dc57
commit 13047a092c6d3f23b7d684b5b3fe46b2b50423b9
commit 982f8ad666a1123028a077b6b009871a0dc9df26
commit 004d2719806fb8e355c1bccd538e82c04319d391
commit 74056092ff415e7e20ce2544689b32ee811c4f0b
commit 0db55f9a1bafbe3dac750ea669de9134922389b5
commit def0c3697287f6e85d5ac68b21302966c95474f9
commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7
commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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gt/uc/intel_guc_rc.o \
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gt/uc/intel_guc_slpc.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_guc_submission.o \
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gt/uc/intel_huc.o \
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2020-03-26 18:11:20 +00:00
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gt/uc/intel_huc_debugfs.o \
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2019-07-13 10:00:11 +00:00
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gt/uc/intel_huc_fw.o
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2015-08-12 14:43:36 +00:00
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2022-09-26 14:12:00 +00:00
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# graphics system controller (GSC) support
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i915-y += gt/intel_gsc.o
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Merge DRM changes from upstream v6.1..v6.2
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.2 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/dma-buf/dma-buf.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
drivers/gpu/drm/ast/ast_drv.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_huc.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st
init_waitqueue_head(&dmabuf->poll);
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
+ INIT_LIST_HEAD(&dmabuf->attachments);
if (!resv) {
- resv = (struct dma_resv *)&dmabuf[1];
- dma_resv_init(resv);
+ dmabuf->resv = (struct dma_resv *)&dmabuf[1];
+ dma_resv_init(dmabuf->resv);
+ } else {
+ dmabuf->resv = resv;
}
- dmabuf->resv = resv;
- file = dma_buf_getfile(dmabuf, exp_info->flags);
- if (IS_ERR(file)) {
- ret = PTR_ERR(file);
+ ret = dma_buf_stats_setup(dmabuf, file);
+ if (ret)
goto err_dmabuf;
- }
+ file->f_mode |= FMODE_LSEEK;
+ file->private_data = dmabuf;
+ file->f_path.dentry->d_fsdata = dmabuf;
dmabuf->file = file;
- mutex_init(&dmabuf->lock);
- INIT_LIST_HEAD(&dmabuf->attachments);
-
mutex_lock(&db_list.lock);
list_add(&dmabuf->list_node, &db_list.head);
mutex_unlock(&db_list.lock);
diff --cc drivers/gpu/drm/bridge/ite-it6505.c
index 99123eec4551,21a9b8422bda..c13fb0bc6260
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_
DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
debugfs_init(it6505);
+ pm_runtime_enable(dev);
+
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+
it6505->bridge.funcs = &it6505_bridge_funcs;
it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 21cd1a4e1823,a0740308555d..bf68f2330dd9
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+
+ /* Wa_18017747507:dg2 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ }
}
static void
diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 4d1cc383b681,410905da8e97..e8d1bd04d2a2
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@@ -291,16 -350,17 +361,55 @@@ out
}
void intel_huc_fini(struct intel_huc *huc)
+ {
+ /*
+ * the fence is initialized in init_early, so we need to clean it up
+ * even if HuC loading is off.
+ */
+ delayed_huc_load_fini(huc);
+
+ if (intel_uc_fw_is_loadable(&huc->fw))
+ intel_uc_fw_fini(&huc->fw);
+ }
+
++void intel_huc_suspend(struct intel_huc *huc)
+{
+ if (!intel_uc_fw_is_loadable(&huc->fw))
+ return;
+
++ /*
++ * in the unlikely case that we're suspending before the GSC has
++ * completed its loading sequence, just stop waiting. We'll restart
++ * on resume.
++ */
+ delayed_huc_load_complete(huc);
++}
+
- i915_sw_fence_fini(&huc->delayed_load.fence);
- intel_uc_fw_fini(&huc->fw);
++int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
++{
++ struct intel_gt *gt = huc_to_gt(huc);
++ int ret;
++
++ ret = __intel_wait_for_register(gt->uncore,
++ huc->status.reg,
++ huc->status.mask,
++ huc->status.value,
++ 2, 50, NULL);
++
++ /* mark the load process as complete even if the wait failed */
++ delayed_huc_load_complete(huc);
++
++ if (ret) {
++ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
++ return ret;
++ }
++
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
++ drm_info(>->i915->drm, "HuC authenticated\n");
++ return 0;
+}
+
void intel_huc_suspend(struct intel_huc *huc)
{
if (!intel_uc_fw_is_loadable(&huc->fw))
Commit list:
commit 78a033433a5ae4fee85511ee075bc9a48312c79e
commit e23a40040819a7a3fcda3c6cedaeff80ad20c231
commit 4b3823ff7fa5bd000aa73384ec1f611980d00855
commit f569ae759472fbe1f6fdddc7398360d43fdcc199
commit fe5979665f6408092ff6072dc894b74a192cbb53
commit 1551b9164f6194ffee78935d1ff515f697619483
commit 835a4d18353492577093eff7cb6fa866f6e7014f
commit 01f0ce3e859619ea84104d668a87ace924bd12df
commit 1bed8b07342069ebfbab6794e5ce3084c3eb9bc8
commit dd890d428fe157f661e19e17c12349c785a97d4b
commit 48176104003058e2ba540fd815ec46c350d65926
commit 14f2f9bf34b180aa90b2088836f5153cb56db95e
commit 1cec34442408a77ba5396b19725fed2c398005c3
commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2
commit 429a09553559297cc4e021fff2253f4035d3be2e
commit bff0d857053bdacbde1e0deea3b468de3a2b7234
commit 9045c0529c40c1a9227d58cfb494033c82274a7d
commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2
commit fb7818989976317cc2e78008aa2df7b9fe423c86
commit 07a70f38e9c33b3c614668b12a847f9fe65a4e25
commit e5f415bfc5c2c94fbb124f8aabfc638168a44cf4
commit 3d99597c6496b9319f7522e0d073afab314d518a
commit c40bd3b14f72446115241563ee0ce7273aa04f35
commit 783f6f852cc061e59962e53aa9824aa785de0d8c
commit 559f701db082a26f057463e14480cdf3306b1d91
commit 958349ff710b79d85f35be73d1b09991f67b3423
commit 7d33fd02dd943c7f8003e95930d15d92529fe917
commit 45810b4c5c33f785053169f053f282fbfd04e93e
commit c2c7075225ef7366a1ccc1cf4b7205c391ec7c9b
commit 944ca7d8b12f9ed4abaa4e63223b62bd9b653b5c
commit 8146d588bfc822b5377dfc0a227af77a57f7177f
commit 71690148dbcf2331a54e40da26970402bd07a527
commit d09aa852585aa12e8ca0aff1425c9806a6f42772
commit 107ba1a2c705f4358f2602ec2f2fd821bb651f42
commit 60c0df33da03c5aebcc5fb46363a1b58c784570e
commit 6a08cbda458e824ac824dddc6a07ed50efd0af70
commit 10c8cbeebd81d2e01437d59a4e47dc3de5925113
commit 49fd54034a523a9241cd73cda6da485112bf4414
commit 5e800d92313497a5a9fc7053890e870888181192
commit 6f7dd8e7d9f6039aa5c286726a941cf5344a784d
commit d7e4a2574520950613d29370ddd41c54a041589a
commit 9c7183a326521769bbddf155ea8f16aa9473de0c
commit 2f0f603a377237c9359d96184e2a6d8ae8299c9f
commit ab6214f3c3dbabdb4409e84fe7c1c43cb79c6c56
commit 6ac2f04ba1c4a81ff1e205625eaeae1ead152720
commit 8648c6048d4dc4d9294b7e7617c220bf446be0e7
commit bde544e1d7017f3169b4d97b2e19c2d28066d87c
commit 543ba9d6873b47982aa32c88a18177427e51ae25
commit ed57cfd9d54a772a1b60de6dd9f4e90fdba72a4a
commit 6340120014e8a82263f38c724ea8f3611cc0d074
commit 59f13af3b645e647247de14cc06f0d04c5cc24ae
commit 2d28094b26be804369fcf92315123ff07f3d4e0e
commit 86570b7b126bd516aba770d1fc4c971c55c66dca
commit eddb4afcb6c533d3f75f5f1a77e292fece27570e
commit fea1beb60db55abc05b2def917bff8e40825d3ed
commit aa07d34d9f2fba6cad41c85ead441dde27882fd5
commit 073a12f45fb8e3b21c9e08c36a2528d9f9e38d83
commit 8a549e8d19f401a717f72cc035f5df6b4d128564
commit e731a2d2fa13eaa584f4730d619e8e89061e4f6e
commit c286558f58535cf97b717b946d6c96d774a09d17
commit e5cedf9859b29642f8908f7e8949d983c748e2d0
commit f28d42663eb063173f63ee294465d2f336da325f
commit a82796a2e332d108b2d3aff38509caad370f69b5
commit 86b972ef1091882d66672399c6f8ebdd12a3b707
commit d24e7855ef7242a045d20af9c2a58474fe238993
commit abf46db341bd87261d0b3128bac9bdc204570284
commit 1e88da4f6d8938bef42b3bc6e9c68c795b46ce0f
commit b801d71493bbb9ec8dd4526bbec41f709621cb97
commit eb89e83c152b122a94e79527d63cb7c79823c37e
commit 55cfeecc2197de68e9cc30f77c711dcbcdf27510
commit 3dbf20e483cf3f31e287ad3152ffadd15a482e4f
commit c09ae4edd11062cd147328c77926330596277097
commit ac4e8560248f8c33c11b96a05ad64cfd1eb39665
commit 59cfc750f537b973e17583ce8f14a913401a5ac0
commit c50cec9bab620927445e9c7c050a8fae536557b8
commit da3dbdfea49cbaef41f37a566470b27df3e0e9ab
commit e26ec8aebfbbb38cb3733d64b793e5c0085cbcee
commit 0d0e7d1eea9e7379b8709a71283eaadd94af37ca
commit 319b0869f51c16034c48627d77ec62fc3b9dccfe
commit 064751a6c5dc719d28a490268f140d4d9cf379d4
commit 2a40e5848a9526c3ad5d35e1aab4c04df117693b
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commit 296cd8ecfd305dae76722bb683943cdfefe7f4d3
commit 0c31611437b7155f115919a24f31673ffe94deee
commit 08fb97de03aa2205c6791301bd83a095abc1949c
commit dbb2ffbfd708b2d0f1b7fe0083c5e3333d0fe35b
commit c3d5cfe7b978acea8c0613fb3a068d376ad93463
commit b1f80a5aaa9e8e1c2cbaf5bd65bb27bcaefb33d3
commit d263545ef0a32a087ec9dd89edb2ee1be1de629f
commit 6fa964c045a6bc3321a9186e87bfbcfd1059b0f1
commit 8da8e32e0b095613af2c2ce4b322240269164a8e
commit a89a96a586114f67598c6391c75678b4dba5c2da
commit 91c9651425fe955b1387f3637607dda005f3f710
commit a627455bbe50a111475d7a42beb58fa64bd96c83
commit f25d9f81a8e09ace4f04106995550bae1f522143
commit 334810f82024815283a6e7febd3d2de1fed6c232
commit d5c45330c8986aff945de997383e19b5b7a85b9a
commit df2f59c5857b56a5cc40b6562b032c5d8d50cdfc
commit 61564e6c5a4addf170b75415c4ac86282784a072
commit 2e25c1fba7145f610c7e4744f3ed99ffff559152
commit adc831bfc8852034d0834a5a8bf7e35e2faeb8b2
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commit 97acb6a8fcc4e5c2cdc2693a35acdc5a7461aaa3
commit c72891256a8068a4c6e335f3e6944e53539230bb
commit c5be8fc973830675a6463836e32b9a6e47852447
commit 9058f9d795ea9ad59fd579249a6d724d78dfeaf8
commit 887a193b4fb13e886d34bea4a1d8711fd775c7cf
commit 087b681805f1de084f89f1041af67295aa981192
commit 27536e03271da3dafcdddf735102041a26ad5bd0
commit e6177ec586d19fc62bba833ca0f6939f1a750928
commit b76c14c8fb2af1e481d51a4eeab8e0c0594824c0
commit a70eebb80022148dfd4d5f60fffd1914ff8e3683
commit bd8eb086611a7eb6bd03da2f4c3bddc64d082201
commit b4c1b4ce5d273c9d2be360f6a655aeeb884f67e3
commit 353b6bf2c4f14f0049cc8db5c2cca26882ff76b4
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commit d5a1224aa68c8b124a4c5c390186e571815ed390
commit 1a6897921f52ceb2c8665ef826e405bd96385159
commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8
commit 8f32378986218812083b127da5ba42d48297d7c4
commit 2a00299e7447395d0898e7c6214817c06a61a8e8
commit a2a04b515562bbb040e8ae3decae8c1e9ef05327
commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
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# graphics hardware monitoring (HWMON) support
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i915-$(CONFIG_HWMON) += i915_hwmon.o
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2014-03-07 08:17:21 +00:00
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# modesetting core code
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2019-06-13 08:44:16 +00:00
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i915-y += \
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2022-05-23 17:17:03 +00:00
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display/hsw_ips.o \
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2019-06-13 08:44:16 +00:00
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display/intel_atomic.o \
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display/intel_atomic_plane.o \
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display/intel_audio.o \
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display/intel_bios.o \
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display/intel_bw.o \
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display/intel_cdclk.o \
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display/intel_color.o \
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display/intel_combo_phy.o \
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display/intel_connector.o \
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2021-01-14 11:13:45 +00:00
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display/intel_crtc.o \
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2022-11-02 15:48:10 +00:00
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display/intel_crtc_state_dump.o \
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2020-12-21 09:04:48 +00:00
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display/intel_cursor.o \
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2019-06-13 08:44:16 +00:00
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display/intel_display.o \
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display/intel_display_power.o \
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2022-11-02 15:27:09 +00:00
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display/intel_display_power_map.o \
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display/intel_display_power_well.o \
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2021-05-18 21:34:44 +00:00
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display/intel_dmc.o \
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2019-06-13 08:44:16 +00:00
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display/intel_dpio_phy.o \
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2021-01-14 11:13:46 +00:00
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display/intel_dpll.o \
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2019-06-13 08:44:16 +00:00
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display/intel_dpll_mgr.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
commit 7b812171257d4b8d9ef69321134c72b647e1ce9c
commit 5918241f607616c0cd9565f575f4cd955fa435e0
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commit e485382ea7eb4b81f4b59073cd831084820497de
commit 8581fd402a0cf80b5298e3b225e7a7bd8f110e69
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commit d46f329a3f6048e04736e86cb13c880645048792
commit 8c45096c60d6ce6341c374636100ed1b2c1c33a1
commit daf8de0874ab5b74b38a38726fdd3d07ef98a7ee
commit 7be3be2b027c12e84833b3dc9597d3bb7e4c5464
commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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display/intel_dpt.o \
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display/intel_drrs.o \
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2019-09-20 11:59:22 +00:00
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display/intel_dsb.o \
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2021-03-25 21:47:49 +00:00
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display/intel_fb.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
commit 7b812171257d4b8d9ef69321134c72b647e1ce9c
commit 5918241f607616c0cd9565f575f4cd955fa435e0
commit 0707570248b8b13008d0fca7cc4f6e1848f0d64f
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commit b2eb7d716426fe056596761cd371005d64e9caec
commit 32a4eb04d59ae8d5bb5baa5a8528e31094ae8e84
commit 992c238188a83befa0094a8c00bfead31aa302ed
commit d8959fb33890ba1956c142e83398e89812450ffc
commit f492283b157053e9555787262f058ae33096f568
commit ea5ea3d8a117517a75c2af30faa399671444a1ea
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commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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display/intel_fb_pin.o \
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2019-06-13 08:44:16 +00:00
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display/intel_fbc.o \
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2021-01-14 11:13:47 +00:00
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display/intel_fdi.o \
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2019-06-13 08:44:16 +00:00
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display/intel_fifo_underrun.o \
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display/intel_frontbuffer.o \
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2020-01-20 17:47:24 +00:00
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display/intel_global_state.o \
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2019-06-13 08:44:16 +00:00
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display/intel_hdcp.o \
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display/intel_hotplug.o \
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Merge DRM changes from upstream v6.1..v6.2
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.2 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/dma-buf/dma-buf.c
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
drivers/gpu/drm/ast/ast_drv.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/drm_atomic_helper.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/selftest_slpc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_huc.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/i915/pxp/intel_pxp_huc.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h
drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.c
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 3ac41b7d82f7,e6528767efc7..6ed1ec778f70
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -653,25 -660,23 +660,24 @@@ struct dma_buf *dma_buf_export(const st
init_waitqueue_head(&dmabuf->poll);
dmabuf->cb_in.poll = dmabuf->cb_out.poll = &dmabuf->poll;
dmabuf->cb_in.active = dmabuf->cb_out.active = 0;
+ INIT_LIST_HEAD(&dmabuf->attachments);
if (!resv) {
- resv = (struct dma_resv *)&dmabuf[1];
- dma_resv_init(resv);
+ dmabuf->resv = (struct dma_resv *)&dmabuf[1];
+ dma_resv_init(dmabuf->resv);
+ } else {
+ dmabuf->resv = resv;
}
- dmabuf->resv = resv;
- file = dma_buf_getfile(dmabuf, exp_info->flags);
- if (IS_ERR(file)) {
- ret = PTR_ERR(file);
+ ret = dma_buf_stats_setup(dmabuf, file);
+ if (ret)
goto err_dmabuf;
- }
+ file->f_mode |= FMODE_LSEEK;
+ file->private_data = dmabuf;
+ file->f_path.dentry->d_fsdata = dmabuf;
dmabuf->file = file;
- mutex_init(&dmabuf->lock);
- INIT_LIST_HEAD(&dmabuf->attachments);
-
mutex_lock(&db_list.lock);
list_add(&dmabuf->list_node, &db_list.head);
mutex_unlock(&db_list.lock);
diff --cc drivers/gpu/drm/bridge/ite-it6505.c
index 99123eec4551,21a9b8422bda..c13fb0bc6260
--- a/drivers/gpu/drm/bridge/ite-it6505.c
+++ b/drivers/gpu/drm/bridge/ite-it6505.c
@@@ -3312,12 -3343,13 +3343,18 @@@ static int it6505_i2c_probe(struct i2c_
DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
debugfs_init(it6505);
+ pm_runtime_enable(dev);
+
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+ it6505->aux.name = "DP-AUX";
+ it6505->aux.dev = dev;
+ it6505->aux.transfer = it6505_aux_transfer;
+ drm_dp_aux_init(&it6505->aux);
+
it6505->bridge.funcs = &it6505_bridge_funcs;
it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 21cd1a4e1823,a0740308555d..bf68f2330dd9
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2779,19 -2998,22 +2998,30 @@@ general_render_compute_wa_init(struct i
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ }
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+
+ /* Wa_18017747507:dg2 */
+ wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
}
+
+ if (IS_DG2(i915)) {
+ /*
+ * Wa_16011620976:dg2_g11
+ * Wa_22015475538:dg2
+ */
+ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ }
}
static void
diff --cc drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 4d1cc383b681,410905da8e97..e8d1bd04d2a2
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@@ -291,16 -350,17 +361,55 @@@ out
}
void intel_huc_fini(struct intel_huc *huc)
+ {
+ /*
+ * the fence is initialized in init_early, so we need to clean it up
+ * even if HuC loading is off.
+ */
+ delayed_huc_load_fini(huc);
+
+ if (intel_uc_fw_is_loadable(&huc->fw))
+ intel_uc_fw_fini(&huc->fw);
+ }
+
++void intel_huc_suspend(struct intel_huc *huc)
+{
+ if (!intel_uc_fw_is_loadable(&huc->fw))
+ return;
+
++ /*
++ * in the unlikely case that we're suspending before the GSC has
++ * completed its loading sequence, just stop waiting. We'll restart
++ * on resume.
++ */
+ delayed_huc_load_complete(huc);
++}
+
- i915_sw_fence_fini(&huc->delayed_load.fence);
- intel_uc_fw_fini(&huc->fw);
++int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
++{
++ struct intel_gt *gt = huc_to_gt(huc);
++ int ret;
++
++ ret = __intel_wait_for_register(gt->uncore,
++ huc->status.reg,
++ huc->status.mask,
++ huc->status.value,
++ 2, 50, NULL);
++
++ /* mark the load process as complete even if the wait failed */
++ delayed_huc_load_complete(huc);
++
++ if (ret) {
++ drm_err(>->i915->drm, "HuC: Firmware not verified %d\n", ret);
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
++ return ret;
++ }
++
++ intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
++ drm_info(>->i915->drm, "HuC authenticated\n");
++ return 0;
+}
+
void intel_huc_suspend(struct intel_huc *huc)
{
if (!intel_uc_fw_is_loadable(&huc->fw))
Commit list:
commit 78a033433a5ae4fee85511ee075bc9a48312c79e
commit e23a40040819a7a3fcda3c6cedaeff80ad20c231
commit 4b3823ff7fa5bd000aa73384ec1f611980d00855
commit f569ae759472fbe1f6fdddc7398360d43fdcc199
commit fe5979665f6408092ff6072dc894b74a192cbb53
commit 1551b9164f6194ffee78935d1ff515f697619483
commit 835a4d18353492577093eff7cb6fa866f6e7014f
commit 01f0ce3e859619ea84104d668a87ace924bd12df
commit 1bed8b07342069ebfbab6794e5ce3084c3eb9bc8
commit dd890d428fe157f661e19e17c12349c785a97d4b
commit 48176104003058e2ba540fd815ec46c350d65926
commit 14f2f9bf34b180aa90b2088836f5153cb56db95e
commit 1cec34442408a77ba5396b19725fed2c398005c3
commit ad3aa7c31efa5a09b0dba42e66cfdf77e0db7dc2
commit 429a09553559297cc4e021fff2253f4035d3be2e
commit bff0d857053bdacbde1e0deea3b468de3a2b7234
commit 9045c0529c40c1a9227d58cfb494033c82274a7d
commit 0d2d201095e9f141d6a9fb44320afce761f8b5c2
commit fb7818989976317cc2e78008aa2df7b9fe423c86
commit 07a70f38e9c33b3c614668b12a847f9fe65a4e25
commit e5f415bfc5c2c94fbb124f8aabfc638168a44cf4
commit 3d99597c6496b9319f7522e0d073afab314d518a
commit c40bd3b14f72446115241563ee0ce7273aa04f35
commit 783f6f852cc061e59962e53aa9824aa785de0d8c
commit 559f701db082a26f057463e14480cdf3306b1d91
commit 958349ff710b79d85f35be73d1b09991f67b3423
commit 7d33fd02dd943c7f8003e95930d15d92529fe917
commit 45810b4c5c33f785053169f053f282fbfd04e93e
commit c2c7075225ef7366a1ccc1cf4b7205c391ec7c9b
commit 944ca7d8b12f9ed4abaa4e63223b62bd9b653b5c
commit 8146d588bfc822b5377dfc0a227af77a57f7177f
commit 71690148dbcf2331a54e40da26970402bd07a527
commit d09aa852585aa12e8ca0aff1425c9806a6f42772
commit 107ba1a2c705f4358f2602ec2f2fd821bb651f42
commit 60c0df33da03c5aebcc5fb46363a1b58c784570e
commit 6a08cbda458e824ac824dddc6a07ed50efd0af70
commit 10c8cbeebd81d2e01437d59a4e47dc3de5925113
commit 49fd54034a523a9241cd73cda6da485112bf4414
commit 5e800d92313497a5a9fc7053890e870888181192
commit 6f7dd8e7d9f6039aa5c286726a941cf5344a784d
commit d7e4a2574520950613d29370ddd41c54a041589a
commit 9c7183a326521769bbddf155ea8f16aa9473de0c
commit 2f0f603a377237c9359d96184e2a6d8ae8299c9f
commit ab6214f3c3dbabdb4409e84fe7c1c43cb79c6c56
commit 6ac2f04ba1c4a81ff1e205625eaeae1ead152720
commit 8648c6048d4dc4d9294b7e7617c220bf446be0e7
commit bde544e1d7017f3169b4d97b2e19c2d28066d87c
commit 543ba9d6873b47982aa32c88a18177427e51ae25
commit ed57cfd9d54a772a1b60de6dd9f4e90fdba72a4a
commit 6340120014e8a82263f38c724ea8f3611cc0d074
commit 59f13af3b645e647247de14cc06f0d04c5cc24ae
commit 2d28094b26be804369fcf92315123ff07f3d4e0e
commit 86570b7b126bd516aba770d1fc4c971c55c66dca
commit eddb4afcb6c533d3f75f5f1a77e292fece27570e
commit fea1beb60db55abc05b2def917bff8e40825d3ed
commit aa07d34d9f2fba6cad41c85ead441dde27882fd5
commit 073a12f45fb8e3b21c9e08c36a2528d9f9e38d83
commit 8a549e8d19f401a717f72cc035f5df6b4d128564
commit e731a2d2fa13eaa584f4730d619e8e89061e4f6e
commit c286558f58535cf97b717b946d6c96d774a09d17
commit e5cedf9859b29642f8908f7e8949d983c748e2d0
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commit a82796a2e332d108b2d3aff38509caad370f69b5
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commit d24e7855ef7242a045d20af9c2a58474fe238993
commit abf46db341bd87261d0b3128bac9bdc204570284
commit 1e88da4f6d8938bef42b3bc6e9c68c795b46ce0f
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commit 3dbf20e483cf3f31e287ad3152ffadd15a482e4f
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commit a89a96a586114f67598c6391c75678b4dba5c2da
commit 91c9651425fe955b1387f3637607dda005f3f710
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commit dd2db2dc4bd298f33dea50c80c3c11bee4e3b0a4
commit 275d8a1db261a1272a818d40ebc61b3b865b60e5
commit 154711aa5759ef9b45903124fa813c4c29ee681c
commit 1538709c9f1c207d30afd95ea41b3aeb973f67e7
commit bb25849c0fa550b26cecc9c476c519a927c66898
commit 5048fa1ebf89d03cf0ceca13fab8f800399e9ee3
commit ac7170082c0e140663f0853d3de733a5341ce7b0
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commit abf301e14e42702c11ab20331aa4d0ab87a777ca
commit 74d6c8ea183e73031db635a96f67bc30ae1fc2ee
commit f1a9e82a1203802df3c917dd7ab1b5a5ded55793
commit bffede38f82c27cf5e203a2c659fcc9b581dd7b8
commit 9f8b3706eb23bed26f7898af3c6f7fe3858564a1
commit 90d5e8301ac24550be80d193aa5582cab56c29fc
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commit 49d0555976f0972af68397ed996375c135b38ba7
commit 0e763afcb50814e256ecb780fcc0f3bade2e1a0c
commit 9874cc2df4e892c8744aa0472866cbf7c3cf1862
commit dc38b996db968f51f0fe45845a519c5cd7f6bd04
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commit 5ad7bbf3dba5c4a684338df1f285080f2588b535
commit 6c1a6d0b64e1a15016ba7450cce8629f94de56c7
commit c6ac406cd8ff610a2d5da298b1d3071acfcde7f0
commit 4693e852f19a1338a49e540fb99fe3b2898d8594
commit 9734a75cd99d448814e64feca133dc9a6e3f65f2
commit 1b7ac7989ad82f8df6365cd6338df0d9937e0119
commit e7d636476ba73e61460619bd8822e16af3cba509
commit 337d5b5edc3d03a30a972aead75cc6be5dcebbf6
commit 0ed904169f85efcf9f82bd960597aac46260537f
commit 777c1e01cb7e1947765fb0c3b9b71dab18e53e46
commit 7484a5bc153e81a1740c06ce037fd55b7638335c
commit bb2ff6c27bc9e1da4d3ec5e7b1d6b9df1092cb5a
commit d5a1224aa68c8b124a4c5c390186e571815ed390
commit 1a6897921f52ceb2c8665ef826e405bd96385159
commit a950b989ea29ab3b38ea7f6e3d2540700a3c54e8
commit 8f32378986218812083b127da5ba42d48297d7c4
commit 2a00299e7447395d0898e7c6214817c06a61a8e8
commit a2a04b515562bbb040e8ae3decae8c1e9ef05327
commit f7597e3c58eeb9ce534993f53c982f2e91e6dd4d
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 14:19:42 +00:00
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display/intel_hti.o \
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2019-06-13 08:44:16 +00:00
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display/intel_lpe_audio.o \
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2022-11-02 15:48:10 +00:00
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display/intel_modeset_verify.o \
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display/intel_modeset_setup.o \
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2019-06-13 08:44:16 +00:00
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display/intel_overlay.o \
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2022-05-23 17:15:52 +00:00
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display/intel_pch_display.o \
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display/intel_pch_refclk.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
commit 7b812171257d4b8d9ef69321134c72b647e1ce9c
commit 5918241f607616c0cd9565f575f4cd955fa435e0
commit 0707570248b8b13008d0fca7cc4f6e1848f0d64f
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commit b2eb7d716426fe056596761cd371005d64e9caec
commit 32a4eb04d59ae8d5bb5baa5a8528e31094ae8e84
commit 992c238188a83befa0094a8c00bfead31aa302ed
commit d8959fb33890ba1956c142e83398e89812450ffc
commit f492283b157053e9555787262f058ae33096f568
commit ea5ea3d8a117517a75c2af30faa399671444a1ea
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Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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display/i9xx_plane.o \
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2021-02-05 14:48:42 +00:00
|
|
|
display/skl_scaler.o \
|
Merge DRM changes from upstream v6.0.8..v6.1
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.1 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/mgag200/mgag200_pll.c
Conflict resolution:
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ecb8db731081,253ea6b159df..6ebed4d58ced
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@@ -162,6 -162,7 +162,8 @@@
#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
+ #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque
*/
static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
{
- uint8_t i;
- int j;
++
+ int i, j;
struct dc_stream_state *stream = NULL;
struct dc_plane_state *plane = NULL;
uint32_t cursor_size = 0;
@@@ -237,24 -236,24 +237,27 @@@
mblk_width = DCN3_2_MBLK_WIDTH;
mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
++
/* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
* FLOOR(vp_x_start, blk_width)
*
* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c
*/
mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
- pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) +
+ pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) -
(pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
++
/* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
* FLOOR(vp_y_start, blk_height)
*
* mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c
*/
mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
- pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) +
+ pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) -
(pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
++
num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
diff --cc drivers/gpu/drm/ast/ast_mode.c
index b93181a42048,1bc0220e6783..ae5a4cce972f
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@@ -42,9 -40,8 +42,8 @@@
#include <drm/drm_fourcc.h>
#include <drm/drm_gem_atomic_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
-#include <drm/drm_gem_vram_helper.h>
+#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_managed.h>
- #include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
@@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane
static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_crtc_state *crtc_state;
- struct ast_crtc_state *ast_crtc_state;
+ struct drm_device *dev = plane->dev;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_crtc_state *new_crtc_state = NULL;
+ struct ast_crtc_state *new_ast_crtc_state;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
false, true);
- if (ret)
+ if (ret) {
return ret;
+ } else if (!new_plane_state->visible) {
+ if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */
+ return -EINVAL;
+ else
+ return 0;
+ }
- if (!new_plane_state->visible)
- return 0;
-
- ast_crtc_state = to_ast_crtc_state(crtc_state);
+ new_ast_crtc_state = to_ast_crtc_state(new_crtc_state);
- ast_crtc_state->format = new_plane_state->fb->format;
+ new_ast_crtc_state->format = new_plane_state->fb->format;
return 0;
}
@@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_
static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_framebuffer *fb = new_plane_state->fb;
- struct drm_crtc_state *crtc_state;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_framebuffer *new_fb = new_plane_state->fb;
+ struct drm_crtc_state *new_crtc_state = NULL;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
true, true);
- if (ret)
+ if (ret || !new_plane_state->visible)
return ret;
- if (!new_plane_state->visible)
- return 0;
-
- if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
+ if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT)
return -EINVAL;
return 0;
diff --cc drivers/gpu/drm/i915/display/intel_display.c
index bd629f2da6eb,de77054195c6..d3bfa2a675b8
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9
else if (DISPLAY_VER(i915) >= 11)
pipes = BIT(PIPE_B) | BIT(PIPE_C);
else
++
pipes = 0;
- return pipes & RUNTIME_INFO(i915)->pipe_mask;
+ return pipes & INTEL_INFO(i915)->display.pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj
return !strncmp(kobj->name, "gt", 2);
}
- static struct intel_gt *kobj_to_gt(struct kobject *kobj)
- {
- return container_of(kobj, struct intel_gt, sysfs_gt);
- }
-
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name)
{
- struct kobject *kobj = &dev->kobj;
-
/*
* We are interested at knowing from where the interface
* has been called, whether it's called from gt/ or from
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
index 6bee2c6a894d,6232923a420d..c3a123faee98
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g
struct kobject *dir,
const char *name);
+ static inline struct intel_gt *kobj_to_gt(struct kobject *kobj)
+ {
+ return container_of(kobj, struct intel_gt, sysfs_gt);
+ }
+
void intel_gt_sysfs_register(struct intel_gt *gt);
void intel_gt_sysfs_unregister(struct intel_gt *gt);
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name);
#endif /* SYSFS_GT_H */
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe
NULL
};
+ static ssize_t
+ default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
+ }
+
+ static struct kobj_attribute default_min_freq_mhz =
+ __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
+
+ static ssize_t
+ default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
+ }
+
+ static struct kobj_attribute default_max_freq_mhz =
+ __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
+
+ static const struct attribute * const rps_defaults_attrs[] = {
+ &default_min_freq_mhz.attr,
+ &default_max_freq_mhz.attr,
+ NULL
+ };
+
-static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
- const struct attribute * const *attrs)
+static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
{
+ const struct attribute * const *attrs;
+ struct attribute *vlv_attr;
int ret;
if (GRAPHICS_VER(gt->i915) < 6)
diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4,3955292483a6..d3ac73c3559f
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc
/* hsdes: 1809175790 */
if (!HAS_FLAT_CCS(ce->engine->i915))
- cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
+ cs = gen12_emit_aux_table_inv(ce->engine->gt,
+ cs, GEN12_GFX_CCS_AUX_NV);
+
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+
return cs;
}
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b6479b5bd32,a821e3d405db..21cd1a4e1823
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ }
- /* Wa_16011620976:dg2_g11 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 844dee09a321,1db59eeb34db..1ac0e66d39e5
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i
return 0;
}
+struct scheduling_policy {
+ /* internal data */
+ u32 max_words, num_words;
+ u32 count;
+ /* API data */
+ struct guc_update_scheduling_policy h2g;
+};
+
+static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy)
+{
+ u32 *start = (void *)&policy->h2g;
+ u32 *end = policy->h2g.data + policy->num_words;
+ size_t delta = end - start;
+
+ return delta;
+}
+
+static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy)
+{
+ policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV;
+ policy->max_words = ARRAY_SIZE(policy->h2g.data);
+ policy->num_words = 0;
+ policy->count = 0;
+
+ return policy;
+}
+
+static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy,
+ u32 action, u32 *data, u32 len)
+{
+ u32 *klv_ptr = policy->h2g.data + policy->num_words;
+
+ GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words);
+ *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) |
+ FIELD_PREP(GUC_KLV_0_LEN, len);
+ memcpy(klv_ptr, data, sizeof(u32) * len);
+ policy->num_words += 1 + len;
+ policy->count++;
+}
+
+static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
+ struct scheduling_policy *policy)
+{
+ int ret;
+
+ ret = intel_guc_send(guc, (u32 *)&policy->h2g,
+ __guc_scheduling_policy_action_size(policy));
+ if (ret < 0)
+ return ret;
+
+ if (ret != policy->count) {
+ drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
+ ret, policy->count);
+ if (ret > policy->count)
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+static int guc_init_global_schedule_policy(struct intel_guc *guc)
+{
+ struct scheduling_policy policy;
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0))
+ return 0;
+
+ __guc_scheduling_policy_start_klv(&policy);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ u32 yield[] = {
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION,
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO,
+ };
+
+ __guc_scheduling_policy_add_klv(&policy,
+ GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD,
+ yield, ARRAY_SIZE(yield));
+
+ ret = __guc_action_set_scheduling_policies(guc, &policy);
+ if (ret)
+ i915_probe_error(gt->i915,
+ "Failed to configure global scheduling policies: %pe!\n",
+ ERR_PTR(ret));
+ }
+
+ return ret;
+}
+
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
+ guc_init_global_schedule_policy(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index fb309ae43001,b91ad4aede1f..24aac2f32dd1
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@@ -339,6 -347,6 +347,7 @@@ bad
fw_blobs[i].blob.patch);
uc_fw->file_selected.path = NULL;
++
}
}
}
diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 098955526b68,c481daa4bbce..38a0ba4a1b3f
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi
st7701->dsi = dsi;
st7701->desc = desc;
- return mipi_dsi_attach(dsi);
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_attach;
+
+ return 0;
+
+err_attach:
+ drm_panel_remove(&st7701->panel);
+ return ret;
}
- static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
+ static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
{
struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
Commit list:
commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f
commit 6dc548745d5b5102e3c53dc5097296ac270b6c69
commit 859161b952a453b86362f168fadef72a8ba31a05
commit d72ac4bbf4cc8f6b50526ce400861f176659884f
commit 1fd452c403ca2cd9dcbd8465f9f72be52e15ac1a
commit 79abca2b399009eb8d12c652d0f0f7a9c7a06289
commit 96dc635d5538055cb6ccd7b6e9290dfcfc385f97
commit dc1dc76bd9a48c6aba3efae5eadb9a884043966e
commit 356d2c8e76ebb1134a0685ce4b923d8201337475
commit 4c59b0805e9bf873fd3f5dca4fc53d8c220e39b4
commit e5bd7e3e4a68f0befe53f59954b25eec9a792d60
commit ba71593217b5b03c9e3385b268ff8613a71fc6ce
commit 0a2486f85e0cfa6439116abb9078ab888a619746
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commit d3d6b1bf85aefe0ebc0624574b3bb62f0693914c
commit 9a8cc8cabc1e351614fd7f9e774757a5143b6fe8
commit c082fbd687ad70a92e0a8be486a7555a66f03079
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commit c290db013742e98fe5b64073bc2dd8c8a2ac9e4c
commit 24013314be6ee4ee456114a671e9fa3461323de8
commit 09bf649a74573cb596e211418a4f8008f265c5a9
commit 6e90293618ed476d6b11f82ce724efbb9e9a071b
commit bc21fe9a5844c5bc8f7ec319b11d2671a94eb867
commit aeffc8fb2174f017a10df114bc312f899904dc68
commit c4252650a8c4770b669398fe7270ed8c94fc0eba
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
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display/skl_universal_plane.o \
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display/skl_watermark.o
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2019-06-13 08:44:16 +00:00
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i915-$(CONFIG_ACPI) += \
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display/intel_acpi.o \
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display/intel_opregion.o
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i915-$(CONFIG_DRM_FBDEV_EMULATION) += \
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display/intel_fbdev.o
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2014-03-07 08:17:21 +00:00
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# modesetting output/encoder code
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2019-06-13 08:44:15 +00:00
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i915-y += \
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display/dvo_ch7017.o \
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display/dvo_ch7xxx.o \
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display/dvo_ivch.o \
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display/dvo_ns2501.o \
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display/dvo_sil164.o \
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display/dvo_tfp410.o \
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2021-03-18 16:10:13 +00:00
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display/g4x_dp.o \
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2021-03-18 16:10:14 +00:00
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display/g4x_hdmi.o \
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2019-06-13 08:44:15 +00:00
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display/icl_dsi.o \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
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commit ebae8973884ee9ac703b3bfe34cabbb118b18538
commit 2eb82577a16d4c8eb31e4ed520649850bb95b223
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commit a07f8b9983543d465b50870ab4f845d4d710ed3f
commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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display/intel_backlight.o \
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2019-06-13 08:44:15 +00:00
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display/intel_crt.o \
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display/intel_ddi.o \
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2021-02-04 19:43:18 +00:00
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display/intel_ddi_buf_trans.o \
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2022-05-23 17:15:52 +00:00
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display/intel_display_trace.o \
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Merge DRM changes from upstream v6.0.8..v6.1
NOTE: This commit does not compile due to missing RHEL-specific fix-ups,
which are split out into separate Git commits following this one.
If git bisect selected this commit, run "git bisect skip" and try again.
Repeat this until it selects a commit which compiles.
This commit was generated using:
rhdrm-merge-drm v6.1 2160457
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2160457
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/ast/ast_mode.c
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_workarounds.c
drivers/gpu/drm/i915/gt/uc/intel_guc.c
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
drivers/gpu/drm/i915/gvt/kvmgt.c
drivers/gpu/drm/mgag200/mgag200_pll.c
Conflict resolution:
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ecb8db731081,253ea6b159df..6ebed4d58ced
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@@ -162,6 -162,7 +162,8 @@@
#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
++#define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
+ #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
#define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER 0x00000001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x00000001
diff --cc drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 3128c111c619,d0b46a3e0155..6f6f6e5ad14b
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@@ -206,8 -206,7 +206,8 @@@ static bool dcn32_check_no_memory_reque
*/
static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
{
- uint8_t i;
- int j;
++
+ int i, j;
struct dc_stream_state *stream = NULL;
struct dc_plane_state *plane = NULL;
uint32_t cursor_size = 0;
@@@ -237,24 -236,24 +237,27 @@@
mblk_width = DCN3_2_MBLK_WIDTH;
mblk_height = bytes_per_pixel == 4 ? DCN3_2_MBLK_HEIGHT_4BPE : DCN3_2_MBLK_HEIGHT_8BPE;
++
/* full_vp_width_blk_aligned = FLOOR(vp_x_start + full_vp_width + blk_width - 1, blk_width) -
* FLOOR(vp_x_start, blk_width)
*
* mall_alloc_width_blk_aligned_l/c = full_vp_width_blk_aligned_l/c
*/
mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x +
- pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) +
+ pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) -
(pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width);
++
/* full_vp_height_blk_aligned = FLOOR(vp_y_start + full_vp_height + blk_height - 1, blk_height) -
* FLOOR(vp_y_start, blk_height)
*
* mall_alloc_height_blk_aligned_l/c = full_vp_height_blk_aligned_l/c
*/
mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y +
- pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) +
+ pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) -
(pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height);
++
num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *
((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);
diff --cc drivers/gpu/drm/ast/ast_mode.c
index b93181a42048,1bc0220e6783..ae5a4cce972f
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@@ -42,9 -40,8 +42,8 @@@
#include <drm/drm_fourcc.h>
#include <drm/drm_gem_atomic_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
-#include <drm/drm_gem_vram_helper.h>
+#include <drm/drm_gem_shmem_helper.h>
#include <drm/drm_managed.h>
- #include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
@@@ -604,31 -550,31 +603,31 @@@ static const uint32_t ast_primary_plane
static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_crtc_state *crtc_state;
- struct ast_crtc_state *ast_crtc_state;
+ struct drm_device *dev = plane->dev;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_crtc_state *new_crtc_state = NULL;
+ struct ast_crtc_state *new_ast_crtc_state;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
false, true);
- if (ret)
+ if (ret) {
return ret;
+ } else if (!new_plane_state->visible) {
+ if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */
+ return -EINVAL;
+ else
+ return 0;
+ }
- if (!new_plane_state->visible)
- return 0;
-
- ast_crtc_state = to_ast_crtc_state(crtc_state);
+ new_ast_crtc_state = to_ast_crtc_state(new_crtc_state);
- ast_crtc_state->format = new_plane_state->fb->format;
+ new_ast_crtc_state->format = new_plane_state->fb->format;
return 0;
}
@@@ -850,22 -774,29 +849,22 @@@ static const uint32_t ast_cursor_plane_
static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *state)
{
- struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
- plane);
- struct drm_framebuffer *fb = new_plane_state->fb;
- struct drm_crtc_state *crtc_state;
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_framebuffer *new_fb = new_plane_state->fb;
+ struct drm_crtc_state *new_crtc_state = NULL;
int ret;
- if (!new_plane_state->crtc)
- return 0;
-
- crtc_state = drm_atomic_get_new_crtc_state(state,
- new_plane_state->crtc);
+ if (new_plane_state->crtc)
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
- ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
- DRM_PLANE_HELPER_NO_SCALING,
- DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
true, true);
- if (ret)
+ if (ret || !new_plane_state->visible)
return ret;
- if (!new_plane_state->visible)
- return 0;
-
- if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
+ if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT)
return -EINVAL;
return 0;
diff --cc drivers/gpu/drm/i915/display/intel_display.c
index bd629f2da6eb,de77054195c6..d3bfa2a675b8
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@@ -3724,9 -3730,9 +3730,10 @@@ static u8 bigjoiner_pipes(struct drm_i9
else if (DISPLAY_VER(i915) >= 11)
pipes = BIT(PIPE_B) | BIT(PIPE_C);
else
++
pipes = 0;
- return pipes & RUNTIME_INFO(i915)->pipe_mask;
+ return pipes & INTEL_INFO(i915)->display.pipe_mask;
}
static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index 1e52ea387dc5,d651ccd0ab20..fb733fa8a491
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@@ -22,14 -22,11 +22,9 @@@ bool is_object_gt(struct kobject *kobj
return !strncmp(kobj->name, "gt", 2);
}
- static struct intel_gt *kobj_to_gt(struct kobject *kobj)
- {
- return container_of(kobj, struct intel_gt, sysfs_gt);
- }
-
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name)
{
- struct kobject *kobj = &dev->kobj;
-
/*
* We are interested at knowing from where the interface
* has been called, whether it's called from gt/ or from
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
index 6bee2c6a894d,6232923a420d..c3a123faee98
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@@ -22,9 -23,14 +23,14 @@@ intel_gt_create_kobj(struct intel_gt *g
struct kobject *dir,
const char *name);
+ static inline struct intel_gt *kobj_to_gt(struct kobject *kobj)
+ {
+ return container_of(kobj, struct intel_gt, sysfs_gt);
+ }
+
void intel_gt_sysfs_register(struct intel_gt *gt);
void intel_gt_sysfs_unregister(struct intel_gt *gt);
-struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct kobject *kobj,
const char *name);
#endif /* SYSFS_GT_H */
diff --cc drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 1fef52e7c2c8,180dd6f3ef57..426da98a96ed
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@@ -682,10 -726,37 +682,39 @@@ static const struct attribute *media_pe
NULL
};
+ static ssize_t
+ default_min_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.min_freq);
+ }
+
+ static struct kobj_attribute default_min_freq_mhz =
+ __ATTR(rps_min_freq_mhz, 0444, default_min_freq_mhz_show, NULL);
+
+ static ssize_t
+ default_max_freq_mhz_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+ {
+ struct intel_gt *gt = kobj_to_gt(kobj->parent);
+
+ return sysfs_emit(buf, "%u\n", gt->defaults.max_freq);
+ }
+
+ static struct kobj_attribute default_max_freq_mhz =
+ __ATTR(rps_max_freq_mhz, 0444, default_max_freq_mhz_show, NULL);
+
+ static const struct attribute * const rps_defaults_attrs[] = {
+ &default_min_freq_mhz.attr,
+ &default_max_freq_mhz.attr,
+ NULL
+ };
+
-static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
- const struct attribute * const *attrs)
+static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj)
{
+ const struct attribute * const *attrs;
+ struct attribute *vlv_attr;
int ret;
if (GRAPHICS_VER(gt->i915) < 6)
diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c
index 070cec4ff8a4,3955292483a6..d3ac73c3559f
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@@ -1278,12 -1298,13 +1298,17 @@@ gen12_emit_indirect_ctx_rcs(const struc
/* hsdes: 1809175790 */
if (!HAS_FLAT_CCS(ce->engine->i915))
- cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
+ cs = gen12_emit_aux_table_inv(ce->engine->gt,
+ cs, GEN12_GFX_CCS_AUX_NV);
+
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+ /* Wa_16014892111 */
+ if (IS_DG2(ce->engine->i915))
+ cs = dg2_emit_draw_watermark_setting(cs);
+
return cs;
}
diff --cc drivers/gpu/drm/i915/gt/intel_workarounds.c
index 1b6479b5bd32,a821e3d405db..21cd1a4e1823
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@@ -2108,15 -2108,18 +2108,22 @@@ rcs_engine_wa_init(struct intel_engine_
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ }
- /* Wa_16011620976:dg2_g11 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
}
+ if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
+ IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
+ /* Wa_1509727124:dg2 */
+ wa_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ }
+
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
diff --cc drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 844dee09a321,1db59eeb34db..1ac0e66d39e5
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@@ -4209,103 -4177,18 +4185,111 @@@ int intel_guc_submission_setup(struct i
return 0;
}
+struct scheduling_policy {
+ /* internal data */
+ u32 max_words, num_words;
+ u32 count;
+ /* API data */
+ struct guc_update_scheduling_policy h2g;
+};
+
+static u32 __guc_scheduling_policy_action_size(struct scheduling_policy *policy)
+{
+ u32 *start = (void *)&policy->h2g;
+ u32 *end = policy->h2g.data + policy->num_words;
+ size_t delta = end - start;
+
+ return delta;
+}
+
+static struct scheduling_policy *__guc_scheduling_policy_start_klv(struct scheduling_policy *policy)
+{
+ policy->h2g.header.action = INTEL_GUC_ACTION_UPDATE_SCHEDULING_POLICIES_KLV;
+ policy->max_words = ARRAY_SIZE(policy->h2g.data);
+ policy->num_words = 0;
+ policy->count = 0;
+
+ return policy;
+}
+
+static void __guc_scheduling_policy_add_klv(struct scheduling_policy *policy,
+ u32 action, u32 *data, u32 len)
+{
+ u32 *klv_ptr = policy->h2g.data + policy->num_words;
+
+ GEM_BUG_ON((policy->num_words + 1 + len) > policy->max_words);
+ *(klv_ptr++) = FIELD_PREP(GUC_KLV_0_KEY, action) |
+ FIELD_PREP(GUC_KLV_0_LEN, len);
+ memcpy(klv_ptr, data, sizeof(u32) * len);
+ policy->num_words += 1 + len;
+ policy->count++;
+}
+
+static int __guc_action_set_scheduling_policies(struct intel_guc *guc,
+ struct scheduling_policy *policy)
+{
+ int ret;
+
+ ret = intel_guc_send(guc, (u32 *)&policy->h2g,
+ __guc_scheduling_policy_action_size(policy));
+ if (ret < 0)
+ return ret;
+
+ if (ret != policy->count) {
+ drm_warn(&guc_to_gt(guc)->i915->drm, "GuC global scheduler policy processed %d of %d KLVs!",
+ ret, policy->count);
+ if (ret > policy->count)
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+static int guc_init_global_schedule_policy(struct intel_guc *guc)
+{
+ struct scheduling_policy policy;
+ struct intel_gt *gt = guc_to_gt(guc);
+ intel_wakeref_t wakeref;
+ int ret = 0;
+
+ if (GET_UC_VER(guc) < MAKE_UC_VER(70, 3, 0))
+ return 0;
+
+ __guc_scheduling_policy_start_klv(&policy);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ u32 yield[] = {
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION,
+ GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO,
+ };
+
+ __guc_scheduling_policy_add_klv(&policy,
+ GUC_SCHEDULING_POLICIES_KLV_ID_RENDER_COMPUTE_YIELD,
+ yield, ARRAY_SIZE(yield));
+
+ ret = __guc_action_set_scheduling_policies(guc, &policy);
+ if (ret)
+ i915_probe_error(gt->i915,
+ "Failed to configure global scheduling policies: %pe!\n",
+ ERR_PTR(ret));
+ }
+
+ return ret;
+}
+
void intel_guc_submission_enable(struct intel_guc *guc)
{
+ struct intel_gt *gt = guc_to_gt(guc);
+
+ /* Enable and route to GuC */
+ if (GRAPHICS_VER(gt->i915) >= 12)
+ intel_uncore_write(gt->uncore, GEN12_GUC_SEM_INTR_ENABLES,
+ GUC_SEM_INTR_ROUTE_TO_GUC |
+ GUC_SEM_INTR_ENABLE_ALL);
+
guc_init_lrc_mapping(guc);
guc_init_engine_stats(guc);
+ guc_init_global_schedule_policy(guc);
}
void intel_guc_submission_disable(struct intel_guc *guc)
diff --cc drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index fb309ae43001,b91ad4aede1f..24aac2f32dd1
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@@ -339,6 -347,6 +347,7 @@@ bad
fw_blobs[i].blob.patch);
uc_fw->file_selected.path = NULL;
++
}
}
}
diff --cc drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 098955526b68,c481daa4bbce..38a0ba4a1b3f
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@@ -384,18 -762,10 +762,18 @@@ static int st7701_dsi_probe(struct mipi
st7701->dsi = dsi;
st7701->desc = desc;
- return mipi_dsi_attach(dsi);
+ ret = mipi_dsi_attach(dsi);
+ if (ret)
+ goto err_attach;
+
+ return 0;
+
+err_attach:
+ drm_panel_remove(&st7701->panel);
+ return ret;
}
- static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
+ static void st7701_dsi_remove(struct mipi_dsi_device *dsi)
{
struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
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commit 40cdb02cb9f965732eb543d47f15bef8d10f0f5f
commit 6dc548745d5b5102e3c53dc5097296ac270b6c69
commit 859161b952a453b86362f168fadef72a8ba31a05
commit d72ac4bbf4cc8f6b50526ce400861f176659884f
commit 1fd452c403ca2cd9dcbd8465f9f72be52e15ac1a
commit 79abca2b399009eb8d12c652d0f0f7a9c7a06289
commit 96dc635d5538055cb6ccd7b6e9290dfcfc385f97
commit dc1dc76bd9a48c6aba3efae5eadb9a884043966e
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commit 4c59b0805e9bf873fd3f5dca4fc53d8c220e39b4
commit e5bd7e3e4a68f0befe53f59954b25eec9a792d60
commit ba71593217b5b03c9e3385b268ff8613a71fc6ce
commit 0a2486f85e0cfa6439116abb9078ab888a619746
commit 8aba4d30520ed656065eb36f0628109bdea385ee
commit d093100b425df6fe400881f2e62c3f0be7bf18cf
commit b92db7e4fe740daab858366faff1f992d53d3ff4
commit 0c05fcd3b45d6769c496fc6e2b88d18fc78ebe11
commit a6aa679a70e9d8fa4ad3f519c060db9bb186e21c
commit 6de745238aa30529778a26622a430dfcb171b089
commit d395fb1999abb7eaa3fb5fd2107cae0f1e41e6d0
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commit 347987a2cf0d146484d1c586951ef10028bb1674
commit 63af82cf5e36b6ba3f3ebcdd1edd9f91934bfa59
commit 64e257f187a5c76ec5766f50204462c0c483e418
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commit ba8f16cd081902350e2d2a00afcc6b77b1815d50
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commit 3c1ea6a5f4f55d4e376675dda16945eb5d9bb4de
commit a8899b8728013c7b2456f0bfa20e5fea85ee0fd1
commit 12b8b046e4c9de40fa59b6f067d6826f4e688f68
commit 8c115864501fc09932cdfec53d9ec1cde82b4a28
commit 04aa64375f48a5d430b5550d9271f8428883e550
commit 6f6cb1714365a07dbc66851879538df9f6969288
commit d3d6b1bf85aefe0ebc0624574b3bb62f0693914c
commit 9a8cc8cabc1e351614fd7f9e774757a5143b6fe8
commit c082fbd687ad70a92e0a8be486a7555a66f03079
commit bdaa78c6aa861f0e8c612a0b2272423d92f0071c
commit c290db013742e98fe5b64073bc2dd8c8a2ac9e4c
commit 24013314be6ee4ee456114a671e9fa3461323de8
commit 09bf649a74573cb596e211418a4f8008f265c5a9
commit 6e90293618ed476d6b11f82ce724efbb9e9a071b
commit bc21fe9a5844c5bc8f7ec319b11d2671a94eb867
commit aeffc8fb2174f017a10df114bc312f899904dc68
commit c4252650a8c4770b669398fe7270ed8c94fc0eba
Signed-off-by: Mika Penttilä <mpenttil@redhat.com>
2023-04-27 13:56:29 +00:00
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display/intel_dkl_phy.o \
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2019-06-13 08:44:15 +00:00
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display/intel_dp.o \
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2021-01-20 10:18:34 +00:00
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display/intel_dp_aux.o \
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2019-06-13 08:44:15 +00:00
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display/intel_dp_aux_backlight.o \
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2020-08-18 15:39:00 +00:00
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display/intel_dp_hdcp.o \
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2019-06-13 08:44:15 +00:00
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display/intel_dp_link_training.o \
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display/intel_dp_mst.o \
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display/intel_dsi.o \
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display/intel_dsi_dcs_backlight.o \
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display/intel_dsi_vbt.o \
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display/intel_dvo.o \
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display/intel_gmbus.o \
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display/intel_hdmi.o \
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display/intel_lspcon.o \
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display/intel_lvds.o \
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display/intel_panel.o \
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2021-05-19 00:06:10 +00:00
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display/intel_qp_tables.o \
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Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
commit 17917ff62443414569ea76e151e7a7ef44812264
commit 837f93247634b12e5eebb3d707405b701a4f3479
commit 867cf9cd73c3d31666e4b480aa4f52828d25ac94
commit 6eca310e8924ab98c73b81dfd39e7dd553ceddfd
commit 16c243e99d335e1ef3059871897119affc98b493
commit d098775ed44021293b1962dea61efb19297b8d02
commit 86441fa29e57940eeb00f35fefb1853c1fbe67bb
commit a3af0140663dc335e5c18277a61bb99bfcb60694
commit 26594678d00f94c62f2e43162bd6d10fd0b74917
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commit 0db55f9a1bafbe3dac750ea669de9134922389b5
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commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
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commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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display/intel_snps_phy.o \
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2019-06-13 08:44:15 +00:00
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display/intel_tv.o \
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display/intel_vdsc.o \
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2021-01-25 20:08:18 +00:00
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display/intel_vrr.o \
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2019-06-13 08:44:15 +00:00
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display/vlv_dsi.o \
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display/vlv_dsi_pll.o
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2013-10-09 07:18:51 +00:00
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2019-06-26 12:38:26 +00:00
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i915-y += i915_perf.o
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2022-11-28 15:00:47 +00:00
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# Protected execution platform (PXP) support. Base support is required for HuC
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i915-y += \
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
commit 5c5c40e28c52a36bb5ac26817275d5a0281ab819
commit 70418a68713c13da3f36c388087d0220b456a430
commit fa9899dad3ed84a8b6433467670d4cacd9b873bc
commit 89f2e7ab4dd93d8785619ce58838391b9b07feb7
commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
commit 8b46cc6577f4bbef7e5909bb926da31d705f350f
commit b97090575ed27f8a23cc8f8ace642d5a8ea59206
commit 8b93d1d7dbd578fd296e70008b29c0f62d09d7cb
commit 804b6e5ee613b019b942ba6be52cccecd9d33655
commit 45d9c8dde4cd8589f9180309ec60f0da2ce486e4
commit efd330b97855013c8b58185683ddfb75deab5fa9
commit ad482232e3cc6d65eaeb19ce2412887458b19559
commit d5ef86b38e4c2a65d5c1d64d8d0f3fcf58aa0884
commit ebd8cbf1fb968cb1c3e3cf7b26dfe2c1f201bdf0
commit f6864b27d6d324771d979694de7ca455afbad32a
commit 7b812171257d4b8d9ef69321134c72b647e1ce9c
commit 5918241f607616c0cd9565f575f4cd955fa435e0
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Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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i915-$(CONFIG_DRM_I915_PXP) += \
|
Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
commit 5798a769d6f5be656638c5e6e0cd5c4f155a2fb5
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commit 70418a68713c13da3f36c388087d0220b456a430
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commit d16de9a25b5cc458d0c8c978970f8edf9cf710d0
commit 01da701b77d498ed2625483c58bd73000e2767e3
commit c5589bb5dccb0c5cb74910da93663f489589f3ce
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commit d97e631af2db84c8c9d63abf68d487d0bb559e4c
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commit 33735c1c8d0223170d79dbe166976d9cd7339c7a
commit 33bb63915fee190102cae7d6576bc51a0bc342b2
commit ee2698cf79cc759a397c61086c758d4cc85938bf
commit aeeb82fd6147b65689f0f1e5aaa389d34212a3c7
commit ce9b333c73a5a8707f2f446a837a6ca743ddcffd
commit eaa090538e8d21801c6d5f94590c3799e6a528b5
commit b95dc06af3e683d6b7ddbbae178b2b2a21ee8b2b
commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
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pxp/intel_pxp_cmd.o \
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pxp/intel_pxp_debugfs.o \
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pxp/intel_pxp_irq.o \
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2022-11-28 15:00:47 +00:00
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pxp/intel_pxp_session.o
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Merge DRM changes from upstream v5.15..v5.16
This commit was generated using:
rhdrm-merge-drm v5.16 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/drm_connector.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/i915_gem_object_types.h
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/intel_uncore.c
Conflict resolution:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3012cbe5b0b7,da85169006d4..a0aa6dbe120e
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -295,11 -299,12 +299,13 @@@ struct drm_i915_gem_object
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
- #define I915_BO_READONLY BIT(4)
- #define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
- #define I915_BO_WAS_BOUND_BIT 6
-
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+ #define I915_BO_READONLY BIT(6)
+ #define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
+ #define I915_BO_PROTECTED BIT(8)
++#define I915_BO_WAS_BOUND_BIT 9
/**
* @mem_flags - Mutable placement-related flags
*
diff --cc drivers/gpu/drm/i915/gt/intel_gt_types.h
index 9fbcbcc6c35d,14216cc471b1..f20687796490
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@@ -72,8 -73,8 +73,10 @@@ struct intel_gt
struct intel_uc uc;
+ struct mutex tlb_invalidate_lock;
+
+ struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --cc drivers/gpu/drm/i915/intel_uncore.c
index de8d0558389c,e072054adac5..e21c779cb487
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -734,11 -739,7 +740,11 @@@ static void __intel_uncore_forcewake_pu
continue;
}
- fw_domains_put(uncore, domain->mask);
+ if (delayed &&
+ !(domain->uncore->fw_domains_timer & domain->mask))
+ fw_domain_arm_timer(domain);
+ else
- uncore->funcs.force_wake_put(uncore, domain->mask);
++ fw_domains_put(uncore, domain->mask);
}
}
@@@ -759,20 -760,7 +765,20 @@@ void intel_uncore_forcewake_put(struct
return;
spin_lock_irqsave(&uncore->lock, irqflags);
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
+ spin_unlock_irqrestore(&uncore->lock, irqflags);
+}
+
+void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,
+ enum forcewake_domains fw_domains)
+{
+ unsigned long irqflags;
+
- if (!uncore->funcs.force_wake_put)
++ if (!uncore->fw_get_funcs)
+ return;
+
+ spin_lock_irqsave(&uncore->lock, irqflags);
+ __intel_uncore_forcewake_put(uncore, fw_domains, true);
spin_unlock_irqrestore(&uncore->lock, irqflags);
}
@@@ -811,10 -799,10 +817,10 @@@ void intel_uncore_forcewake_put__locked
{
lockdep_assert_held(&uncore->lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
- __intel_uncore_forcewake_put(uncore, fw_domains);
+ __intel_uncore_forcewake_put(uncore, fw_domains, false);
}
void assert_forcewakes_inactive(struct intel_uncore *uncore)
Commit list:
commit ce7e75c7ef1bf8ea3d947da8c674d2f40fd7d734
commit bc33e71f00a7491810cac9e1335ca97e889d5620
commit 39afa4104bedf214e5779ef20655665723ad48cd
commit f9d56cd64ef3186d6ce072751f7f44dcd189f6bc
commit 0bb50de156d8280e53884adf1d5a04d6108f90e7
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commit df5bc0aa7ff6e2e14cb75182b4eda20253c711d4
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 17:14:01 +00:00
|
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|
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2016-10-12 09:05:18 +00:00
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# Post-mortem debug and GPU hang state capture
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|
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i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
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2017-02-13 17:15:12 +00:00
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|
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i915-$(CONFIG_DRM_I915_SELFTEST) += \
|
Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
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commit 2ef8ea23942f4c2569930c34e7689a0cb1b232cc
commit 53c2ff8bcb06acd07e24a62e7f5a0247bd7c6f67
commit 772970620a839141835eaf2bc507d957b10adcca
commit 3e4c31e8f70251732529a10934355084c7fab0ac
commit a79f40cccd4644c32f6d5ae1ccf091a262e1dc57
commit 13047a092c6d3f23b7d684b5b3fe46b2b50423b9
commit 982f8ad666a1123028a077b6b009871a0dc9df26
commit 004d2719806fb8e355c1bccd538e82c04319d391
commit 74056092ff415e7e20ce2544689b32ee811c4f0b
commit 0db55f9a1bafbe3dac750ea669de9134922389b5
commit def0c3697287f6e85d5ac68b21302966c95474f9
commit 595cb5e0b832a3e100cbbdefef797b0c27bf725a
commit ee71fb6c4d99c51f2d82a32c503c872b7e40e7f7
commit fcf918ffd3b35e288097036c04af7446b2c6f2f1
commit 9761ffb8f1090289b908590039e2c363cc35cf45
commit 6e6f96630805874fa80b0067e1a57aafc06225f6
commit 61b1d445f3bfe4c3ba4335ceeb7e8ba688fd31e2
commit defbbcd99fa68cb7feed453662048baa87e9a441
commit 3f4e54bd312d3dafb59daf2b97ffa08abebe60f5
commit 54149d13f369e1ab02f36b91feee02069184c1d8
commit ad76744b041d8c87ef1c9adbb04fb7eaa20a179e
commit 19928833e8f8fa5ee687c451437ce674f19d6c09
commit 79516af3497a5b89acb09f4a644f61d6c69e5f16
commit 9a4aa3a2f1606a03c220b21049baa4a2b6169626
commit 946ca97e2ea3682e434ae1d0958a4565fa10b6bc
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
|
|
|
gem/selftests/i915_gem_client_blt.o \
|
2019-05-28 09:29:49 +00:00
|
|
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gem/selftests/igt_gem_utils.o \
|
Merge DRM changes from upstream v5.14..v5.15
This commit was generated using:
rhdrm-merge-drm v5.15 2043115
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2043115
Conflicts:
Makefile
drivers/gpu/drm/drm_gem_atomic_helper.c
drivers/gpu/drm/drm_gem_framebuffer_helper.c
drivers/gpu/drm/gud/gud_pipe.c
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
include/drm/drm_gem_atomic_helper.h
include/drm/drm_gem_framebuffer_helper.h
Conflict resolution:
diff --cc drivers/dma-buf/dma-buf.c
index 09d4d01a0ae1,63d32261b63f..6c2b5ea828a6
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@@ -992,10 -1010,9 +1010,9 @@@ struct sg_table *dma_buf_map_attachment
}
}
#endif /* CONFIG_DMA_API_DEBUG */
-
return sg_table;
}
-EXPORT_SYMBOL_GPL(dma_buf_map_attachment);
+EXPORT_SYMBOL_NS_GPL(dma_buf_map_attachment, DMA_BUF);
/**
* dma_buf_unmap_attachment - unmaps and decreases usecount of the buffer;might
diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index e49c8dfb749b,96a8fd0ca1df..5024cd5e23b4
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@@ -2012,15 -2011,9 +2018,15 @@@ int amdgpu_ras_recovery_init(struct amd
goto free;
if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
- adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs);
+ adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
}
+#ifdef CONFIG_X86_MCE_AMD
+ if ((adev->asic_type == CHIP_ALDEBARAN) &&
+ (adev->gmc.xgmi.connected_to_cpu))
+ amdgpu_register_bad_pages_mca_notifier();
+#endif
+
return 0;
free:
diff --cc drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0bc58c57a65e,2471f36aaff3..3012cbe5b0b7
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@@ -185,24 -290,138 +290,139 @@@ struct drm_i915_gem_object
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
- #define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
- #define I915_BO_ALLOC_CPU_CLEAR BIT(3)
+ #define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+ #define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
- I915_BO_ALLOC_CPU_CLEAR)
+ I915_BO_ALLOC_CPU_CLEAR | \
+ I915_BO_ALLOC_USER)
#define I915_BO_READONLY BIT(4)
#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+#define I915_BO_WAS_BOUND_BIT 6
- /*
- * Is the object to be mapped as read-only to the GPU
- * Only honoured if hardware has relevant pte bit
+ /**
+ * @mem_flags - Mutable placement-related flags
+ *
+ * These are flags that indicate specifics of the memory region
+ * the object is currently in. As such they are only stable
+ * either under the object lock or if the object is pinned.
+ */
+ unsigned int mem_flags;
+ #define I915_BO_FLAG_STRUCT_PAGE BIT(0) /* Object backed by struct pages */
+ #define I915_BO_FLAG_IOMEM BIT(1) /* Object backed by IO memory */
+ /**
+ * @cache_level: The desired GTT caching level.
+ *
+ * See enum i915_cache_level for possible values, along with what
+ * each does.
*/
unsigned int cache_level:3;
- unsigned int cache_coherent:2;
+ /**
+ * @cache_coherent:
+ *
+ * Track whether the pages are coherent with the GPU if reading or
+ * writing through the CPU caches. The largely depends on the
+ * @cache_level setting.
+ *
+ * On platforms which don't have the shared LLC(HAS_SNOOP), like on Atom
+ * platforms, coherency must be explicitly requested with some special
+ * GTT caching bits(see enum i915_cache_level). When enabling coherency
+ * it does come at a performance and power cost on such platforms. On
+ * the flip side the kernel does not need to manually flush any buffers
+ * which need to be coherent with the GPU, if the object is not coherent
+ * i.e @cache_coherent is zero.
+ *
+ * On platforms that share the LLC with the CPU(HAS_LLC), all GT memory
+ * access will automatically snoop the CPU caches(even with CACHE_NONE).
+ * The one exception is when dealing with the display engine, like with
+ * scanout surfaces. To handle this the kernel will always flush the
+ * surface out of the CPU caches when preparing it for scanout. Also
+ * note that since scanout surfaces are only ever read by the display
+ * engine we only need to care about flushing any writes through the CPU
+ * cache, reads on the other hand will always be coherent.
+ *
+ * Something strange here is why @cache_coherent is not a simple
+ * boolean, i.e coherent vs non-coherent. The reasoning for this is back
+ * to the display engine not being fully coherent. As a result scanout
+ * surfaces will either be marked as I915_CACHE_NONE or I915_CACHE_WT.
+ * In the case of seeing I915_CACHE_NONE the kernel makes the assumption
+ * that this is likely a scanout surface, and will set @cache_coherent
+ * as only I915_BO_CACHE_COHERENT_FOR_READ, on platforms with the shared
+ * LLC. The kernel uses this to always flush writes through the CPU
+ * cache as early as possible, where it can, in effect keeping
+ * @cache_dirty clean, so we can potentially avoid stalling when
+ * flushing the surface just before doing the scanout. This does mean
+ * we might unnecessarily flush non-scanout objects in some places, but
+ * the default assumption is that all normal objects should be using
+ * I915_CACHE_LLC, at least on platforms with the shared LLC.
+ *
+ * Supported values:
+ *
+ * I915_BO_CACHE_COHERENT_FOR_READ:
+ *
+ * On shared LLC platforms, we use this for special scanout surfaces,
+ * where the display engine is not coherent with the CPU cache. As such
+ * we need to ensure we flush any writes before doing the scanout. As an
+ * optimisation we try to flush any writes as early as possible to avoid
+ * stalling later.
+ *
+ * Thus for scanout surfaces using I915_CACHE_NONE, on shared LLC
+ * platforms, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ
+ *
+ * While for normal objects that are fully coherent, including special
+ * scanout surfaces marked as I915_CACHE_WT, we use:
+ *
+ * cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ |
+ * I915_BO_CACHE_COHERENT_FOR_WRITE
+ *
+ * And then for objects that are not coherent at all we use:
+ *
+ * cache_coherent = 0
+ *
+ * I915_BO_CACHE_COHERENT_FOR_WRITE:
+ *
+ * When writing through the CPU cache, the GPU is still coherent. Note
+ * that this also implies I915_BO_CACHE_COHERENT_FOR_READ.
+ */
#define I915_BO_CACHE_COHERENT_FOR_READ BIT(0)
#define I915_BO_CACHE_COHERENT_FOR_WRITE BIT(1)
+ unsigned int cache_coherent:2;
+
+ /**
+ * @cache_dirty:
+ *
+ * Track if we are we dirty with writes through the CPU cache for this
+ * object. As a result reading directly from main memory might yield
+ * stale data.
+ *
+ * This also ties into whether the kernel is tracking the object as
+ * coherent with the GPU, as per @cache_coherent, as it determines if
+ * flushing might be needed at various points.
+ *
+ * Another part of @cache_dirty is managing flushing when first
+ * acquiring the pages for system memory, at this point the pages are
+ * considered foreign, so the default assumption is that the cache is
+ * dirty, for example the page zeroing done by the kernel might leave
+ * writes though the CPU cache, or swapping-in, while the actual data in
+ * main memory is potentially stale. Note that this is a potential
+ * security issue when dealing with userspace objects and zeroing. Now,
+ * whether we actually need apply the big sledgehammer of flushing all
+ * the pages on acquire depends on if @cache_coherent is marked as
+ * I915_BO_CACHE_COHERENT_FOR_WRITE, i.e that the GPU will be coherent
+ * for both reads and writes though the CPU cache.
+ *
+ * Note that on shared LLC platforms we still apply the heavy flush for
+ * I915_CACHE_NONE objects, under the assumption that this is going to
+ * be used for scanout.
+ *
+ * Update: On some hardware there is now also the 'Bypass LLC' MOCS
+ * entry, which defeats our @cache_coherent tracking, since userspace
+ * can freely bypass the CPU cache when touching the pages with the GPU,
+ * where the kernel is completely unaware. On such platform we need
+ * apply the sledgehammer-on-acquire regardless of the @cache_coherent.
+ */
unsigned int cache_dirty:1;
/**
diff --cc drivers/gpu/drm/nouveau/nouveau_drm.c
index b9aaf640f372,6109cd9e3399..e7efd9ede8e4
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@@ -815,9 -796,8 +817,8 @@@ nouveau_drm_device_remove(struct drm_de
struct nvkm_client *client;
struct nvkm_device *device;
- drm_dev_unregister(dev);
+ drm_dev_unplug(dev);
- dev->irq_enabled = false;
client = nvxx_client(&drm->client.base);
device = nvkm_device_find(client->device);
diff --cc drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
index f9d399ea628d,e50fb82a3030..2aceac7856e2
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c
@@@ -28,9 -28,10 +28,10 @@@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
-#include <linux/mem_encrypt.h>
+#include <linux/cc_platform.h>
#include <asm/hypervisor.h>
+ #include <drm/drm_ioctl.h>
#include "vmwgfx_drv.h"
#include "vmwgfx_msg_x86.h"
@@@ -153,8 -160,9 +160,9 @@@ static unsigned long vmw_port_hb_out(st
unsigned long msg_len = strlen(msg);
/* HB port can't access encrypted memory. */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_high;
+ u32 channel_id = (channel->channel_id << 16);
si = (uintptr_t) msg;
di = channel->cookie_low;
@@@ -208,8 -216,9 +216,9 @@@ static unsigned long vmw_port_hb_in(str
unsigned long si, di, eax, ebx, ecx, edx;
/* HB port can't access encrypted memory */
- if (hb && !mem_encrypt_active()) {
+ if (hb && !cc_platform_has(CC_ATTR_MEM_ENCRYPT)) {
unsigned long bp = channel->cookie_low;
+ u32 channel_id = (channel->channel_id << 16);
si = channel->cookie_high;
di = (uintptr_t) reply;
Commit list:
commit 241a9e233e7cf1001d09426c9fc520768f8961bf
commit 4154fa0e2688118ba3dbc67aa834435463f9ea68
commit 3faea9939a3d1eb5a40f3f6100c24792865b6445
commit 46e745a8edc8c2a2fe4fdc491d7e39598e104441
commit 3b51c2bb6f5f3f8a88fe9f4ab62e38496b2d200b
commit ade673bb2ba496a66250c5c2006c502c3d734ea2
commit 17917ff62443414569ea76e151e7a7ef44812264
commit 837f93247634b12e5eebb3d707405b701a4f3479
commit 867cf9cd73c3d31666e4b480aa4f52828d25ac94
commit 6eca310e8924ab98c73b81dfd39e7dd553ceddfd
commit 16c243e99d335e1ef3059871897119affc98b493
commit d098775ed44021293b1962dea61efb19297b8d02
commit 86441fa29e57940eeb00f35fefb1853c1fbe67bb
commit a3af0140663dc335e5c18277a61bb99bfcb60694
commit 26594678d00f94c62f2e43162bd6d10fd0b74917
commit a3a5f9d0fb15da90820254ba735491887cc12099
commit 213d5092776345ad5d6e2efa36a6bfbe9899e8b3
commit 2e53d7c1147a2751e959c53970c61b7ae33e1ecb
commit f425821b946847282708121600fffc20344183a0
commit cf3e3e86d77970211e0983130e896ae242601003
commit 0ea02bb8bc7a16446169bfae46938ea3a195db5d
commit aeb33699fc2c97994de0e9acb74d0fd319380614
commit 74c06c282ae63560fcf4073d1564f054d96285ec
commit cc5a3fc041f0104d97ac61b0423ec533d7a93214
commit a1e3667a9835e15101cf27731219fe2581dbf572
commit e0bbcc6233f7c664474287aaed8dcffd935a1869
commit a70e558c151043ce46a5e5999f4310e0b3551f57
commit 4c1b3d94bf632c1420a5d4108199f55a5655831d
commit d92223ead97cd697abe76c5b7a78160d6910a90d
commit 7a7a933edd6c3a6d5d64e08093f2d564104cefcd
commit a12be0277316ed923411c9c80b2899ee74d2b033
commit 74231041d14030f1ae6582b9233bfe782ac23e33
commit f674a218c610bea97c106ca8179b55b2a7a7528a
commit 8d9a8d9bd5034a88afef470664918aa914b1c3dc
commit b7d0949f6ce691131323fafabd48bf2f5074ae8d
commit baee602e5c0d00a7233fdb2b2bfd3ace4b5b8f29
commit 352a81b71ea0a3ce8f929aa60afe369d738a0c6a
commit 00f4471e42c871524c68ef1413d2fe53ce1d0a1b
commit bfd616ff9a2602ec66414438c3f9871a49fa1e16
commit ade0e676ecdcdd3428210684c76493722e09a791
commit c649432e86ca677d8762c5764a2832509ca8d449
commit 0e9d217b79371d726e53d4a1beef1743952383b7
commit 35c6367f516090a3086d37e7023b08608d555aba
commit b4b9731b02c3ce859d85dec17ec63f4bf3140bf4
commit 9c61e789546810ee63708568737cb990d2b86605
commit 440d0f12b52a920f4c78376b3ce7039ba59244c5
commit 413f52f146f148827dd7a61ca599143f60ae3e3c
commit c2a61865baa45b5d1dfc3e83da50bcd51d518786
commit b91e3c830f00814c0f5c2e3afaf63b48d8ccb9d3
commit aae74ff9caa8de9a45ae2e46068c417817392a26
commit bdb8d06dfefd666d5981d884b535b04105869fcc
commit 8c209f42cb3a209c366bae2956c98d8ed0514773
commit ad5fd900a69b1ae24e6b22506dea637b6bbbdb55
commit 544021e3f2aa3c4c6c5aabc58907e8bab69b3762
commit c865204e84a1a5c35e055b45971524efe4616e31
commit 88be9a0a06b73ecd85a688a7c174c941e9692e92
commit f701b16d4cc535d24facdfdd21dc97a3691e5576
commit 38f28c0695c0413b701f67105bff2573c667492a
commit beb6a22911ff6f7e933670b43e4bda5be56bd8f9
commit 687c7d0fcf8014a006416d7dc7474a101a85bf00
commit d53ec322dc7de32a59bf1c2a56b93e90fc2f1c28
commit 13c2ceb6addb6b14468e09b75832c98909eed8e7
commit 151ec347b06a2fb6ecd2922475dca71a7af827a5
commit ebc9ac7c3dfe85e7e29af896c7fd1095129fd72c
commit c2aaa37dc18fb7191a0fd829a7a943f61c2821de
commit 46e4e5ffbc2af8a6f7935648ab286902b406a01d
commit 9f808288ba88ac2a9582118343d4ca7e3d95dd43
commit dc2408d86e5ae88ec981e1315f95b7d4d15169fe
commit a6c5b891252143ee9bc02f649282905954d6705c
commit 1c4dbe056dab0b7c2a2f42f4d393cc7b9bdb98ad
commit 5c43ec5d538a5fa1736d298e63a3f8ac03009eea
commit 3b86eb82dc2c9989ca6e53cb597a2a1390c64d12
commit 0dcd6fdf3b4be20995d8d35198ac252833613ab9
commit 3607e1e9ba7553e39b175fa14d10a48677083607
commit b4ef95309110122e05b0d17310b80a0abde881d9
commit cf586021642d8017cde111b7dd1ba86224e9da51
commit 563baae1875cbcac332086cca325cf55a0532b9e
commit 94ce0d65076cda511da843ae1893c819948a215a
commit 50331a7b50741035cc9335f863939d638b225e71
commit 57143f2e5b41f3e51b13d3c358e29a932334110d
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Signed-off-by: Karol Herbst <kherbst@redhat.com>
2022-05-23 13:49:08 +00:00
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selftests/intel_scheduler_helpers.o \
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2017-02-13 17:15:12 +00:00
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selftests/i915_random.o \
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2018-05-05 09:10:13 +00:00
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selftests/i915_selftest.o \
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2020-01-03 10:45:15 +00:00
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selftests/igt_atomic.o \
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2018-11-30 08:02:53 +00:00
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selftests/igt_flush_test.o \
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2019-01-21 22:20:47 +00:00
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2019-11-07 18:06:00 +00:00
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2018-12-03 12:50:11 +00:00
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2020-04-17 15:20:17 +00:00
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selftests/librapl.o
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2016-10-12 09:05:18 +00:00
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2015-02-10 11:05:47 +00:00
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# virtual gpu code
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i915-y += i915_vgpu.o
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2022-08-02 20:41:59 +00:00
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i915-$(CONFIG_DRM_I915_GVT) += \
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intel_gvt.o \
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intel_gvt_mmio_table.o
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drm/i915: gvt: Introduce the basic architecture of GVT-g
This patch introduces the very basic framework of GVT-g device model,
includes basic prototypes, definitions, initialization.
v12:
- Call intel_gvt_init() in driver early initialization stage. (Chris)
v8:
- Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
v7:
- Refine the URL link in Kconfig. (Joonas)
- Refine the introduction of GVT-g host support in Kconfig. (Joonas)
- Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
- Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
- Remove {alloc, free}_gvt_device()
- Rename intel_gvt_{create, destroy}_gvt_device()
- Expost intel_gvt_init_host()
- Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
v6:
- Refine introduction in Kconfig. (Chris)
- The exposed API functions will take struct intel_gvt * instead of
void *. (Chris/Tvrtko)
- Remove most memebers of strct intel_gvt_device_info. Will add them
in the device model patches.(Chris)
- Remove gvt_info() and gvt_err() in debug.h. (Chris)
- Move GVT kernel parameter into i915_params. (Chris)
- Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
- Remove the redundant struct i915_gvt *, as the functions in i915
will directly take struct intel_gvt *.
- Add more comments for reviewer.
v5:
Take Tvrtko's comments:
- Fix the misspelled words in Kconfig
- Let functions take drm_i915_private * instead of struct drm_device *
- Remove redundant prints/local varible initialization
v3:
Take Joonas' comments:
- Change file name i915_gvt.* to intel_gvt.*
- Move GVT kernel parameter into intel_gvt.c
- Remove redundant debug macros
- Change error handling style
- Add introductions for some stub functions
- Introduce drm/i915_gvt.h.
Take Kevin's comments:
- Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
v2:
- Introduce i915_gvt.c.
It's necessary to introduce the stubs between i915 driver and GVT-g host,
as GVT-g components is configurable in kernel config. When disabled, the
stubs here do nothing.
Take Joonas' comments:
- Replace boolean return value with int.
- Replace customized info/warn/debug macros with DRM macros.
- Document all non-static functions like i915.
- Remove empty and unused functions.
- Replace magic number with marcos.
- Set GVT-g in kernel config to "n" by default.
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.com
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-16 12:07:00 +00:00
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include $(src)/gvt/Makefile
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2016-08-19 15:54:28 +00:00
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obj-$(CONFIG_DRM_I915) += i915.o
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2022-08-02 20:42:22 +00:00
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obj-$(CONFIG_DRM_I915_GVT_KVMGT) += kvmgt.o
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2019-12-19 15:56:52 +00:00
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# header test
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# exclude some broken headers from the test coverage
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no-header-test := \
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2020-12-08 10:29:14 +00:00
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display/intel_vbt_defs.h
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2019-12-19 15:56:52 +00:00
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2021-01-20 06:23:51 +00:00
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always-$(CONFIG_DRM_I915_WERROR) += \
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2019-12-19 15:56:52 +00:00
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$(patsubst %.h,%.hdrtest, $(filter-out $(no-header-test), \
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$(shell cd $(srctree)/$(src) && find * -name '*.h')))
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quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)
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2020-02-21 10:54:14 +00:00
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cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@
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2019-12-19 15:56:52 +00:00
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$(obj)/%.hdrtest: $(src)/%.h FORCE
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$(call if_changed_dep,hdrtest)
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