wifi: rtw88: Add some definitions for RTL8814AU
JIRA: https://issues.redhat.com/browse/RHEL-89168 commit 679ec431477cdb68d1cab068c008da0de7f842ef Author: Bitterblue Smith <rtl8821cerfe2@gmail.com> Date: Fri Mar 7 02:22:17 2025 +0200 wifi: rtw88: Add some definitions for RTL8814AU Add various register definitions which will be used by the new driver. Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com> Acked-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/1dcb5abb-26f8-4db5-be36-057de56465e5@gmail.com Signed-off-by: Jose Ignacio Tornos Martinez <jtornosm@redhat.com>
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Jose Ignacio Tornos Martinez
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df38ecb62f
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@ -8,6 +8,7 @@
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#define REG_SYS_FUNC_EN 0x0002
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#define BIT_FEN_EN_25_1 BIT(13)
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#define BIT_FEN_ELDR BIT(12)
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#define BIT_FEN_PCIEA BIT(6)
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#define BIT_FEN_CPUEN BIT(2)
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#define BIT_FEN_USBA BIT(2)
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#define BIT_FEN_BB_GLB_RST BIT(1)
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@ -39,6 +40,9 @@
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#define BIT_RF_RSTB BIT(1)
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#define BIT_RF_EN BIT(0)
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#define REG_RF_CTRL1 0x0020
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#define REG_RF_CTRL2 0x0021
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#define REG_AFE_CTRL1 0x0024
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#define BIT_MAC_CLK_SEL (BIT(20) | BIT(21))
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#define REG_EFUSE_CTRL 0x0030
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@ -73,6 +77,8 @@
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#define BIT_BT_PTA_EN BIT(5)
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#define BIT_WLRFE_4_5_EN BIT(2)
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#define REG_GPIO_PIN_CTRL 0x0044
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#define REG_LED_CFG 0x004C
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#define BIT_LNAON_SEL_EN BIT(26)
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#define BIT_PAPE_SEL_EN BIT(25)
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@ -110,6 +116,7 @@
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#define BIT_SDIO_PAD_E5 BIT(18)
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#define REG_RF_B_CTRL 0x76
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#define REG_RF_CTRL3 0x0076
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#define REG_AFE_CTRL_4 0x0078
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#define BIT_CK320M_AFE_EN BIT(4)
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@ -603,15 +610,25 @@
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#define REG_CCA2ND 0x0838
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#define REG_L1PKTH 0x0848
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#define REG_CLKTRK 0x0860
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#define REG_CSI_MASK_SETTING1 0x0874
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#define REG_NBI_SETTING 0x087c
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#define BIT_NBI_ENABLE BIT(13)
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#define REG_CSI_FIX_MASK0 0x0880
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#define REG_CSI_FIX_MASK1 0x0884
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#define REG_CSI_FIX_MASK6 0x0898
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#define REG_CSI_FIX_MASK7 0x089c
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#define REG_ADCCLK 0x08AC
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#define REG_HSSI_READ 0x08B0
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#define REG_FPGA0_XCD_RF_PARA 0x08B4
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#define REG_RX_MCS_LIMIT 0x08BC
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#define REG_ADC160 0x08C4
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#define REG_DBGSEL 0x08fc
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#define REG_ANTSEL_SW 0x0900
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#define REG_DAC_RSTB 0x090c
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#define REG_PSD 0x0910
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#define BIT_PSD_INI GENMASK(23, 22)
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#define REG_SINGLE_TONE_CONT_TX 0x0914
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#define REG_AGC_TABLE 0x0958
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#define REG_RFE_CTRL_E 0x0974
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#define REG_2ND_CCA_CTRL 0x0976
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#define REG_IQK_COM00 0x0978
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@ -621,10 +638,18 @@
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#define REG_FAS 0x09a4
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#define REG_RXSB 0x0a00
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#define BIT_RXSB_ANA_DIV BIT(15)
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#define REG_CCK_RX 0x0a04
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#define REG_CCK_PD_TH 0x0a0a
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#define REG_CCK0_FAREPORT 0xa2c
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#define REG_PRECTRL 0x0a14
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#define BIT_DIS_CO_PATHSEL BIT(7)
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#define BIT_IQ_WGT GENMASK(9, 8)
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#define REG_CCA_MF 0x0a20
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#define BIT_MBC_WIN GENMASK(5, 4)
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#define REG_CCK0_TX_FILTER1 0x0a20
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#define REG_CCK0_TX_FILTER2 0x0a24
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#define REG_CCK0_DEBUG_PORT 0x0a28
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#define REG_CCK0_FAREPORT 0x0a2c
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#define BIT_CCK0_2RX BIT(18)
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#define BIT_CCK0_MRC BIT(22)
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#define REG_FA_CCK 0x0a5c
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@ -643,10 +668,18 @@
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#define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)
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#define DIS_DPD_RATEALL GENMASK(9, 0)
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#define REG_CCA 0x0a70
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#define BIT_CCA_CO BIT(7)
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#define REG_ANTSEL 0x0a74
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#define BIT_ANT_BYCO BIT(8)
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#define REG_CCKTX 0x0a84
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#define BIT_CMB_CCA_2R BIT(28)
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#define REG_CNTRST 0x0b58
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#define REG_3WIRE_SWA 0x0c00
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#define REG_RX_IQC_AB_A 0x0c10
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#define REG_RX_IQC_CD_A 0x0c14
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#define REG_TXSCALE_A 0x0c1c
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#define BB_SWING_MASK GENMASK(31, 21)
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#define REG_TX_AGC_A_CCK_11_CCK_1 0xc20
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@ -674,7 +707,7 @@
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#define REG_LSSI_WRITE_A 0x0c90
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#define REG_PREDISTA 0x0c90
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#define REG_TXAGCIDX 0x0c94
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#define REG_TX_AGC_A 0x0c94
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#define REG_RFE_PINMUX_A 0x0cb0
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#define REG_RFE_INV_A 0x0cb4
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#define REG_RFE_CTRL8 0x0cb4
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@ -683,6 +716,7 @@
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#define DPDT_CTRL_PIN 0x77
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#define RFE_INV_MASK 0x3ff00000
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#define REG_RFECTL_A 0x0cb8
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#define REG_RFE_INV0 0x0cbc
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#define REG_RFE_INV8 0x0cbd
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#define BIT_MASK_RFE_INV89 GENMASK(1, 0)
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#define REG_RFE_INV16 0x0cbe
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@ -703,6 +737,7 @@
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#define REG_3WIRE_SWB 0x0e00
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#define REG_RX_IQC_AB_B 0x0e10
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#define REG_RX_IQC_CD_B 0x0e14
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#define REG_TXSCALE_B 0x0e1c
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#define REG_TX_AGC_B_CCK_11_CCK_1 0xe20
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#define REG_TX_AGC_B_OFDM18_OFDM6 0xe24
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@ -729,6 +764,7 @@
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#define REG_LSSI_WRITE_B 0x0e90
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#define REG_PREDISTB 0x0e90
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#define REG_INIDLYB 0x0e94
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#define REG_TX_AGC_B 0x0e94
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#define REG_RFE_PINMUX_B 0x0eb0
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#define REG_RFE_INV_B 0x0eb4
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#define REG_RFECTL_B 0x0eb8
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@ -744,8 +780,11 @@
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#define REG_CRC_HT 0x0f10
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#define REG_CRC_OFDM 0x0f14
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#define REG_FA_OFDM 0x0f48
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#define REG_DBGRPT 0x0fa0
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#define REG_CCA_CCK 0x0fcc
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#define REG_SYS_CFG3_8814A 0x1000
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#define REG_ANAPARSW_MAC_0 0x1010
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#define BIT_CF_L_V2 GENMASK(29, 28)
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@ -863,9 +902,27 @@
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#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
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#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
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#define REG_RX_IQC_AB_C 0x1810
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#define REG_RX_IQC_CD_C 0x1814
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#define REG_TXSCALE_C 0x181c
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#define REG_CK_MONHC 0x185c
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#define REG_AFE_PWR1_C 0x1860
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#define REG_IGN_GNT_BT1 0x1860
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#define REG_TX_AGC_C 0x1894
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#define REG_RFE_PINMUX_C 0x18b4
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#define REG_RFESEL_CTRL 0x1990
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#define REG_AGC_TBL 0x1998
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#define REG_RX_IQC_AB_D 0x1a10
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#define REG_RX_IQC_CD_D 0x1a14
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#define REG_TXSCALE_D 0x1a1c
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#define REG_CK_MONHD 0x1a5c
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#define REG_AFE_PWR1_D 0x1a60
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#define REG_TX_AGC_D 0x1a94
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#define REG_RFE_PINMUX_D 0x1ab4
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#define REG_RFE_INVSEL_D 0x1abc
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#define BIT_RFE_SELSW0_D GENMASK(27, 20)
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#define REG_NOMASK_TXBT 0x1ca7
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#define REG_ANAPAR 0x1c30
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@ -906,6 +963,7 @@
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#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
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#define RF18_CHANNEL_MASK (MASKBYTE0)
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#define RF18_RFSI_MASK (BIT(18) | BIT(17))
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#define RF_RCK1_V1 0x1c
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#define RF_RCK 0x1d
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#define RF_MODE_TABLE_ADDR 0x30
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#define RF_MODE_TABLE_DATA0 0x31
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