144 lines
5.6 KiB
Rust
144 lines
5.6 KiB
Rust
// 导出 ahci 相关的 module
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pub mod ahci_inode;
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pub mod ahcidisk;
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pub mod hba;
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use crate::arch::MMArch;
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use crate::driver::base::block::manager::block_dev_manager;
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use crate::driver::block::cache::cached_block_device::BlockCache;
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use crate::driver::disk::ahci::ahcidisk::LockedAhciDisk;
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use crate::driver::pci::pci::{
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get_pci_device_structure_mut, PciDeviceStructure, PCI_DEVICE_LINKEDLIST,
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};
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use crate::driver::disk::ahci::{
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hba::HbaMem,
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hba::{HbaPort, HbaPortType},
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};
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use crate::libs::rwlock::RwLockWriteGuard;
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use crate::libs::spinlock::{SpinLock, SpinLockGuard};
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use crate::mm::{MemoryManagementArch, VirtAddr};
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use alloc::{boxed::Box, collections::LinkedList, vec::Vec};
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use core::sync::atomic::compiler_fence;
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use log::debug;
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use system_error::SystemError;
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// 仅module内可见 全局数据区 hbr_port, disks
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static LOCKED_HBA_MEM_LIST: SpinLock<Vec<&mut HbaMem>> = SpinLock::new(Vec::new());
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const AHCI_CLASS: u8 = 0x1;
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const AHCI_SUBCLASS: u8 = 0x6;
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/* TFES - Task File Error Status */
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#[allow(non_upper_case_globals)]
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pub const HBA_PxIS_TFES: u32 = 1 << 30;
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/// @brief 寻找所有的ahci设备
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/// @param list 链表的写锁
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/// @return Result<Vec<&'a mut Box<dyn PciDeviceStructure>>, SystemError> 成功则返回包含所有ahci设备结构体的可变引用的链表，失败则返回err
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fn ahci_device_search<'a>(
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list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>,
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) -> Result<Vec<&'a mut Box<dyn PciDeviceStructure>>, SystemError> {
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let result = get_pci_device_structure_mut(list, AHCI_CLASS, AHCI_SUBCLASS);
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if result.is_empty() {
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return Err(SystemError::ENODEV);
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}
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return Ok(result);
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}
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/// @brief: 初始化 ahci
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pub fn ahci_init() -> Result<(), SystemError> {
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let mut list = PCI_DEVICE_LINKEDLIST.write();
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let ahci_device = ahci_device_search(&mut list)?;
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for device in ahci_device {
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let standard_device = device.as_standard_device_mut().unwrap();
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standard_device.bar_ioremap();
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// 对于每一个ahci控制器分配一块空间
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let ahci_port_base_vaddr =
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Box::leak(Box::new([0u8; (1 << 20) as usize])) as *mut u8 as usize;
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let virtaddr = standard_device
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.bar()
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.ok_or(SystemError::EACCES)?
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.get_bar(5)
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.or(Err(SystemError::EACCES))?
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.virtual_address()
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.unwrap();
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// 最后把这个引用列表放入到全局列表
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let mut hba_mem_list = LOCKED_HBA_MEM_LIST.lock();
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//这里两次unsafe转引用规避rust只能有一个可变引用的检查，提高运行速度
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let hba_mem = unsafe { (virtaddr.data() as *mut HbaMem).as_mut().unwrap() };
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hba_mem_list.push(unsafe { (virtaddr.data() as *mut HbaMem).as_mut().unwrap() });
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let pi = volatile_read!(hba_mem.pi);
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let hba_mem_index = hba_mem_list.len() - 1;
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drop(hba_mem_list);
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// 初始化所有的port
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for j in 0..32 {
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if (pi >> j) & 1 > 0 {
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let hba_mem_list = LOCKED_HBA_MEM_LIST.lock();
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let hba_mem_port = &mut hba_mem.ports[j];
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let tp = hba_mem_port.check_type();
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match tp {
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HbaPortType::None => {
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debug!("<ahci_rust_init> Find a None type Disk.");
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}
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HbaPortType::Unknown(err) => {
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debug!("<ahci_rust_init> Find a Unknown({:?}) type Disk.", err);
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}
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_ => {
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debug!("<ahci_rust_init> Find a {:?} type Disk.", tp);
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// 计算地址
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let fb = unsafe {
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MMArch::virt_2_phys(VirtAddr::new(
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ahci_port_base_vaddr + (32 << 10) + (j << 8),
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))
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}
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.unwrap()
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.data();
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let clb = unsafe {
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MMArch::virt_2_phys(VirtAddr::new(ahci_port_base_vaddr + (j << 10)))
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.unwrap()
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.data()
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};
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let ctbas = (0..32)
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.map(|x| unsafe {
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MMArch::virt_2_phys(VirtAddr::new(
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ahci_port_base_vaddr + (40 << 10) + (j << 13) + (x << 8),
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))
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.unwrap()
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.data() as u64
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})
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.collect::<Vec<_>>();
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// 初始化 port
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hba_mem_port.init(clb as u64, fb as u64, &ctbas);
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drop(hba_mem_list);
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compiler_fence(core::sync::atomic::Ordering::SeqCst);
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let ahci_disk = LockedAhciDisk::new(hba_mem_index as u8, j as u8)?;
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block_dev_manager()
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.register(ahci_disk)
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.expect("register ahci disk failed");
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debug!("start register ahci device");
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}
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}
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}
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}
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BlockCache::init();
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}
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compiler_fence(core::sync::atomic::Ordering::SeqCst);
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return Ok(());
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}
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/// @brief: 通过 ctrl_num 和 port_num 获取 port
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fn _port(ctrl_num: u8, port_num: u8) -> &'static mut HbaPort {
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let list: SpinLockGuard<Vec<&mut HbaMem>> = LOCKED_HBA_MEM_LIST.lock();
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let port: &HbaPort = &list[ctrl_num as usize].ports[port_num as usize];
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return unsafe { (port as *const HbaPort as *mut HbaPort).as_mut().unwrap() };
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}
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