2024-01-03 03:22:36 +00:00
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// SPDX-License-Identifier: MPL-2.0
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2024-06-27 09:47:20 +00:00
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//! PCI device common definitions or functions.
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2025-01-24 10:06:53 +00:00
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#![expect(dead_code)]
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2024-06-03 18:34:33 +00:00
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2023-07-23 10:31:43 +00:00
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use alloc::vec::Vec;
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use super::{
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capability::Capability,
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cfg_space::{AddrLen, Bar, Command, PciDeviceCommonCfgOffset, Status},
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2025-07-25 07:51:39 +00:00
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device_info::PciDeviceId,
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2023-07-23 10:31:43 +00:00
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};
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2025-08-13 01:30:31 +00:00
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use crate::device_info::PciDeviceLocation;
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2023-07-23 10:31:43 +00:00
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/// PCI common device, Contains a range of information and functions common to PCI devices.
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#[derive(Debug)]
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pub struct PciCommonDevice {
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device_id: PciDeviceId,
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location: PciDeviceLocation,
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bar_manager: BarManager,
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capabilities: Vec<Capability>,
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}
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impl PciCommonDevice {
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2024-06-27 09:47:20 +00:00
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/// PCI device ID
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2023-07-23 10:31:43 +00:00
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pub fn device_id(&self) -> &PciDeviceId {
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&self.device_id
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}
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2024-06-27 09:47:20 +00:00
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/// PCI device location
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2023-07-23 10:31:43 +00:00
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pub fn location(&self) -> &PciDeviceLocation {
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&self.location
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}
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2024-06-27 09:47:20 +00:00
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/// PCI Base Address Register (BAR) manager
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2023-07-23 10:31:43 +00:00
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pub fn bar_manager(&self) -> &BarManager {
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&self.bar_manager
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}
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2024-06-27 09:47:20 +00:00
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/// PCI capabilities
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2023-07-23 10:31:43 +00:00
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pub fn capabilities(&self) -> &Vec<Capability> {
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&self.capabilities
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}
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2024-06-27 09:47:20 +00:00
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/// Gets the PCI Command
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2023-07-23 10:31:43 +00:00
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pub fn command(&self) -> Command {
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Command::from_bits_truncate(
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self.location
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.read16(PciDeviceCommonCfgOffset::Command as u16),
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)
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}
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2024-06-27 09:47:20 +00:00
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/// Sets the PCI Command
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2023-07-23 10:31:43 +00:00
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pub fn set_command(&self, command: Command) {
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self.location
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.write16(PciDeviceCommonCfgOffset::Command as u16, command.bits())
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}
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2024-06-27 09:47:20 +00:00
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/// Gets the PCI status
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pub fn status(&self) -> Status {
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Status::from_bits_truncate(
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self.location
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.read16(PciDeviceCommonCfgOffset::Status as u16),
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)
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}
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pub(super) fn new(location: PciDeviceLocation) -> Option<Self> {
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if location.read16(0) == 0xFFFF {
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// not exists
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return None;
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}
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let capabilities = Vec::new();
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let device_id = PciDeviceId::new(location);
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2025-07-13 16:57:08 +00:00
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let bar_manager = BarManager {
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bars: [const { None }; 6],
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};
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let mut device = Self {
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device_id,
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location,
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bar_manager,
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capabilities,
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};
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2025-07-13 16:57:08 +00:00
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device.set_command(
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device.command() | Command::MEMORY_SPACE | Command::BUS_MASTER | Command::IO_SPACE,
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);
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device.bar_manager = BarManager::new(location);
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device.capabilities = Capability::device_capabilities(&mut device);
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Some(device)
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}
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pub(super) fn bar_manager_mut(&mut self) -> &mut BarManager {
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&mut self.bar_manager
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}
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pub(super) fn capabilities_mut(&mut self) -> &mut Vec<Capability> {
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&mut self.capabilities
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}
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}
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2024-06-27 09:47:20 +00:00
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/// Base Address Registers manager.
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2023-07-23 10:31:43 +00:00
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#[derive(Debug)]
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pub struct BarManager {
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2025-03-25 11:37:41 +00:00
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/// There are at most 6 BARs in PCI device.
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bars: [Option<Bar>; 6],
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}
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impl BarManager {
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/// Gain access to the BAR space and return None if that BAR is absent.
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pub fn bar(&self, idx: u8) -> &Option<Bar> {
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&self.bars[idx as usize]
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}
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/// Parse the BAR space by PCI device location.
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fn new(location: PciDeviceLocation) -> Self {
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let header_type = location.read8(PciDeviceCommonCfgOffset::HeaderType as u16) & !(1 << 7);
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// Get the max bar amount, header type=0 => end device; header type=1 => PCI bridge.
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let max = match header_type {
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0 => 6,
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1 => 2,
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_ => 0,
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};
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let mut idx = 0;
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let mut bars = [None, None, None, None, None, None];
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while idx < max {
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2023-09-04 03:04:42 +00:00
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if let Ok(bar) = Bar::new(location, idx) {
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let mut idx_step = 0;
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match &bar {
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Bar::Memory(memory_bar) => {
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if memory_bar.address_length() == AddrLen::Bits64 {
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idx_step = 1;
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}
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}
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Bar::Io(_) => {}
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}
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bars[idx as usize] = Some(bar);
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2023-09-04 03:04:42 +00:00
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idx += idx_step;
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}
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idx += 1;
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}
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Self { bars }
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}
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}
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