asterinas/kernel/comps/pci/src/common_device.rs

145 lines
4.0 KiB
Rust
Raw Normal View History

2024-01-03 03:22:36 +00:00
// SPDX-License-Identifier: MPL-2.0
2024-06-27 09:47:20 +00:00
//! PCI device common definitions or functions.
#![expect(dead_code)]
2023-07-23 10:31:43 +00:00
use alloc::vec::Vec;
use super::{
capability::Capability,
cfg_space::{AddrLen, Bar, Command, PciDeviceCommonCfgOffset, Status},
2025-07-25 07:51:39 +00:00
device_info::PciDeviceId,
2023-07-23 10:31:43 +00:00
};
use crate::device_info::PciDeviceLocation;
2023-07-23 10:31:43 +00:00
/// PCI common device, Contains a range of information and functions common to PCI devices.
#[derive(Debug)]
pub struct PciCommonDevice {
device_id: PciDeviceId,
location: PciDeviceLocation,
bar_manager: BarManager,
capabilities: Vec<Capability>,
}
impl PciCommonDevice {
2024-06-27 09:47:20 +00:00
/// PCI device ID
2023-07-23 10:31:43 +00:00
pub fn device_id(&self) -> &PciDeviceId {
&self.device_id
}
2024-06-27 09:47:20 +00:00
/// PCI device location
2023-07-23 10:31:43 +00:00
pub fn location(&self) -> &PciDeviceLocation {
&self.location
}
2024-06-27 09:47:20 +00:00
/// PCI Base Address Register (BAR) manager
2023-07-23 10:31:43 +00:00
pub fn bar_manager(&self) -> &BarManager {
&self.bar_manager
}
2024-06-27 09:47:20 +00:00
/// PCI capabilities
2023-07-23 10:31:43 +00:00
pub fn capabilities(&self) -> &Vec<Capability> {
&self.capabilities
}
2024-06-27 09:47:20 +00:00
/// Gets the PCI Command
2023-07-23 10:31:43 +00:00
pub fn command(&self) -> Command {
Command::from_bits_truncate(
self.location
.read16(PciDeviceCommonCfgOffset::Command as u16),
)
}
2024-06-27 09:47:20 +00:00
/// Sets the PCI Command
2023-07-23 10:31:43 +00:00
pub fn set_command(&self, command: Command) {
self.location
.write16(PciDeviceCommonCfgOffset::Command as u16, command.bits())
}
2024-06-27 09:47:20 +00:00
/// Gets the PCI status
2023-07-23 10:31:43 +00:00
pub fn status(&self) -> Status {
Status::from_bits_truncate(
self.location
.read16(PciDeviceCommonCfgOffset::Status as u16),
)
}
pub(super) fn new(location: PciDeviceLocation) -> Option<Self> {
if location.read16(0) == 0xFFFF {
// not exists
return None;
}
let capabilities = Vec::new();
let device_id = PciDeviceId::new(location);
let bar_manager = BarManager {
bars: [const { None }; 6],
};
2023-07-23 10:31:43 +00:00
let mut device = Self {
device_id,
location,
bar_manager,
capabilities,
};
device.set_command(
device.command() | Command::MEMORY_SPACE | Command::BUS_MASTER | Command::IO_SPACE,
);
device.bar_manager = BarManager::new(location);
2023-07-23 10:31:43 +00:00
device.capabilities = Capability::device_capabilities(&mut device);
Some(device)
}
pub(super) fn bar_manager_mut(&mut self) -> &mut BarManager {
&mut self.bar_manager
}
pub(super) fn capabilities_mut(&mut self) -> &mut Vec<Capability> {
&mut self.capabilities
}
}
2024-06-27 09:47:20 +00:00
/// Base Address Registers manager.
2023-07-23 10:31:43 +00:00
#[derive(Debug)]
pub struct BarManager {
2025-03-25 11:37:41 +00:00
/// There are at most 6 BARs in PCI device.
bars: [Option<Bar>; 6],
2023-07-23 10:31:43 +00:00
}
impl BarManager {
2025-03-25 11:37:41 +00:00
/// Gain access to the BAR space and return None if that BAR is absent.
pub fn bar(&self, idx: u8) -> &Option<Bar> {
&self.bars[idx as usize]
2023-07-23 10:31:43 +00:00
}
/// Parse the BAR space by PCI device location.
fn new(location: PciDeviceLocation) -> Self {
let header_type = location.read8(PciDeviceCommonCfgOffset::HeaderType as u16) & !(1 << 7);
// Get the max bar amount, header type=0 => end device; header type=1 => PCI bridge.
let max = match header_type {
0 => 6,
1 => 2,
_ => 0,
};
let mut idx = 0;
let mut bars = [None, None, None, None, None, None];
while idx < max {
2023-09-04 03:04:42 +00:00
if let Ok(bar) = Bar::new(location, idx) {
let mut idx_step = 0;
match &bar {
Bar::Memory(memory_bar) => {
if memory_bar.address_length() == AddrLen::Bits64 {
idx_step = 1;
2023-07-23 10:31:43 +00:00
}
}
2023-09-04 03:04:42 +00:00
Bar::Io(_) => {}
2023-07-23 10:31:43 +00:00
}
2025-03-25 11:37:41 +00:00
bars[idx as usize] = Some(bar);
2023-09-04 03:04:42 +00:00
idx += idx_step;
2023-07-23 10:31:43 +00:00
}
idx += 1;
}
Self { bars }
}
}