Unify and fix RISC-V symbol names
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121da78aa2
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@ -49,6 +49,13 @@ foo:
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The assembler treats the directives `.global` and `.globl` as the same.
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For clarity, however, `.global` is preferred.
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Note that a Rust crate is a single translation unit, so `global_asm!` labels in
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different modules within the same crate share the same global namespace. In RISC-V,
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we have experienced that defining two labels with the same name in different modules
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can nondeterministically cause duplicate symbol error. The `.L` prefix does not help.
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Therefore, add custom prefixes to your labels to avoid name clashes. Nevertheless,
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use `.global` to export symbols that need to be visible within the same crate.
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In x86-64, if an executable section contains a mix of 32-bit and 64-bit code,
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the `.code64` and `.code32` directives are treated as function attributes.
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```asm
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@ -34,6 +34,7 @@
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.section ".boot", "awx", @progbits
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# `_start` is also the entrypoint specified in the linker script.
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.global _start
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_start:
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# Set DMW0 (kernel)
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@ -19,7 +19,7 @@ use crate::{
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mm::paddr_to_vaddr,
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};
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global_asm!(include_str!("boot.S"));
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global_asm!(include_str!("bsp_boot.S"));
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static EFI_SYSTEM_TABLE: Once<&'static EfiSystemTable> = Once::new();
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@ -35,7 +35,7 @@ ap_boot_start:
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# Check if the write to satp succeeds.
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# Reference: <https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#satp>.
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csrr t3, satp
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beq t3, t1, flush_tlb_ap
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beq t3, t1, ap_flush_tlb
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# This AP doesn't support Sv48. So the `__ap_boot_page_table_pointer` must
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# point to a Sv39 page table since we assume that all harts support a same
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@ -47,13 +47,13 @@ ap_boot_start:
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# Check again if the write to satp succeeds.
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csrr t0, satp
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beq t0, t1, flush_tlb_ap
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beq t0, t1, ap_flush_tlb
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# If the CPU doesn't support either Sv48 or Sv39 this is actually reachable.
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unreachable_pa_ap:
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j unreachable_pa_ap
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ap_unreachable_pa:
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j ap_unreachable_pa
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flush_tlb_ap:
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ap_flush_tlb:
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sfence.vma # Flush TLB.
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# Now we need to switch to virtual addressing.
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@ -87,11 +87,11 @@ __ap_boot_cpu_id_tail:
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ap_boot_virtual:
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# Atomically update the CPU ID tail and load the previous value to t1.
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lla t0, __ap_boot_cpu_id_tail
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cmpxchg_load:
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ap_cmpxchg_load:
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lr.d t1, (t0)
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addi t2, t1, 1
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sc.d t2, t2, (t0)
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bnez t2, cmpxchg_load
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bnez t2, ap_cmpxchg_load
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# Get the AP boot info array pointer using absolute addressing.
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lla t2, __ap_boot_info_array_pointer
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@ -118,5 +118,5 @@ cmpxchg_load:
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lla t1, riscv_ap_early_entry
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jr t1
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unreachable_va_ap:
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j unreachable_va_ap
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ap_unreachable_va:
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j ap_unreachable_va
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@ -19,6 +19,7 @@ KERNEL_VMA_OFFSET = 0xffffffff00000000
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.section ".boot", "awx", @progbits
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# `_start` is also the entrypoint specified in the linker script.
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.global _start
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_start:
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# Arguments passed from SBI:
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@ -46,7 +47,7 @@ _start:
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# Check if the write to satp succeeds. If not, try Sv39.
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# Reference: <https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#satp>.
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csrr t1, satp
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beq t0, t1, flush_tlb_bsp
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beq t0, t1, bsp_flush_tlb
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# Try loading the Sv39 page table.
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lla t0, sv39_boot_l3pt
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@ -57,20 +58,20 @@ _start:
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# Check again if the write to satp succeeds.
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csrr t1, satp
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beq t0, t1, flush_tlb_bsp
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beq t0, t1, bsp_flush_tlb
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# If the CPU doesn't support either Sv48 or Sv39 this is actually reachable.
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unreachable_pa_bsp:
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j unreachable_pa_bsp
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bsp_unreachable_pa:
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j bsp_unreachable_pa
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flush_tlb_bsp:
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bsp_flush_tlb:
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sfence.vma
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# Update SP/PC to use the virtual address.
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li t1, KERNEL_VMA_OFFSET
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lla sp, boot_stack_top
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or sp, sp, t1
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lla t0, _start_virt - KERNEL_VMA_OFFSET
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lla t0, bsp_boot_virt - KERNEL_VMA_OFFSET
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or t0, t0, t1
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jr t0
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@ -120,7 +121,7 @@ boot_stack_top:
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.text
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_start_virt:
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bsp_boot_virt:
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# Initialize GP to the CPU-local storage's base address.
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.extern __cpu_local_start
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lla gp, __cpu_local_start
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@ -129,5 +130,5 @@ _start_virt:
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lla t0, riscv_boot
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jr t0
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unreachable_va_bsp:
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j unreachable_va_bsp
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bsp_unreachable_va:
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j bsp_unreachable_va
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@ -18,7 +18,7 @@ use crate::{
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mm::paddr_to_vaddr,
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};
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global_asm!(include_str!("boot.S"));
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global_asm!(include_str!("bsp_boot.S"));
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/// The Flattened Device Tree of the platform.
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pub static DEVICE_TREE: Once<Fdt> = Once::new();
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