Remove outdated safety comments
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35ab40057a
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19b1fe36c5
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@ -16,13 +16,7 @@ impl HwCpuId {
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}
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/// Sends a general inter-processor interrupt (IPI) to the specified CPU.
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///
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/// # Safety
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///
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/// The caller must ensure that the interrupt number is valid and that
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/// the corresponding handler is configured correctly on the remote CPU.
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/// Furthermore, invoking the interrupt handler must also be safe.
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pub(crate) unsafe fn send_ipi(_hw_cpu_id: HwCpuId, _guard: &dyn PinCurrentCpu) {
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pub(crate) fn send_ipi(_hw_cpu_id: HwCpuId, _guard: &dyn PinCurrentCpu) {
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// To suppress unused function lint errors. We should be using it here.
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let _ = crate::smp::do_inter_processor_call;
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unimplemented!()
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@ -64,7 +64,7 @@ pub(in crate::arch) unsafe fn init_current_hart() {
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/// An IRQ chip.
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///
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/// This abstracts the hardware IRQ chips (or IRQ controllers), allowing the bus
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/// or device drivers to enable [`IrqLine`]s (via, e.g., [`map_interrupt_source_to`])
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/// or device drivers to enable [`IrqLine`]s (via, e.g., [`map_fdt_pin_to`])
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/// regardless of the specifics of the IRQ chip.
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///
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/// In the RISC-V architecture, the underlying hardware is typically Platform-Level
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@ -11,8 +11,8 @@ use crate::{cpu::PinCurrentCpu, irq::IrqLine};
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pub(crate) struct HwCpuId(u32);
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impl HwCpuId {
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#[expect(unused_variables)]
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pub(crate) fn read_current(guard: &dyn PinCurrentCpu) -> Self {
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pub(crate) fn read_current(_guard: &dyn PinCurrentCpu) -> Self {
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// No races because of `_guard`.
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Self(crate::arch::boot::smp::get_current_hart_id())
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}
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}
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@ -49,14 +49,7 @@ pub(in crate::arch) unsafe fn init_current_hart() {
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}
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/// Sends a general inter-processor interrupt (IPI) to the specified CPU.
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///
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/// # Safety
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///
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/// The caller must ensure that the interrupt number is valid and that
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/// the corresponding handler is configured correctly on the remote CPU.
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/// Furthermore, invoking the interrupt handler must also be safe.
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#[expect(unused_variables)]
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pub(crate) unsafe fn send_ipi(hw_cpu_id: HwCpuId, guard: &dyn PinCurrentCpu) {
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pub(crate) fn send_ipi(hw_cpu_id: HwCpuId, _guard: &dyn PinCurrentCpu) {
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const XLEN: usize = core::mem::size_of::<usize>() * 8;
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const XLEN_MASK: usize = XLEN - 1;
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@ -110,6 +110,7 @@ pub(super) fn handle_irq(trap_frame: &TrapFrame, interrupt: Interrupt, priv_leve
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);
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}
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Interrupt::SupervisorExternal => {
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// No races because we're in IRQs.
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let hart_id = crate::arch::boot::smp::get_current_hart_id();
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while let Some(hw_irq_line) = IRQ_CHIP.get().unwrap().claim_interrupt(hart_id) {
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call_irq_callback_functions(trap_frame, &hw_irq_line, priv_level);
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@ -32,13 +32,7 @@ pub(in crate::arch) fn init() {
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}
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/// Sends a general inter-processor interrupt (IPI) to the specified CPU.
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///
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/// # Safety
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///
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/// The caller must ensure that the interrupt number is valid and that
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/// the corresponding handler is configured correctly on the remote CPU.
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/// Furthermore, invoking the interrupt handler must also be safe.
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pub(crate) unsafe fn send_ipi(hw_cpu_id: HwCpuId, guard: &dyn PinCurrentCpu) {
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pub(crate) fn send_ipi(hw_cpu_id: HwCpuId, guard: &dyn PinCurrentCpu) {
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use crate::arch::kernel::apic::{self, Icr};
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let irq_num = IPI_IRQ.get().unwrap().num();
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@ -50,11 +50,7 @@ pub fn inter_processor_call(targets: &CpuSet, f: fn()) {
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continue;
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}
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let hw_cpu_id = ipi_data.hw_cpu_ids[cpu_id.as_usize()];
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// SAFETY: The value of `irq_num` corresponds to a valid IRQ line and
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// triggering it will not cause any safety issues.
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unsafe {
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crate::arch::irq::send_ipi(hw_cpu_id, &irq_guard as _);
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}
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crate::arch::irq::send_ipi(hw_cpu_id, &irq_guard as _);
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}
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if call_on_self {
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// Execute the function synchronously.
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@ -76,7 +72,8 @@ cpu_local! {
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///
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/// # Safety
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///
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/// It should only be called upon the inter processor interrupt.
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/// This function must be called from an IRQ handler that can be triggered by
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/// inter-processor interrupts.
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pub(crate) unsafe fn do_inter_processor_call(_trapframe: &TrapFrame) {
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// No races because we are in IRQs.
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let this_cpu_id = crate::cpu::CpuId::current_racy();
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