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adjust feature enabling sequence and fix xsave size function

This commit is contained in:
Hsy-Intel 2025-07-22 14:57:36 +08:00 committed by Tate, Hongliang Tian
parent 2e3d8ea867
commit 24d56cfde7
2 changed files with 3 additions and 3 deletions
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2
ostd/src/arch/x86/cpu/context/mod.rs
View File

@ -666,7 +666,7 @@ pub(in crate::arch) fn enable_essential_features() {
let size = cpuid
.get_extended_state_info()
.unwrap()
.xsave_area_size_supported_features() as usize;
.xsave_area_size_enabled_features() as usize;
debug_assert!(size <= MAX_XSAVE_AREA_SIZE);
size
});

4
ostd/src/arch/x86/mod.rs
View File

@ -180,8 +180,6 @@ pub(crate) fn enable_cpu_features() {
cpuid.get_feature_info().unwrap()
});
cpu::context::enable_essential_features();
let mut cr4 = x86_64::registers::control::Cr4::read();
cr4 |= Cr4Flags::FSGSBASE
| Cr4Flags::OSXSAVE
@ -208,6 +206,8 @@ pub(crate) fn enable_cpu_features() {
x86_64::registers::xcontrol::XCr0::write(xcr0);
}
cpu::context::enable_essential_features();
unsafe {
// enable non-executable page protection
x86_64::registers::model_specific::Efer::update(|efer| {