Resolve minor issues in `ostd::src::arch`

ostd/src/arch/loongarch/boot/mod.rs

@@ -3,7 +3,8 @@
 //! The LoongArch boot module defines the entrypoints of Asterinas.
 
 mod efi;
-pub mod smp;
+pub(crate) mod smp;
+
 use core::{arch::global_asm, ffi::CStr};
 
 use fdt::Fdt;

ostd/src/arch/loongarch/mm/mod.rs

@@ -12,10 +12,8 @@ use crate::{
     Pod,
 };
 
-pub(crate) const NR_ENTRIES_PER_PAGE: usize = 512;
-
 #[derive(Clone, Debug, Default)]
-pub struct PagingConsts {}
+pub(crate) struct PagingConsts {}
 
 impl PagingConstsTrait for PagingConsts {
     const BASE_PAGE_SIZE: usize = 4096;
@@ -31,7 +29,7 @@ bitflags::bitflags! {
     #[derive(Pod)]
     #[repr(C)]
     /// Possible flags for a page table entry.
-    pub struct PageTableFlags: usize {
+    pub(crate) struct PageTableFlags: usize {
         /// Specifies whether the mapped frame is valid.
         const VALID =           1 << 0;
         /// Whether the memory area represented by this entry is modified.
@@ -113,13 +111,13 @@ pub(crate) fn tlb_flush_all_including_global() {
 ///
 /// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
 /// changing the page mapping.
-pub unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy) {
+pub(crate) unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy) {
     assert!(root_paddr % PagingConsts::BASE_PAGE_SIZE == 0);
     loongArch64::register::pgdl::set_base(root_paddr);
     loongArch64::register::pgdh::set_base(root_paddr);
 }
 
-pub fn current_page_table_paddr() -> Paddr {
+pub(crate) fn current_page_table_paddr() -> Paddr {
     let pgdl = loongArch64::register::pgdl::read().raw();
     let pgdh = loongArch64::register::pgdh::read().raw();
     assert_eq!(
@@ -131,7 +129,7 @@ pub fn current_page_table_paddr() -> Paddr {
 
 #[derive(Clone, Copy, Pod, Default)]
 #[repr(C)]
-pub struct PageTableEntry(usize);
+pub(crate) struct PageTableEntry(usize);
 
 impl PageTableEntry {
     const PHYS_ADDR_MASK: usize = 0x0000_FFFF_FFFF_F000;

ostd/src/arch/riscv/boot/mod.rs

@@ -2,7 +2,7 @@
 
 //! The RISC-V boot module defines the entrypoints of Asterinas.
 
-pub mod smp;
+pub(crate) mod smp;
 
 use core::arch::global_asm;
 

ostd/src/arch/riscv/mm/mod.rs

@@ -13,10 +13,8 @@ use crate::{
     Pod,
 };
 
-pub(crate) const NR_ENTRIES_PER_PAGE: usize = 512;
-
 #[derive(Clone, Debug, Default)]
-pub struct PagingConsts {}
+pub(crate) struct PagingConsts {}
 
 impl PagingConstsTrait for PagingConsts {
     const BASE_PAGE_SIZE: usize = 4096;
@@ -31,7 +29,7 @@ bitflags::bitflags! {
     #[derive(Pod)]
     #[repr(C)]
     /// Possible flags for a page table entry.
-    pub struct PageTableFlags: usize {
+    pub(crate) struct PageTableFlags: usize {
         /// Specifies whether the mapped frame or page table is valid.
         const VALID =           1 << 0;
         /// Controls whether reads to the mapped frames are allowed.
@@ -87,7 +85,7 @@ pub(crate) fn tlb_flush_all_including_global() {
 
 #[derive(Clone, Copy, Pod, Default)]
 #[repr(C)]
-pub struct PageTableEntry(usize);
+pub(crate) struct PageTableEntry(usize);
 
 /// Activate the given level 4 page table.
 ///
@@ -98,7 +96,7 @@ pub struct PageTableEntry(usize);
 ///
 /// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
 /// changing the page mapping.
-pub unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy) {
+pub(crate) unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy) {
     assert!(root_paddr % PagingConsts::BASE_PAGE_SIZE == 0);
     let ppn = root_paddr >> 12;
     unsafe {
@@ -106,7 +104,7 @@ pub unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy
     }
 }
 
-pub fn current_page_table_paddr() -> Paddr {
+pub(crate) fn current_page_table_paddr() -> Paddr {
     riscv::register::satp::read().ppn() << 12
 }
 

ostd/src/arch/x86/boot/mod.rs

@@ -22,7 +22,7 @@ mod linux_boot;
 mod multiboot;
 mod multiboot2;
 
-pub mod smp;
+pub(crate) mod smp;
 
 use core::arch::global_asm;
 

ostd/src/arch/x86/mm/mod.rs

@@ -1,7 +1,5 @@
 // SPDX-License-Identifier: MPL-2.0
 
-#![expect(dead_code)]
-
 use alloc::fmt;
 use core::ops::Range;
 
@@ -22,10 +20,8 @@ use crate::{
 
 mod util;
 
-pub(crate) const NR_ENTRIES_PER_PAGE: usize = 512;
-
 #[derive(Clone, Debug, Default)]
-pub struct PagingConsts {}
+pub(crate) struct PagingConsts {}
 
 impl PagingConstsTrait for PagingConsts {
     const BASE_PAGE_SIZE: usize = 4096;
@@ -40,7 +36,7 @@ bitflags::bitflags! {
     #[derive(Pod)]
     #[repr(C)]
     /// Possible flags for a page table entry.
-    pub struct PageTableFlags: usize {
+    pub(crate) struct PageTableFlags: usize {
         /// Specifies whether the mapped frame or page table is loaded in memory.
         const PRESENT =         1 << 0;
         /// Controls whether writes to the mapped frames are allowed.
@@ -116,7 +112,7 @@ pub(crate) fn tlb_flush_all_including_global() {
 
 #[derive(Clone, Copy, Pod, Default)]
 #[repr(C)]
-pub struct PageTableEntry(usize);
+pub(crate) struct PageTableEntry(usize);
 
 /// Activates the given level 4 page table.
 /// The cache policy of the root page table node is controlled by `root_pt_cache`.
@@ -125,7 +121,7 @@ pub struct PageTableEntry(usize);
 ///
 /// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
 /// changing the page mapping.
-pub unsafe fn activate_page_table(root_paddr: Paddr, root_pt_cache: CachePolicy) {
+pub(crate) unsafe fn activate_page_table(root_paddr: Paddr, root_pt_cache: CachePolicy) {
     let addr = PhysFrame::from_start_address(x86_64::PhysAddr::new(root_paddr as u64)).unwrap();
     let flags = match root_pt_cache {
         CachePolicy::Writeback => x86_64::registers::control::Cr3Flags::empty(),
@@ -138,7 +134,7 @@ pub unsafe fn activate_page_table(root_paddr: Paddr, root_pt_cache: CachePolicy)
     unsafe { x86_64::registers::control::Cr3::write(addr, flags) };
 }
 
-pub fn current_page_table_paddr() -> Paddr {
+pub(crate) fn current_page_table_paddr() -> Paddr {
     x86_64::registers::control::Cr3::read_raw()
         .0
         .start_address()

ostd/src/arch/x86/mod.rs

@@ -2,7 +2,7 @@
 
 //! Platform-specific code for the x86 platform.
 
-pub mod boot;
+pub(crate) mod boot;
 pub mod cpu;
 pub mod device;
 pub(crate) mod ex_table;
@@ -92,11 +92,10 @@ pub(crate) unsafe fn init_on_ap() {
 }
 
 pub(crate) fn interrupts_ack(irq_number: usize) {
-    if !cpu::context::CpuException::is_cpu_exception(irq_number) {
-        // TODO: We're in the interrupt context, so `disable_preempt()` is not
-        // really necessary here.
-        kernel::apic::get_or_init(&crate::task::disable_preempt() as _).eoi();
-    }
+    debug_assert!(!cpu::context::CpuException::is_cpu_exception(irq_number));
+    // TODO: We're in the interrupt context, so `disable_preempt()` is not
+    // really necessary here.
+    kernel::apic::get_or_init(&crate::task::disable_preempt() as _).eoi();
 }
 
 /// Returns the frequency of TSC. The unit is Hz.