Add the cpu section of LoongArch in OSTD and kernel
This commit is contained in:
王英泰
Tate, Hongliang Tian
parent
ce22374b50
commit
91e7785915
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@ -0,0 +1,188 @@
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// SPDX-License-Identifier: MPL-2.0
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use alloc::{format, string::String};
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use ostd::{
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cpu::context::{CpuExceptionInfo, GeneralRegs, UserContext},
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user::UserContextApi,
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Pod,
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};
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use crate::{cpu::LinuxAbi, thread::exception::PageFaultInfo, vm::perms::VmPerms};
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impl LinuxAbi for UserContext {
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fn syscall_num(&self) -> usize {
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self.a7()
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}
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fn set_syscall_num(&mut self, num: usize) {
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self.set_a7(num);
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}
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fn syscall_ret(&self) -> usize {
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self.a0()
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}
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fn set_syscall_ret(&mut self, ret: usize) {
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self.set_a0(ret)
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}
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fn syscall_args(&self) -> [usize; 6] {
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[
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self.a0(),
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self.a1(),
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self.a2(),
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self.a3(),
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self.a4(),
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self.a5(),
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]
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}
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fn set_tls_pointer(&mut self, tls: usize) {
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self.set_tp(tls);
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}
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fn tls_pointer(&self) -> usize {
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self.tp()
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}
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}
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/// Represents the context of a signal handler.
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///
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/// This contains the context saved before a signal handler is invoked and restored by `sys_rt_sigreturn`.
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///
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/// Reference: <https://elixir.bootlin.com/linux/v6.15.7/source/arch/loongarch/include/uapi/asm/sigcontext.h#L20>
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#[repr(C)]
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#[repr(align(16))]
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#[derive(Clone, Copy, Debug, Default, Pod)]
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pub struct SigContext {
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pub pc: usize,
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pub zero: usize,
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pub ra: usize,
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pub tp: usize,
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pub sp: usize,
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pub a0: usize,
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pub a1: usize,
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pub a2: usize,
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pub a3: usize,
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pub a4: usize,
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pub a5: usize,
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pub a6: usize,
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pub a7: usize,
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pub t0: usize,
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pub t1: usize,
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pub t2: usize,
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pub t3: usize,
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pub t4: usize,
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pub t5: usize,
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pub t6: usize,
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pub t7: usize,
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pub t8: usize,
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pub r21: usize,
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pub fp: usize,
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pub s0: usize,
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pub s1: usize,
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pub s2: usize,
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pub s3: usize,
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pub s4: usize,
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pub s5: usize,
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pub s6: usize,
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pub s7: usize,
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pub s8: usize,
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pub flags: u32,
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// In LoongArch, the signal stack layout places the FPU context directly
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// after the general-purpose registers.
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// Reference: <https://elixir.bootlin.com/linux/v6.15.7/source/arch/loongarch/kernel/signal.c#L861>
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}
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macro_rules! copy_gp_regs {
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($src: ident, $dst: ident) => {
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$dst.zero = $src.zero;
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$dst.ra = $src.ra;
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$dst.tp = $src.tp;
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$dst.sp = $src.sp;
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$dst.a0 = $src.a0;
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$dst.a1 = $src.a1;
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$dst.a2 = $src.a2;
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$dst.a3 = $src.a3;
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$dst.a4 = $src.a4;
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$dst.a5 = $src.a5;
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$dst.a6 = $src.a6;
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$dst.a7 = $src.a7;
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$dst.t0 = $src.t0;
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$dst.t1 = $src.t1;
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$dst.t2 = $src.t2;
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$dst.t3 = $src.t3;
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$dst.t4 = $src.t4;
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$dst.t5 = $src.t5;
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$dst.t6 = $src.t6;
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$dst.t7 = $src.t7;
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$dst.t8 = $src.t8;
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$dst.r21 = $src.r21;
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$dst.fp = $src.fp;
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$dst.s0 = $src.s0;
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$dst.s1 = $src.s1;
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$dst.s2 = $src.s2;
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$dst.s3 = $src.s3;
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$dst.s4 = $src.s4;
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$dst.s5 = $src.s5;
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$dst.s6 = $src.s6;
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$dst.s7 = $src.s7;
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$dst.s8 = $src.s8;
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};
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}
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impl SigContext {
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pub fn copy_user_regs_to(&self, dst: &mut UserContext) {
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let gp_regs = dst.general_regs_mut();
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copy_gp_regs!(self, gp_regs);
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dst.set_instruction_pointer(self.pc);
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}
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pub fn copy_user_regs_from(&mut self, src: &UserContext) {
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let gp_regs = src.general_regs();
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copy_gp_regs!(gp_regs, self);
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self.pc = src.instruction_pointer();
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}
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}
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impl TryFrom<&CpuExceptionInfo> for PageFaultInfo {
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// [`Err`] indicates that the [`CpuExceptionInfo`] is not a page fault,
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// with no additional error information.
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type Error = ();
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fn try_from(value: &CpuExceptionInfo) -> Result<Self, ()> {
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use loongArch64::register::estat::Exception;
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let required_perms = match value.cpu_exception() {
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Exception::FetchPageFault => VmPerms::EXEC,
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Exception::LoadPageFault => VmPerms::READ,
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Exception::StorePageFault => VmPerms::WRITE,
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_ => return Err(()),
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};
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Ok(PageFaultInfo {
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address: value.page_fault_addr,
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required_perms,
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})
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}
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}
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/// CPU Information structure.
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// TODO: Implement CPU information retrieval on LoongArch platforms.
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pub struct CpuInfo {
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processor: u32,
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}
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impl CpuInfo {
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pub fn new(processor_id: u32) -> Self {
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Self {
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processor: processor_id,
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}
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}
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/// Collect and format CPU information into a `String`.
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pub fn collect_cpu_info(&self) -> String {
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format!("processor\t: {}\n", self.processor)
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}
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}
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@ -0,0 +1,4 @@
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// SPDX-License-Identifier: MPL-2.0
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pub mod cpu;
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pub mod signal;
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: MPL-2.0
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use ostd::cpu::context::{CpuExceptionInfo, UserContext};
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use crate::process::signal::{sig_num::SigNum, signals::fault::FaultSignal, SignalContext};
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impl SignalContext for UserContext {
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fn set_arguments(&mut self, sig_num: SigNum, siginfo_addr: usize, ucontext_addr: usize) {
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self.set_a0(sig_num.as_u8() as usize);
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self.set_a1(siginfo_addr);
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self.set_a2(ucontext_addr);
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}
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}
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impl From<&CpuExceptionInfo> for FaultSignal {
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fn from(trap_info: &CpuExceptionInfo) -> Self {
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unimplemented!()
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}
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}
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@ -0,0 +1,365 @@
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// SPDX-License-Identifier: MPL-2.0
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//! CPU execution context control.
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use core::{arch::asm, fmt::Debug};
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use loongArch64::register::estat::{self, Exception, Interrupt, Trap};
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use crate::{
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arch::{
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mm::tlb_flush_addr,
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trap::{RawUserContext, TrapFrame},
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},
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trap::call_irq_callback_functions,
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user::{ReturnReason, UserContextApi, UserContextApiInternal},
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};
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/// General registers
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#[derive(Debug, Default, Clone, Copy)]
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#[repr(C)]
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#[expect(missing_docs)]
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pub struct GeneralRegs {
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pub zero: usize,
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pub ra: usize,
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pub tp: usize,
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pub sp: usize,
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pub a0: usize,
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pub a1: usize,
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pub a2: usize,
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pub a3: usize,
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pub a4: usize,
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pub a5: usize,
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pub a6: usize,
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pub a7: usize,
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pub t0: usize,
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pub t1: usize,
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pub t2: usize,
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pub t3: usize,
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pub t4: usize,
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pub t5: usize,
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pub t6: usize,
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pub t7: usize,
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pub t8: usize,
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pub r21: usize,
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pub fp: usize,
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pub s0: usize,
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pub s1: usize,
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pub s2: usize,
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pub s3: usize,
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pub s4: usize,
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pub s5: usize,
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pub s6: usize,
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pub s7: usize,
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pub s8: usize,
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}
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/// CPU exception information.
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//
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// TODO: Refactor the struct into an enum (similar to x86's `CpuException`).
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#[derive(Clone, Copy, Debug)]
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#[repr(C)]
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pub struct CpuExceptionInfo {
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/// The type of the exception.
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pub code: Exception,
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/// The page fault address.
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pub page_fault_addr: usize,
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/// The error code associated with the exception.
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pub error_code: usize, // TODO
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}
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impl Default for CpuExceptionInfo {
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fn default() -> Self {
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CpuExceptionInfo {
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code: Exception::AddressNotAligned,
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page_fault_addr: 0,
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error_code: 0,
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}
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}
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}
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impl CpuExceptionInfo {
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/// Gets corresponding CPU exception.
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pub fn cpu_exception(&self) -> CpuException {
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self.code
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}
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}
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/// Userspace CPU context, including general-purpose registers and exception information.
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#[derive(Clone, Copy, Debug)]
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#[repr(C)]
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pub struct UserContext {
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user_context: RawUserContext,
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trap: Trap,
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cpu_exception_info: Option<CpuExceptionInfo>,
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}
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impl Default for UserContext {
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fn default() -> Self {
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UserContext {
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user_context: RawUserContext::default(),
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trap: Trap::Unknown,
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cpu_exception_info: None,
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}
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}
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}
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impl UserContext {
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/// Returns a reference to the general registers.
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pub fn general_regs(&self) -> &GeneralRegs {
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&self.user_context.general
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}
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/// Returns a mutable reference to the general registers
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pub fn general_regs_mut(&mut self) -> &mut GeneralRegs {
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&mut self.user_context.general
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}
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/// Returns the trap information.
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pub fn take_exception(&mut self) -> Option<CpuExceptionInfo> {
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self.cpu_exception_info.take()
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}
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/// Sets thread-local storage pointer.
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pub fn set_tls_pointer(&mut self, tls: usize) {
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self.set_tp(tls)
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}
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/// Gets thread-local storage pointer.
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pub fn tls_pointer(&self) -> usize {
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self.tp()
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}
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/// Activates thread-local storage pointer on the current CPU.
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pub fn activate_tls_pointer(&self) {
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// No-op
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}
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/// Enables floating-point unit.
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pub fn enable_fpu(&mut self) {
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self.user_context.euen = 0x1;
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}
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}
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impl UserContextApiInternal for UserContext {
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fn execute<F>(&mut self, mut has_kernel_event: F) -> ReturnReason
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where
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F: FnMut() -> bool,
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{
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let ret = loop {
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self.user_context.run();
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let cause = loongArch64::register::estat::read().cause();
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let badv = loongArch64::register::badv::read().raw();
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let badi = loongArch64::register::badi::read().raw();
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let era = loongArch64::register::era::read().raw();
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match cause {
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Trap::Exception(exception) => match exception {
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Exception::Syscall => {
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self.user_context.era += 4;
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break ReturnReason::UserSyscall;
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}
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Exception::LoadPageFault
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| Exception::StorePageFault
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| Exception::FetchPageFault
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| Exception::PageModifyFault
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| Exception::PageNonReadableFault
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| Exception::PageNonExecutableFault
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| Exception::PagePrivilegeIllegal => {
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// Handle page fault
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// Disable the badv in TLB.
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tlb_flush_addr(badv);
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self.cpu_exception_info = Some(CpuExceptionInfo {
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code: exception,
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page_fault_addr: badv,
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error_code: 0, // TODO: Set error code if needed
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});
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break ReturnReason::UserException;
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}
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Exception::FetchInstructionAddressError
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| Exception::MemoryAccessAddressError
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| Exception::AddressNotAligned
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| Exception::BoundsCheckFault
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| Exception::Breakpoint
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| Exception::InstructionNotExist
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| Exception::InstructionPrivilegeIllegal => {
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// Handle other exceptions
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self.cpu_exception_info = Some(CpuExceptionInfo {
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code: exception,
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page_fault_addr: 0,
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error_code: 0, // TODO: Set error code if needed
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});
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log::debug!(
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"Exception {exception:?} occurred, badv: {badv:#x?}, badi: {badi:#x?}, era: {era:#x?}"
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);
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break ReturnReason::UserException;
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}
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Exception::FloatingPointUnavailable => {
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log::debug!(
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"Floating point unit is not available, badv: {badv:#x?}, badi: {badi:#x?}, era: {era:#x?}"
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);
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// TODO: Add FPU support and enable it when this exception occurs.
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break ReturnReason::UserException;
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}
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Exception::TLBRFill => unreachable!(),
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},
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Trap::Interrupt(interrupt) => match interrupt {
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Interrupt::SWI0 => todo!(),
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Interrupt::SWI1 => todo!(),
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Interrupt::HWI0
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| Interrupt::HWI1
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| Interrupt::HWI2
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| Interrupt::HWI3
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| Interrupt::HWI4
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| Interrupt::HWI5
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| Interrupt::HWI6
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| Interrupt::HWI7 => {
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log::debug!("Handling hardware interrupt: {:?}", interrupt);
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while let Some(irq) = crate::arch::kernel::irq::claim() {
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// Call the IRQ callback functions for the claimed interrupt
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call_irq_callback_functions(&self.as_trap_frame(), irq as _);
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}
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}
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Interrupt::PMI => todo!(),
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Interrupt::Timer => todo!(),
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Interrupt::IPI => todo!(),
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},
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Trap::MachineError(machine_error) => panic!(
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"Machine error: {machine_error:?}, badv: {badv:#x?}, badi: {badi:#x?}, era: {era:#x?}"
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),
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Trap::Unknown => panic!(
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"Unknown trap, badv: {badv:#x?}, badi: {badi:#x?}, era: {era:#x?}"
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),
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}
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if has_kernel_event() {
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break ReturnReason::KernelEvent;
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}
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};
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crate::arch::irq::enable_local();
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ret
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}
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fn as_trap_frame(&self) -> TrapFrame {
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TrapFrame {
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general: self.user_context.general,
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prmd: self.user_context.prmd,
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era: self.user_context.era,
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euen: self.user_context.euen,
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}
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}
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}
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impl UserContextApi for UserContext {
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fn trap_number(&self) -> usize {
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todo!()
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}
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fn trap_error_code(&self) -> usize {
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todo!()
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}
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fn instruction_pointer(&self) -> usize {
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self.user_context.era
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}
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fn set_instruction_pointer(&mut self, ip: usize) {
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self.user_context.era = ip;
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}
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fn stack_pointer(&self) -> usize {
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self.sp()
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}
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fn set_stack_pointer(&mut self, sp: usize) {
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self.set_sp(sp);
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}
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}
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macro_rules! cpu_context_impl_getter_setter {
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( $( [ $field: ident, $setter_name: ident] ),*) => {
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impl UserContext {
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$(
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#[doc = concat!("Gets the value of ", stringify!($field))]
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#[inline(always)]
|
||||
pub fn $field(&self) -> usize {
|
||||
self.user_context.general.$field
|
||||
}
|
||||
|
||||
#[doc = concat!("Sets the value of ", stringify!($field))]
|
||||
#[inline(always)]
|
||||
pub fn $setter_name(&mut self, $field: usize) {
|
||||
self.user_context.general.$field = $field;
|
||||
}
|
||||
)*
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
cpu_context_impl_getter_setter!(
|
||||
[ra, set_ra],
|
||||
[tp, set_tp],
|
||||
[sp, set_sp],
|
||||
[a0, set_a0],
|
||||
[a1, set_a1],
|
||||
[a2, set_a2],
|
||||
[a3, set_a3],
|
||||
[a4, set_a4],
|
||||
[a5, set_a5],
|
||||
[a6, set_a6],
|
||||
[a7, set_a7],
|
||||
[t0, set_t0],
|
||||
[t1, set_t1],
|
||||
[t2, set_t2],
|
||||
[t3, set_t3],
|
||||
[t4, set_t4],
|
||||
[t5, set_t5],
|
||||
[t6, set_t6],
|
||||
[t7, set_t7],
|
||||
[t8, set_t8],
|
||||
[r21, set_r21],
|
||||
[fp, set_fp],
|
||||
[s0, set_s0],
|
||||
[s1, set_s1],
|
||||
[s2, set_s2],
|
||||
[s3, set_s3],
|
||||
[s4, set_s4],
|
||||
[s5, set_s5],
|
||||
[s6, set_s6],
|
||||
[s7, set_s7],
|
||||
[s8, set_s8]
|
||||
);
|
||||
|
||||
/// CPU exception.
|
||||
pub type CpuException = Exception;
|
||||
|
||||
/// The FPU context of user task.
|
||||
/// Reference: <https://elixir.bootlin.com/linux/v6.15.7/source/arch/loongarch/include/uapi/asm/sigcontext.h#L37>
|
||||
// FIXME: Implement FPU context on LoongArch64 platforms.
|
||||
#[derive(Clone, Copy, Debug, Default)]
|
||||
pub struct FpuContext;
|
||||
|
||||
impl FpuContext {
|
||||
/// Creates a new FPU context.
|
||||
pub fn new() -> Self {
|
||||
Self
|
||||
}
|
||||
|
||||
/// Saves CPU's current FPU context to this instance, if needed.
|
||||
pub fn save(&mut self) {}
|
||||
|
||||
/// Loads CPU's FPU context from this instance, if needed.
|
||||
pub fn load(&mut self) {}
|
||||
|
||||
/// Returns the FPU context as a byte slice.
|
||||
pub fn as_bytes(&self) -> &[u8] {
|
||||
&[]
|
||||
}
|
||||
|
||||
/// Returns the FPU context as a mutable byte slice.
|
||||
pub fn as_bytes_mut(&mut self) -> &mut [u8] {
|
||||
&mut []
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: MPL-2.0
|
||||
|
||||
//! Architecture dependent CPU-local information utilities.
|
||||
|
||||
pub(crate) fn get_base() -> u64 {
|
||||
let mut gp;
|
||||
unsafe {
|
||||
core::arch::asm!(
|
||||
"move {gp}, $r21",
|
||||
gp = out(reg) gp,
|
||||
options(preserves_flags, nostack)
|
||||
);
|
||||
}
|
||||
gp
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
// SPDX-License-Identifier: MPL-2.0
|
||||
|
||||
//! CPU context & state control and CPU local memory.
|
||||
|
||||
pub mod context;
|
||||
pub mod local;
|
||||
Loading…
Reference in New Issue