diff --git a/ostd/src/arch/x86/irq/chip/ioapic.rs b/ostd/src/arch/x86/irq/chip/ioapic.rs
index 8427bba0b..b4ca5586a 100644
--- a/ostd/src/arch/x86/irq/chip/ioapic.rs
+++ b/ostd/src/arch/x86/irq/chip/ioapic.rs
@@ -161,7 +161,11 @@ impl IoApicAccess {
     /// I/O Window (data).
     const MMIO_WIN: usize = 0x10;
     /// The size of the MMIO region.
-    const MMIO_SIZE: usize = 0x20;
+    ///
+    /// I/O APICs only have two MMIO registers, at offsets 0x00 and 0x10. Therefore, the size of
+    /// the MMIO region may be 0x20. However, we use a page here because (1) multiple I/O APICs
+    /// typically use different MMIO pages and (2) TD guests do not support sub-page MMIO regions.
+    const MMIO_SIZE: usize = crate::mm::PAGE_SIZE;
 
     /// IOAPIC ID.
     const IOAPICID: u8 = 0x00;
diff --git a/ostd/src/arch/x86/kernel/apic/xapic.rs b/ostd/src/arch/x86/kernel/apic/xapic.rs
index 90b49cbcc..a4608b686 100644
--- a/ostd/src/arch/x86/kernel/apic/xapic.rs
+++ b/ostd/src/arch/x86/kernel/apic/xapic.rs
@@ -145,4 +145,8 @@ pub(super) unsafe fn read_xapic_base_address() -> usize {
 }
 
 /// The size of the xAPIC MMIO region.
-pub(super) const XAPIC_MMIO_SIZE: usize = size_of::<[u32; 256]>();
+///
+/// Intel(R) 64 and IA-32 Architectures Software Developer's Manual, CHAPTER 11 ADVANCED
+/// PROGRAMMABLE INTERRUPT CONTROLLER (APIC) says "The local-APIC register-address space comprises
+/// the 4 KBytes at the physical address specified in the IA32_APIC_BASE MSR."
+pub(super) const XAPIC_MMIO_SIZE: usize = crate::mm::PAGE_SIZE;