Add the mm section of LoongArch in OSTD
This commit is contained in:
王英泰
Tate, Hongliang Tian
parent
d3538ec6df
commit
e4db73e1a0
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@ -0,0 +1,314 @@
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// SPDX-License-Identifier: MPL-2.0
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use alloc::fmt;
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use core::{arch::asm, ops::Range};
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use crate::{
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mm::{
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page_prop::{CachePolicy, PageFlags, PageProperty, PrivilegedPageFlags as PrivFlags},
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page_table::PageTableEntryTrait,
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Paddr, PagingConstsTrait, PagingLevel, PodOnce, Vaddr, PAGE_SIZE,
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},
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Pod,
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};
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pub(crate) const NR_ENTRIES_PER_PAGE: usize = 512;
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#[derive(Clone, Debug, Default)]
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pub struct PagingConsts {}
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impl PagingConstsTrait for PagingConsts {
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const BASE_PAGE_SIZE: usize = 4096;
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const NR_LEVELS: PagingLevel = 4;
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const ADDRESS_WIDTH: usize = 48;
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const VA_SIGN_EXT: bool = true;
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// TODO: Support huge page
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const HIGHEST_TRANSLATION_LEVEL: PagingLevel = 1;
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const PTE_SIZE: usize = core::mem::size_of::<PageTableEntry>();
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}
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bitflags::bitflags! {
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#[derive(Pod)]
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#[repr(C)]
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/// Possible flags for a page table entry.
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pub struct PageTableFlags: usize {
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/// Specifies whether the mapped frame is valid.
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const VALID = 1 << 0;
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/// Whether the memory area represented by this entry is modified.
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const DIRTY = 1 << 1;
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/// Privilege level corresponding to the page table entry.
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/// When `RPLV` = 0, the page table entry can be accessed by any program
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/// with a privilege level not lower than `PLV`;
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/// When `RPLV` = 1, this page table entry can only be accessed by programs
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/// with privilege level equal to `PLV`.
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const PLVL = 1 << 2;
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const PLVH = 1 << 3;
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/// Controls the memory access type of the memory access operation
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/// falling on the address space of the table page entry.
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const MATL = 1 << 4;
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const MATH = 1 << 5;
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/// If this entry is a basic page table entry, it is `GLOBAL`,
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/// which means that the mapping is present in all address spaces,
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/// so it isn't flushed from the TLB on an address space switch.
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/// If this entry is a huge page table entry, it is `HUGE`,
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/// which means that the memory area represented by this entry is
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/// a huge page.
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const GLOBAL_OR_HUGE = 1 << 6;
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/// Specifies whether the mapped frame or page table is loaded in memory.
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/// This flag does not fill in TLB.
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const PRESENT = 1 << 7;
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/// Controls whether writes to the mapped frames are allowed.
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/// This flag does not fill in TLB.
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const WRITABLE = 1 << 8;
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// Whether this entry is a basic page table entry.
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const IS_BASIC = 1 << 9;
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// First bit ignored by MMU.
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const RSV1 = 1 << 10;
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// Second bit ignored by MMU.
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const RSV2 = 1 << 11;
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/// If this entry is a huge page table entry, it is `GLOBAL`.
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const GLOBAL_IN_HUGE = 1 << 12;
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/// Controls whether reads to the mapped frames are not allowed.
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const NOT_READABLE = 1 << 61;
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/// Controls whether execution code in the mapped frames are not allowed.
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const NOT_EXECUTABLE = 1 << 62;
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/// Whether the `PageTableEntry` can only be accessed by the privileged level `PLV` field inferred
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const RPLV = 1 << 63;
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}
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}
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pub(crate) fn tlb_flush_addr(vaddr: Vaddr) {
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unsafe {
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asm!(
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"invtlb 0, $zero, {}",
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in(reg) vaddr
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);
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}
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}
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pub(crate) fn tlb_flush_addr_range(range: &Range<Vaddr>) {
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for vaddr in range.clone().step_by(PAGE_SIZE) {
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tlb_flush_addr(vaddr);
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}
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}
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pub(crate) fn tlb_flush_all_excluding_global() {
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unsafe {
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asm!("invtlb 3, $zero, $zero");
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}
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}
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pub(crate) fn tlb_flush_all_including_global() {
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unsafe {
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asm!("invtlb 0, $zero, $zero");
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}
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}
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/// Activates the given level 4 page table.
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///
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/// "pgdl" or "pgdh" register doesn't have a field that encodes the cache policy,
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/// so `_root_pt_cache` is ignored.
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///
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/// # Safety
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///
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/// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
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/// changing the page mapping.
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pub unsafe fn activate_page_table(root_paddr: Paddr, _root_pt_cache: CachePolicy) {
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assert!(root_paddr % PagingConsts::BASE_PAGE_SIZE == 0);
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loongArch64::register::pgdl::set_base(root_paddr);
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loongArch64::register::pgdh::set_base(root_paddr);
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}
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pub fn current_page_table_paddr() -> Paddr {
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let pgdl = loongArch64::register::pgdl::read().raw();
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let pgdh = loongArch64::register::pgdh::read().raw();
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assert_eq!(
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pgdl, pgdh,
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"Only support to share the same page table for both user and kernel space"
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);
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pgdl
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}
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#[derive(Clone, Copy, Pod, Default)]
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#[repr(C)]
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pub struct PageTableEntry(usize);
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impl PageTableEntry {
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const PHYS_ADDR_MASK: usize = 0x0000_FFFF_FFFF_F000;
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fn is_user(&self) -> bool {
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self.0 & PageTableFlags::PLVL.bits() != 0 && self.0 & PageTableFlags::PLVH.bits() != 0
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}
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fn is_huge(&self) -> bool {
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if self.0 & PageTableFlags::IS_BASIC.bits() != 0 {
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return false;
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} else {
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return self.0 & PageTableFlags::GLOBAL_OR_HUGE.bits() != 0;
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}
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}
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fn is_global(&self) -> bool {
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if self.0 & PageTableFlags::IS_BASIC.bits() != 0 {
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return self.0 & PageTableFlags::GLOBAL_OR_HUGE.bits() != 0;
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} else {
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return self.0 & PageTableFlags::GLOBAL_IN_HUGE.bits() != 0;
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}
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}
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}
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/// Parse a bit-flag bits `val` in the representation of `from` to `to` in bits.
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macro_rules! parse_flags {
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($val:expr, $from:expr, $to:expr) => {
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($val as usize & $from.bits() as usize) >> $from.bits().ilog2() << $to.bits().ilog2()
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};
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}
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impl PodOnce for PageTableEntry {}
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impl PageTableEntryTrait for PageTableEntry {
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fn is_present(&self) -> bool {
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self.0 & PageTableFlags::VALID.bits() != 0
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}
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fn new_page(paddr: Paddr, level: PagingLevel, prop: PageProperty) -> Self {
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let flags = if level == 1 {
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PageTableFlags::IS_BASIC.bits()
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} else {
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PageTableFlags::GLOBAL_OR_HUGE.bits()
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};
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let mut pte = Self(paddr & Self::PHYS_ADDR_MASK);
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pte.set_prop(prop);
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let pte = pte.0 | flags;
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Self(pte)
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}
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fn new_pt(paddr: Paddr) -> Self {
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Self(paddr & Self::PHYS_ADDR_MASK | PageTableFlags::VALID.bits())
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}
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fn paddr(&self) -> Paddr {
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if self.is_huge() {
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let paddr =
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(self.0 & Self::PHYS_ADDR_MASK & !PageTableFlags::GLOBAL_IN_HUGE.bits()) >> 12;
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paddr << 12
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} else {
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let ppn = (self.0 & Self::PHYS_ADDR_MASK) >> 12;
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ppn << 12
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}
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}
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fn prop(&self) -> PageProperty {
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let flags = (parse_flags!(!(self.0), PageTableFlags::NOT_READABLE, PageFlags::R))
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| (parse_flags!(self.0, PageTableFlags::WRITABLE, PageFlags::W))
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| (parse_flags!(!(self.0), PageTableFlags::NOT_EXECUTABLE, PageFlags::X))
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// TODO: How to get the accessed bit in loongarch?
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| (parse_flags!(self.0, PageTableFlags::PRESENT, PageFlags::ACCESSED))
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| (parse_flags!(self.0, PageTableFlags::DIRTY, PageFlags::DIRTY))
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| (parse_flags!(self.0, PageTableFlags::RSV1, PageFlags::AVAIL1))
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| (parse_flags!(self.0, PageTableFlags::RSV2, PageFlags::AVAIL2));
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let mut priv_flags = PrivFlags::empty().bits();
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if self.is_user() {
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priv_flags |= PrivFlags::USER.bits();
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}
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if self.is_global() {
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priv_flags |= PrivFlags::GLOBAL.bits();
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}
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let cache = if self.0 & PageTableFlags::MATL.bits() != 0 {
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CachePolicy::Writeback
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} else if self.0 & PageTableFlags::MATH.bits() != 0 {
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CachePolicy::WriteCombining
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} else {
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CachePolicy::Writeback
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};
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PageProperty {
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flags: PageFlags::from_bits(flags as u8).unwrap(),
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cache,
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priv_flags: PrivFlags::from_bits(priv_flags as u8).unwrap(),
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}
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}
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fn set_prop(&mut self, prop: PageProperty) {
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let mut flags = PageTableFlags::VALID.bits()
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// FIXME: To avoid the PageModifyFault exception,
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// we set the DIRTY bit to 1 all the time.
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| PageTableFlags::DIRTY.bits()
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| parse_flags!(
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!prop.flags.bits(),
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PageFlags::R,
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PageTableFlags::NOT_READABLE
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)
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| parse_flags!(prop.flags.bits(), PageFlags::W, PageTableFlags::WRITABLE)
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| parse_flags!(
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!prop.flags.bits(),
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PageFlags::X,
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PageTableFlags::NOT_EXECUTABLE
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)
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| parse_flags!(prop.flags.bits(), PageFlags::DIRTY, PageTableFlags::DIRTY)
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// TODO: How to get the accessed bit in loongarch?
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| parse_flags!(prop.flags.bits(), PageFlags::ACCESSED, PageTableFlags::PRESENT)
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| parse_flags!(prop.flags.bits(), PageFlags::AVAIL1, PageTableFlags::RSV1)
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| parse_flags!(prop.flags.bits(), PageFlags::AVAIL2, PageTableFlags::RSV2);
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if prop.priv_flags.contains(PrivFlags::USER) {
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flags |= PageTableFlags::PLVL.bits();
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flags |= PageTableFlags::PLVH.bits();
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}
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if prop.priv_flags.contains(PrivFlags::GLOBAL) {
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if self.is_huge() {
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flags |= PageTableFlags::GLOBAL_IN_HUGE.bits();
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} else {
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flags |= PageTableFlags::GLOBAL_OR_HUGE.bits();
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}
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}
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match prop.cache {
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CachePolicy::Writeback => {
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flags |= PageTableFlags::MATL.bits();
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}
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CachePolicy::Uncacheable => (),
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CachePolicy::WriteCombining => {
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flags |= PageTableFlags::MATH.bits();
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}
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_ => panic!("unsupported cache policy"),
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}
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self.0 = (self.0 & Self::PHYS_ADDR_MASK) | flags;
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}
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fn is_last(&self, level: PagingLevel) -> bool {
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level == 1 || self.is_huge()
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}
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}
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impl fmt::Debug for PageTableEntry {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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let mut f = f.debug_struct("PageTableEntry");
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f.field("raw", &format_args!("{:#x}", self.0))
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.field("paddr", &format_args!("{:#x}", self.paddr()))
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.field("present", &self.is_present())
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.field(
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"flags",
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&PageTableFlags::from_bits_truncate(self.0 & !Self::PHYS_ADDR_MASK),
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)
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.field("prop", &self.prop())
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.finish()
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}
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}
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pub(in crate::arch) fn paddr_to_daddr(pa: Paddr) -> usize {
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const DEVICE_LINEAR_MAPPING_BASE_VADDR: usize = 0x8000_0000_0000_0000;
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pa + DEVICE_LINEAR_MAPPING_BASE_VADDR
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}
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pub(crate) unsafe fn __memcpy_fallible(dst: *mut u8, src: *const u8, size: usize) -> usize {
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// TODO: implement fallible
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unsafe { core::ptr::copy(src, dst, size) };
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0
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}
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pub(crate) unsafe fn __memset_fallible(dst: *mut u8, value: u8, size: usize) -> usize {
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// TODO: implement fallible
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unsafe { core::ptr::write_bytes(dst, value, size) };
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0
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}
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@ -467,6 +467,11 @@ pub(crate) unsafe fn init() -> Segment<MetaPageMeta> {
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max_paddr
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);
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// In RISC-V, the boot page table has mapped the 512GB memory,
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// so we don't need to add temporary linear mapping.
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// In LoongArch, the DWM0 has mapped the whole memory,
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// so we don't need to add temporary linear mapping.
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#[cfg(target_arch = "x86_64")]
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add_temp_linear_mapping(max_paddr);
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let tot_nr_frames = max_paddr / page_size::<PagingConsts>(1);
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@ -604,6 +609,7 @@ fn mark_unusable_ranges() {
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/// We only assume boot page table to contain 4G linear mapping. Thus if the
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/// physical memory is huge we end up depleted of linear virtual memory for
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/// initializing metadata.
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#[cfg(target_arch = "x86_64")]
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fn add_temp_linear_mapping(max_paddr: Paddr) {
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const PADDR4G: Paddr = 0x1_0000_0000;
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@ -949,7 +949,11 @@ impl<'a> From<&'a mut [u8]> for VmWriter<'a, Infallible> {
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/// `read_once`/`write_once` will lead to a failed compile-time assertion.
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pub trait PodOnce: Pod {}
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#[cfg(any(target_arch = "x86_64", target_arch = "riscv64"))]
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#[cfg(any(
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target_arch = "x86_64",
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target_arch = "riscv64",
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target_arch = "loongarch64"
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))]
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mod pod_once_impls {
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use super::PodOnce;
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@ -66,7 +66,10 @@ const ADDR_WIDTH_SHIFT: isize = PagingConsts::ADDRESS_WIDTH as isize - 48;
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/// Start of the kernel address space.
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/// This is the _lowest_ address of the x86-64's _high_ canonical addresses.
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#[cfg(not(target_arch = "loongarch64"))]
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pub const KERNEL_BASE_VADDR: Vaddr = 0xffff_8000_0000_0000 << ADDR_WIDTH_SHIFT;
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#[cfg(target_arch = "loongarch64")]
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pub const KERNEL_BASE_VADDR: Vaddr = 0x9000_0000_0000_0000 << ADDR_WIDTH_SHIFT;
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/// End of the kernel address space (non inclusive).
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pub const KERNEL_END_VADDR: Vaddr = 0xffff_ffff_ffff_0000 << ADDR_WIDTH_SHIFT;
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@ -83,6 +86,8 @@ pub fn kernel_loaded_offset() -> usize {
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const KERNEL_CODE_BASE_VADDR: usize = 0xffff_ffff_8000_0000 << ADDR_WIDTH_SHIFT;
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#[cfg(target_arch = "riscv64")]
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const KERNEL_CODE_BASE_VADDR: usize = 0xffff_ffff_0000_0000 << ADDR_WIDTH_SHIFT;
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#[cfg(target_arch = "loongarch64")]
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const KERNEL_CODE_BASE_VADDR: usize = 0x9000_0000_0000_0000 << ADDR_WIDTH_SHIFT;
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const FRAME_METADATA_CAP_VADDR: Vaddr = 0xffff_e100_0000_0000 << ADDR_WIDTH_SHIFT;
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const FRAME_METADATA_BASE_VADDR: Vaddr = 0xffff_e000_0000_0000 << ADDR_WIDTH_SHIFT;
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@ -94,7 +99,10 @@ pub const VMALLOC_VADDR_RANGE: Range<Vaddr> = VMALLOC_BASE_VADDR..FRAME_METADATA
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/// The base address of the linear mapping of all physical
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/// memory in the kernel address space.
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#[cfg(not(target_arch = "loongarch64"))]
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pub const LINEAR_MAPPING_BASE_VADDR: Vaddr = 0xffff_8000_0000_0000 << ADDR_WIDTH_SHIFT;
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#[cfg(target_arch = "loongarch64")]
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pub const LINEAR_MAPPING_BASE_VADDR: Vaddr = 0x9000_0000_0000_0000 << ADDR_WIDTH_SHIFT;
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pub const LINEAR_MAPPING_VADDR_RANGE: Range<Vaddr> = LINEAR_MAPPING_BASE_VADDR..VMALLOC_BASE_VADDR;
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/// Convert physical address to virtual address using offset, only available inside `ostd`
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@ -173,6 +181,8 @@ pub fn init_kernel_page_table(meta_pages: Segment<MetaPageMeta>) {
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let kpt = PageTable::<KernelPtConfig>::new_kernel_page_table();
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let preempt_guard = disable_preempt();
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// In LoongArch64, we don't need to do linear mappings for the kernel because of DMW0.
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#[cfg(not(target_arch = "loongarch64"))]
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// Do linear mappings for the kernel.
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{
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let max_paddr = crate::mm::frame::max_paddr();
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@ -213,6 +223,8 @@ pub fn init_kernel_page_table(meta_pages: Segment<MetaPageMeta>) {
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}
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}
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// In LoongArch64, we don't need to do linear mappings for the kernel code because of DMW0.
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#[cfg(not(target_arch = "loongarch64"))]
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// Map for the kernel code itself.
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// TODO: set separated permissions for each segments in the kernel.
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{
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