Remove unnecessary `_rdtsc` uses

ostd/src/arch/x86/boot/smp.rs

@@ -343,13 +343,8 @@ fn spin_wait_cycles(c: u64) {
         }
     }
 
-    use core::arch::x86_64::_rdtsc;
-
-    // SAFETY: Reading CPU cycles is always safe.
-    let start = unsafe { _rdtsc() };
-
-    // SAFETY: Reading CPU cycles is always safe.
-    while duration(start, unsafe { _rdtsc() }) < c {
+    let start = crate::arch::read_tsc();
+    while duration(start, crate::arch::read_tsc()) < c {
         core::hint::spin_loop();
     }
 }

ostd/src/arch/x86/kernel/tsc.rs

@@ -2,10 +2,7 @@
 
 #![expect(unused_variables)]
 
-use core::{
-    arch::x86_64::_rdtsc,
-    sync::atomic::{AtomicBool, AtomicU64, Ordering},
-};
+use core::sync::atomic::{AtomicBool, AtomicU64, Ordering};
 
 use log::info;
 use x86::cpuid::cpuid;
@@ -95,20 +92,20 @@ pub fn determine_tsc_freq_via_pit() -> u64 {
         // Set a certain times of callbacks to calculate the frequency
         const CALLBACK_TIMES: u64 = TIMER_FREQ / 10;
 
+        let tsc_current_count = crate::arch::read_tsc();
+
         if IN_TIME.load(Ordering::Relaxed) < CALLBACK_TIMES || IS_FINISH.load(Ordering::Acquire) {
             if IN_TIME.load(Ordering::Relaxed) == 0 {
-                unsafe {
-                    TSC_FIRST_COUNT.store(_rdtsc(), Ordering::Relaxed);
-                }
+                TSC_FIRST_COUNT.store(tsc_current_count, Ordering::Relaxed);
             }
             IN_TIME.fetch_add(1, Ordering::Relaxed);
             return;
         }
 
         pit::disable_ioapic_line();
-        let tsc_count = unsafe { _rdtsc() };
-        let freq =
-            (tsc_count - TSC_FIRST_COUNT.load(Ordering::Relaxed)) * (TIMER_FREQ / CALLBACK_TIMES);
+
+        let tsc_first_count = TSC_FIRST_COUNT.load(Ordering::Relaxed);
+        let freq = (tsc_current_count - tsc_first_count) * (TIMER_FREQ / CALLBACK_TIMES);
         FREQUENCY.store(freq, Ordering::Release);
         IS_FINISH.store(true, Ordering::Release);
     }

ostd/src/arch/x86/mod.rs

@@ -25,10 +25,7 @@ use x86::cpuid::{CpuId, FeatureInfo};
 #[cfg(feature = "cvm_guest")]
 pub(crate) mod tdx_guest;
 
-use core::{
-    arch::x86_64::{_rdrand64_step, _rdtsc},
-    sync::atomic::Ordering,
-};
+use core::sync::atomic::Ordering;
 
 use kernel::apic::ioapic;
 use log::{info, warn};
@@ -132,6 +129,8 @@ pub fn tsc_freq() -> u64 {
 
 /// Reads the current value of the processor’s time-stamp counter (TSC).
 pub fn read_tsc() -> u64 {
+    use core::arch::x86_64::_rdtsc;
+
     // SAFETY: It is safe to read a time-related counter.
     unsafe { _rdtsc() }
 }
@@ -140,6 +139,8 @@ pub fn read_tsc() -> u64 {
 ///
 /// Returns None if no random value was generated.
 pub fn read_random() -> Option<u64> {
+    use core::arch::x86_64::_rdrand64_step;
+
     // Recommendation from "Intel® Digital Random Number Generator (DRNG) Software
     // Implementation Guide" - Section 5.2.1 and "Intel® 64 and IA-32 Architectures
     // Software Developer’s Manual" - Volume 1 - Section 7.3.17.1.

ostd/src/arch/x86/timer/apic.rs

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: MPL-2.0
 
-use core::{
-    arch::x86_64::_rdtsc,
-    sync::atomic::{AtomicU64, Ordering},
-};
+use core::sync::atomic::{AtomicU64, Ordering};
 
 use log::info;
 
@@ -46,7 +43,7 @@ pub(super) fn timer_callback() {
 
     match CONFIG.get().expect("ACPI timer config is not initialized") {
         Config::DeadlineMode { tsc_interval } => {
-            let tsc_value = unsafe { _rdtsc() };
+            let tsc_value = crate::arch::read_tsc();
             let next_tsc_value = tsc_interval + tsc_value;
             unsafe { wrmsr(IA32_TSC_DEADLINE, next_tsc_value) };
         }