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546 Commits

Author SHA1 Message Date
Ruihan Li 275fd21650 Retire missing `ptr::sub` in `mm/io.rs` 2025-08-10 16:40:11 +08:00
Ruihan Li aa7aca3dde Add `VmWriter::fill_zeros` 2025-08-10 16:40:11 +08:00
Ruihan Li d99c18d0be Remove `VmWriter::fill` 2025-08-10 16:40:11 +08:00
Ruihan Li db79aa2453 Remove `VmReader::collect` 2025-08-10 16:40:11 +08:00
Ruihan Li 6e597b40af Remove unsafe code in `mm/test.rs` 2025-08-10 16:40:11 +08:00
Ruihan Li 05990e743e Reimplement PCI BAR detection methods 2025-08-08 09:02:34 +08:00
Zejun Zhao b20d8461fd Fix discovery and access of PCIe (MMIO) configuration space 2025-08-06 02:11:21 +08:00
Zejun Zhao 19f7eea68b Don't assume SVPBMT's existence 2025-08-06 02:11:21 +08:00
Zejun Zhao 26b7428c8e Construct `IoMemAllocator` on RISC-V platforms 2025-08-06 02:11:21 +08:00
jiangjianfeng 4e78653b5b Bump project version to 0.16.0 2025-08-05 14:24:14 +08:00
Wang Siyuan ffdfd01925 Refactor the core scheduling logic in OSTD 2025-08-05 13:37:01 +08:00
Wang Siyuan 3ebb5a25b2 Refactor task schedulers to conform with the new semantics 2025-08-05 13:37:01 +08:00
Tate, Hongliang Tian 659f079c2d Revise the doc of OSTD's scheduling module 2025-07-29 21:58:23 +08:00
Ruihan Li d73f1016a1 Set softfloat targets for ARM/LoongArch/RISC-V 2025-07-29 11:13:59 +08:00
王英泰 0370f8fdf3 Update the init of pci device for LoongArch 2025-07-25 17:37:24 +08:00
王英泰 3391863312 Add the partial support for interrupt in LoongArch 2025-07-25 17:37:24 +08:00
王英泰 7bf716162a Finish the arch section for LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 8b8bbad996 Add the pci section for LoongArch in OSTD and kernel 2025-07-25 17:37:24 +08:00
王英泰 369c8656ee Add the io section for LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 7e9f418caa Add the qemu exit method for LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 25bbdd991f Add the irq section for LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 3824af8c89 Add the trap section for LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 b5c3eb8be8 Add the timer section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 93c562f5d2 Add the task section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 e4db73e1a0 Add the mm section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 d3538ec6df Add the iommu section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 c81ed0162c Add the device section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 91e7785915 Add the cpu section of LoongArch in OSTD and kernel 2025-07-25 17:37:24 +08:00
王英泰 ce22374b50 Add the boot section of LoongArch in OSTD 2025-07-25 17:37:24 +08:00
王英泰 b0b242edbc Add the temporary panic support for LoongArch 2025-07-25 17:37:24 +08:00
Hsy-Intel 24d56cfde7 adjust feature enabling sequence and fix xsave size function 2025-07-22 17:15:53 +08:00
Marsman1996 b04d62ae71 Use official minicov and add unit test for coverage feature 2025-07-22 10:31:56 +08:00
YanWQ-monad 79335b272f Add coverage support 
Co-authored-by: Marsman1996 <lqliuyuwei@outlook.com>
 2025-07-22 10:31:56 +08:00
Zhang Junyang 6a4d8d113f Fix missing updates of page table `Entry::pte` 
Co-authored-by: Xungan2 <2100012996@stu.pku.edu.cn>
 2025-07-21 13:42:38 +08:00
Ruihan Li bc7515389b Create a RISC-V boot code and data section 2025-07-21 10:01:02 +08:00
Ruihan Li e475009fe7 Optimize the x86 binary size 2025-07-21 10:01:02 +08:00
jiangjianfeng 424fcda239 Use iret instead of sysret if the context is not clean 2025-07-20 22:22:20 +08:00
Qingsong Chen 6cd53fbb8a Refactor FPU context using pre_schedule_handler 2025-07-18 11:40:16 +08:00
Ruihan Li cdd7950d2e Remove some variants in `ostd::Error` 2025-07-15 23:05:30 +08:00
Ruihan Li e5c5bc7992 Clarify safety comments in `dyn_cpu_local.rs` 2025-07-11 14:10:46 +08:00
jiangjianfeng 665de6bd35 Make RISC-V code compile under new exception APIs 2025-07-09 10:49:43 +08:00
jiangjianfeng 7f3ca86467 Refactor x86 exception related code 2025-07-09 10:49:43 +08:00
Ruihan Li 801ab865b7 Make paths of `TrapFrame` unique 2025-07-05 18:19:26 +08:00
Ruihan Li 0fce977b40 Clean up `trapframe` items 2025-07-05 18:19:26 +08:00
Ruihan Li 6f2725419f Always clear the need-preempt flag 2025-07-04 19:14:31 +08:00
Wang Siyuan a13297ae4c Add fields in `/proc/*/stat` and `/proc/*/status` 2025-07-02 20:13:47 +08:00
Ruihan Li ac0d92d878 Fix minor issues of the CPU extension module 2025-07-02 07:54:40 +08:00
jiangjianfeng 49ef0e9f7a Change the documentation website of OSTD 2025-07-01 17:07:28 +08:00
jiangjianfeng 2e09957ef9 Fix documentation check errors 2025-07-01 17:07:28 +08:00
jiangjianfeng dc26e18310 Depend on int-to-c-enum instead of num crate 2025-06-30 15:48:40 +08:00