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asterinas
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665 Commits

Author SHA1 Message Date
Zhang Junyang 8096249765 Add a lock before capturing coverage 2025-11-20 14:36:30 +08:00
Ruihan Li 668876aeee Check the existence of i8042 and RTC CMOS 2025-11-19 15:39:49 +08:00
Ruihan Li bbe0e3f3bb Reimplement `RtcCmos` 2025-11-19 15:39:49 +08:00
Zejun Zhao 902106eb2e Allow SBI system_reset to fail 2025-11-18 14:46:16 +08:00
Tao Su 314fbe285a Check size and alignment for untyped metadata 2025-11-17 15:26:45 +08:00
Zhang Junyang 9c8a8f8df9 Remove `PageProperty::new_absent` 2025-11-16 18:18:26 +08:00
Zejun Zhao 963771fd32 Skip management hart while enumerating usable harts 2025-11-16 11:23:46 +08:00
Ruihan Li 69dc2479db Rename initialization methods 2025-11-16 11:09:08 +08:00
Ruihan Li 19b1fe36c5 Remove outdated safety comments 2025-11-16 11:09:08 +08:00
Zhang Junyang e0dd647756 Remove `TIMER_IRQ_NUM` for RISC-V 2025-11-14 10:14:03 +08:00
Zhang Junyang b86aeffd53 Correct some hart ID usage 2025-11-14 10:14:03 +08:00
Zhang Junyang 8148072984 Upgrade the `riscv` crate to fix the ssoft handling 
3c61863630
 2025-11-14 10:14:03 +08:00
Zhang Junyang 7e7f6741c6 Setup RISC-V AP timer 2025-11-14 10:14:03 +08:00
Zhang Junyang 7d21144da6 Add RISC-V IPI 2025-11-14 10:14:03 +08:00
Zhang Junyang 73c0f34947 Remove `Arc` guards of locks that have no users 2025-11-13 23:32:36 +08:00
Zhang Junyang b69feb97c9 Rename some `init` to `init_on_cpu` 2025-11-12 17:57:36 +08:00
Zhang Junyang 14aee3d5cc Unify and fix RISC-V symbol names 2025-11-12 17:39:04 +08:00
Ruihan Li 121da78aa2 Revise names and comments in `ostd::arch` 2025-11-12 14:43:14 +08:00
Ruihan Li d447fe0ca8 Update APICs' MMIO region sizes 2025-11-05 22:48:40 +08:00
Zhang Junyang 3b4569e14d Add RISC-V SMP boot entrypoint 2025-11-02 21:23:32 +08:00
Zejun Zhao 431b6fdff7 Make riscv64's `PageTableEntry::set_prop` recognize A/D bit 2025-10-31 08:52:34 +08:00
Ruihan Li 9c70ac0f0a Mark `sync_dma_range` as `unsafe` 2025-10-30 17:04:45 +08:00
Ruihan Li d487e42b7c Reunify the style of defining `arch` modules 2025-10-30 17:04:45 +08:00
Zejun Zhao 6af524b451 Support RISC-V Sv39 Paging mode 2025-10-30 14:51:37 +08:00
Zejun Zhao 577d8294d0 Use exception table to recover in RISC-V page fault handler 2025-10-30 11:27:08 +08:00
Zejun Zhao 79992c66de Implement fallible memory operations on RISC-V platform 2025-10-30 11:27:08 +08:00
Zejun Zhao 629b053ea8 Make exception table arch-agnostic 2025-10-30 11:27:08 +08:00
Zejun Zhao bfcb1d2c00 Implement `DmaStream::sync` on RISC-V platforms 2025-10-30 10:47:53 +08:00
Zejun Zhao 39a541fdeb Add RISC-V FPU support 2025-10-29 13:24:30 +08:00
Zejun Zhao 32581caa7a Skip management hart when detecting available extensions 2025-10-28 09:32:12 +08:00
Ruihan Li 4996146a24 Add `.type` and `.size` directives 2025-10-28 09:21:44 +08:00
Ruihan Li e61c8ce56a Unify styles of assembly code 2025-10-28 09:21:44 +08:00
Ruihan Li a6b01501ac Load local addresses and define constants 2025-10-28 09:21:44 +08:00
Ruihan Li 0b597d84a0 Use `IoMem<Sensitive>` in local APIC 2025-10-28 09:12:02 +08:00
Ruihan Li d42208b591 Use `IoMem<Sensitive>` in I/O APIC 2025-10-28 09:12:02 +08:00
Zejun Zhao dd8de9f381 Handle kernel page fault on RISC-V platforms 2025-10-27 11:25:59 +08:00
Zejun Zhao 1e183825d3 Refactor RISC-V exception-related code 2025-10-27 11:25:59 +08:00
Arthur Paulino 6a67807fd0 Implement `IdSet::iter_in` 
This patch enables more expressive ways to slice and iterate over
the `Id`s in an `IdSet` with `IdSet::iter_in`, which takes an arbitrary
`IdSetSlicer`.

`IdSet::iter_in` efficiently slices out unintended inner parts and
then, within the remaining parts, skips inactive bits by using
`BitSlice::iter_ones` from the `bitvec` crate.

It also delivers several implementations of `IdSetSlicer` so OSTD
consumers can represent `Id` ranges ergonomically.

In the Asterinas kernel, `CpuSet::iter_in` enables a cleaner way to
define an interator that cycles over the CPUs.
 2025-10-25 11:23:13 +08:00
Zejun Zhao 8251d48bf2 Add RISC-V PLIC support 2025-10-24 16:28:41 +08:00
Zejun Zhao 752f040368 Implement security-sensitive IoMem 2025-10-24 16:28:41 +08:00
Zejun Zhao 68721b2365 Activate kernel page table earlier on BSP 2025-10-24 16:28:41 +08:00
Zejun Zhao 72dbaa4b38 Use absolute time when setting up timer interrupt using SBI 2025-10-24 11:32:28 +08:00
Tate, Hongliang Tian c44e45ea78 Add the `IdSet<I>` utility type 2025-10-22 14:29:52 +08:00
Tate, Hongliang Tian d9a74c6cfc Remove unit tests that instantiate invalid CpuId 2025-10-22 14:29:52 +08:00
Tate, Hongliang Tian 6942bc6643 Extract CpuId into a sub-module of the `cpu` module 
This prevents creating invalid instances of `CpuId` within the `cpu`
module by using `CpuId(raw_id)` directly. Another benefit is to
make the `cpu` module more modular, which is good for readability
and maintainability.
 2025-10-22 14:29:52 +08:00
Yuke Peng 23f14df21f [sched] Fix the missing of preemption check in RISC-V & loongarch 2025-10-20 11:17:24 +08:00
Ruihan Li 384e5bc70d Fix an off-by-one bug in the trap frame 2025-10-16 22:28:29 +09:00
Ruihan Li fe7dc1f83e Adjust some symbol names 2025-10-16 22:28:29 +09:00
Ruihan Li 3673049620 Resolve minor issues in `ostd::src::arch` 2025-10-16 21:46:40 +09:00
Ruihan Li bc6ef5231b Reorangize `ostd::arch::irq` 2025-10-16 21:46:40 +09:00