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72 Commits

Author SHA1 Message Date
Ruihan Li 48c5891543 Remove `VecDeque::try_with_capacity` 2026-01-02 16:47:03 -08:00
Ruihan Li dccf23e283 Redesign inode extensions 2026-01-02 16:47:03 -08:00
Zhang Junyang c7a2c81366 Miscellaneous clippy fixes for Rust 2024 2025-12-09 09:23:58 +08:00
Ruihan Li 13afca6441 Add `i8042.exist` to override ACPI flags 2025-12-07 09:52:42 +08:00
Zhenchen Wang 09665a7692 Implement inotify file and syscalls 
Signed-off-by: Zhenchen Wang <m202372036@hust.edu.cn>
 2025-12-01 20:05:18 +08:00
wyt8 9a0f63b33e Modify the import of modules in kernel to remove dependencies of lib.rs 2025-11-10 10:53:08 +08:00
Tate, Hongliang Tian 06f798908a Extract kernel initialization code into a module 2025-11-10 10:53:08 +08:00
wyt8 05287667c3 Ensure the idle tasks do not sleep or block 2025-11-10 10:53:08 +08:00
Tao Su eb4edd25e8 Add TSM module 2025-10-31 08:53:27 +08:00
Ruihan Li d487e42b7c Reunify the style of defining `arch` modules 2025-10-30 17:04:45 +08:00
Arthur Paulino 6a67807fd0 Implement `IdSet::iter_in` 
This patch enables more expressive ways to slice and iterate over
the `Id`s in an `IdSet` with `IdSet::iter_in`, which takes an arbitrary
`IdSetSlicer`.

`IdSet::iter_in` efficiently slices out unintended inner parts and
then, within the remaining parts, skips inactive bits by using
`BitSlice::iter_ones` from the `bitvec` crate.

It also delivers several implementations of `IdSetSlicer` so OSTD
consumers can represent `Id` ranges ergonomically.

In the Asterinas kernel, `CpuSet::iter_in` enables a cleaner way to
define an interator that cycles over the CPUs.
 2025-10-25 11:23:13 +08:00
Yang Zhichao 6a662a0d85 Add the `CpuTimeStats` module for CPU time statistics. 2025-09-27 21:02:23 +08:00
Ruihan Li 472edcf795 Clean up unnecessary features 2025-09-24 15:41:07 +08:00
Chen Chengjun bacbe58ff3 Modify the related logics in the initial phase 2025-09-24 08:07:25 +08:00
Zejun Zhao 2e46edb68d Register some timer callbacks on all CPUs 2025-09-19 14:40:33 +08:00
Qingsong Chen 8bc0013801 Add stage support for init_component macro 2025-09-18 12:11:44 +08:00
Tate, Hongliang Tian 8d2fec7873 Introduce ASCII art representations of the Asterinas logo 2025-09-17 22:44:40 +08:00
Ruihan Li 9de70e38de Add the `arch::cpu::cpuid` module 2025-09-10 12:10:40 +08:00
Ruihan Li 652657fba5 Drop duplicate public re-exports 2025-09-10 12:10:40 +08:00
jiangjianfeng 83b6e2da5c Add basic namespace framework 2025-09-02 09:47:41 +08:00
Zejun Zhao f4b05597cd Init vDSO singleton in the first kthread 2025-08-31 23:57:17 +08:00
Ruihan Li a6d37f0e79 Mark all kernel modules as private 2025-08-26 18:02:56 +08:00
Chen Chengjun b1bbd6c3fe Optimize the initialization logic during Asterinas init phase 2025-08-26 14:36:59 +08:00
Zejun Zhao e68631d1b6 Implement arch-aware vDSO 2025-08-23 12:38:22 +08:00
王英泰 5c4b3fdd19 Finish the arch section for LoongArch in kernel 2025-07-25 17:37:24 +08:00
Chen Chengjun a8b4c23319 Add SysTreeInodeTy trait to abstract the view part of MVC arch 2025-07-14 20:35:05 +08:00
Ruihan Li abbf152d74 Re-enable framebuffer 2025-07-03 17:47:56 +08:00
Ruihan Li 6146434f15 Unify the styles of the `arch` modules 2025-06-30 15:43:41 +08:00
Ruihan Li 35e0918bce Don't race between enabling IRQs and halting CPU 2025-06-23 22:53:35 +08:00
Ruihan Li 56e9824dd1 Make `current_cpu_racy` a method of `CpuId` 2025-05-29 10:33:02 +08:00
jiangjianfeng 89e8cd5936 Move functions related to spawning the init process to a seperate module 2025-05-09 13:19:57 +08:00
Ruihan Li 50ba735e96 Handle negative P(G)IDs via `cast_(un)signed` 2025-05-09 11:38:01 +08:00
Ruihan Li 7de9666e65 Retire incomplete features 2025-05-06 11:17:20 +08:00
Qingsong Chen 88f08de3af Refactor framebuffer 2025-04-29 19:48:45 +08:00
Zhang Junyang 85d4cdbbb0 Avoid excessive heap allocations in `sys_futex` 2025-04-15 21:56:15 +08:00
jiangjianfeng 3e66732889 Parse netlink message 2025-04-15 17:20:12 +08:00
Zhang Junyang 30ec0be210 Halt the idle CPUs 2025-03-21 21:19:50 +08:00
Chen Chengjun 048fd1077c Inject post_schedule/user_page_fault handler to OSTD 2025-03-20 14:20:47 +08:00
Zejun Zhao d71771e49a Re-enable CFS 2025-02-11 10:51:12 +08:00
Ruihan Li 0dca168717 Use `#[expect(lint)]`, not `#[allow(lint)]` 2025-02-08 15:10:04 +08:00
Zhang Junyang 5ea366bced Move kcmdline parsing out of OSTD 2025-01-02 10:41:51 +08:00
Zhang Junyang 397ce9652f Refactor boot modules to make heap allocation explicit 2025-01-02 10:41:51 +08:00
Ruihan Li 35c20620bc Rewrite `exit()` and `exit_group()` 2024-12-17 19:36:38 +08:00
Zhang Junyang 285dde5546 Set affinity for BSP idle thread 2024-12-16 19:15:59 +08:00
Chen Chengjun 0cb2ea562e Inject the logger for Asterinas 2024-12-04 13:24:06 +08:00
Chen Chengjun b17cbb2408 Finish bootstrap once finishing the initialization of OSTD 2024-12-04 13:24:06 +08:00
徐启航 878f3f3760 Scheduling class support 2024-12-04 09:36:41 +08:00
Marsman1996 6d3bb5a9d0 Fix compile error caused by updated `Step::steps_between` in Rust 2024-12-01 18:56:28 +08:00
Qingsong Chen f762eb8913 Remove the `lazy_static` dependency 2024-11-28 15:28:30 +08:00
Ruihan Li a4a8807a20 Remove `KernelThreadExt` 2024-11-13 21:44:37 +08:00