c7429a7a5c
Allow to repurpose `?Sized` metadata
2025-09-19 11:27:14 +08:00
bf6efbabc7
Remove unused `has_guard_page` boolean
2025-09-14 22:42:48 +08:00
44145cdb53
Set CR0.WP/NE/MP explicitly to fix AP behavior
2025-09-12 08:43:35 +08:00
75ca7e0377
Add the `arch::cpu::extension` module
2025-09-10 12:10:40 +08:00
9de70e38de
Add the `arch::cpu::cpuid` module
2025-09-10 12:10:40 +08:00
652657fba5
Drop duplicate public re-exports
2025-09-10 12:10:40 +08:00
2796c8d1ad
Add unit tests for the newly implemented methods related to `IoMem`
2025-09-05 10:47:43 +08:00
877581f1a6
Add OSTD support for mapping `IoMem` in userspace
2025-09-05 10:47:43 +08:00
5a38c61c49
Ensure that OSTD users cannot modify the `PrivilegedPageFlags` in `PageProperty`
2025-09-05 10:47:43 +08:00
e11227c8da
Move the `AVAIL1` flag from `PageFlags` to `PrivilegedPageFlags` in `PageProperty`
2025-09-05 10:47:43 +08:00
3b606f5b6c
Use `size_of`/`align_of` in the prelude
2025-09-04 09:26:56 +08:00
45b5bd39f1
Disable I/O APIC entries in initialization
2025-09-02 18:03:24 +08:00
4e2bdc65de
Refactor implicit `Arc` APIs for DMA
2025-09-02 17:53:55 +08:00
a6520880ab
Unify memory object slicing
2025-09-02 17:53:55 +08:00
eb69aa4fb9
Unify address and size APIs for memory objects
2025-09-02 17:53:55 +08:00
f56d2f3bad
`context.rs` enhancements
...
* Improve the phrasing of some docstrings and comments
* Add warning comments about attempts to validate memory addresses
at reader/writer instantiation time
* Create the `reader_writer` method for ergonomically instantiate
a reader/writer pair covering the same memory region. This method
is also slightly more efficient than calling `reader` and `writer`
separately
* Clean up `check_vaddr` for clarity and rename it to `check_vaddr_lowerbound`
for explicity
* Include the data length check before calling `check_vaddr_lowerbound`
in `atomic_load` and `atomic_fetch_update` for further consistency
with the delayed buffer validation
2025-09-01 11:16:37 +08:00
bf25806fca
Add an explicit end of call stack for x86_64 and loongarch64
2025-08-29 17:10:48 +08:00
3b0666449f
Use rust-analyzer for riscv64 and loongarch64 target
2025-08-29 16:57:06 +08:00
fc61f4d1b8
Use `IrqLine` abstraction for RISC-V timer interrupt
2025-08-29 10:49:48 +08:00
aeaf103166
Add an explicit end of call stack for x86_64
2025-08-28 17:26:23 +08:00
920ec7f521
Enable RISC-V stack unwinding on panic
2025-08-28 17:26:23 +08:00
924d87398a
Introduce `first_context_switch`
2025-08-20 20:12:38 +08:00
2d3cfb53e0
Swap `context_switch` arguments
2025-08-20 20:12:38 +08:00
85f17ff159
Replace `parse_u32` with `u32::from_str_radix`
2025-08-20 13:19:50 +08:00
6b6c64c591
Rename `atomic_update` to `atomic_fetch_update`
2025-08-20 13:17:57 +08:00
a73f210c7a
Make `wake_robust_futex` atomic
...
Replace `VmWriter::atomic_update` with `VmWriter::atomic_compare_exchange`,
which takes the old value for comparison and new value instead of a
closure to compute it. This version has one less unsafe call.
Then use `atomic_compare_exchange` to reimplement the looping logic
of `wake_robust_futex` and make it atomic.
2025-08-19 19:22:12 +08:00
fc5a12356a
Fix LOONGARCH clippy warnings
2025-08-19 19:20:54 +08:00
9507475102
Fix RISCV clippy warnings
2025-08-19 19:20:54 +08:00
1452aab69c
Optimize the space for `TlbFlushOp`s
2025-08-16 22:09:29 +08:00
d0b98130cf
Don't use `map` to return values
2025-08-16 22:09:29 +08:00
e4fafb13b1
Add atomic operations for VM readers/writers
2025-08-14 11:59:05 +08:00
6e6465942c
Clean up comments and visibility
2025-08-12 19:19:34 +08:00
bb279e6313
Clarify who loads the user TLS pointer
2025-08-12 19:19:34 +08:00
086a80c05f
Drop unsound TLS methods from `Task`
2025-08-12 19:19:34 +08:00
923982c2e5
Remove `user_ctx` from `Task`
2025-08-12 19:19:34 +08:00
695bb1a0a7
Synchronize `{pci,io}.rs` between architectures
2025-08-12 14:00:28 +08:00
d481b10f63
Polish the Rust doc of OSTD's logger module
2025-08-12 10:55:24 +08:00
597b0b5f25
Disable kernel traps before going to userspace
2025-08-10 17:09:22 +08:00
cdd28787ed
Replace `write_vals` by `fill_zeros` in `VmIo`
2025-08-10 16:40:11 +08:00
2700d88bef
Provide efficient `VmIo` with VM readers/writers
2025-08-10 16:40:11 +08:00
894b942a79
Avoid all `Pod::new_uninit`s in OSTD
2025-08-10 16:40:11 +08:00
275fd21650
Retire missing `ptr::sub` in `mm/io.rs`
2025-08-10 16:40:11 +08:00
aa7aca3dde
Add `VmWriter::fill_zeros`
2025-08-10 16:40:11 +08:00
d99c18d0be
Remove `VmWriter::fill`
2025-08-10 16:40:11 +08:00
db79aa2453
Remove `VmReader::collect`
2025-08-10 16:40:11 +08:00
6e597b40af
Remove unsafe code in `mm/test.rs`
2025-08-10 16:40:11 +08:00
05990e743e
Reimplement PCI BAR detection methods
2025-08-08 09:02:34 +08:00
b20d8461fd
Fix discovery and access of PCIe (MMIO) configuration space
2025-08-06 02:11:21 +08:00
19f7eea68b
Don't assume SVPBMT's existence
2025-08-06 02:11:21 +08:00
26b7428c8e
Construct `IoMemAllocator` on RISC-V platforms
2025-08-06 02:11:21 +08:00
4e78653b5b
Bump project version to 0.16.0
2025-08-05 14:24:14 +08:00
ffdfd01925
Refactor the core scheduling logic in OSTD
2025-08-05 13:37:01 +08:00
3ebb5a25b2
Refactor task schedulers to conform with the new semantics
2025-08-05 13:37:01 +08:00
659f079c2d
Revise the doc of OSTD's scheduling module
2025-07-29 21:58:23 +08:00
d73f1016a1
Set softfloat targets for ARM/LoongArch/RISC-V
2025-07-29 11:13:59 +08:00
0370f8fdf3
Update the init of pci device for LoongArch
2025-07-25 17:37:24 +08:00
3391863312
Add the partial support for interrupt in LoongArch
2025-07-25 17:37:24 +08:00
7bf716162a
Finish the arch section for LoongArch in OSTD
2025-07-25 17:37:24 +08:00
8b8bbad996
Add the pci section for LoongArch in OSTD and kernel
2025-07-25 17:37:24 +08:00
369c8656ee
Add the io section for LoongArch in OSTD
2025-07-25 17:37:24 +08:00
7e9f418caa
Add the qemu exit method for LoongArch in OSTD
2025-07-25 17:37:24 +08:00
25bbdd991f
Add the irq section for LoongArch in OSTD
2025-07-25 17:37:24 +08:00
3824af8c89
Add the trap section for LoongArch in OSTD
2025-07-25 17:37:24 +08:00
b5c3eb8be8
Add the timer section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
93c562f5d2
Add the task section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
e4db73e1a0
Add the mm section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
d3538ec6df
Add the iommu section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
c81ed0162c
Add the device section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
91e7785915
Add the cpu section of LoongArch in OSTD and kernel
2025-07-25 17:37:24 +08:00
ce22374b50
Add the boot section of LoongArch in OSTD
2025-07-25 17:37:24 +08:00
b0b242edbc
Add the temporary panic support for LoongArch
2025-07-25 17:37:24 +08:00
24d56cfde7
adjust feature enabling sequence and fix xsave size function
2025-07-22 17:15:53 +08:00
b04d62ae71
Use official minicov and add unit test for coverage feature
2025-07-22 10:31:56 +08:00
79335b272f
Add coverage support
...
Co-authored-by: Marsman1996 <lqliuyuwei@outlook.com>
2025-07-22 10:31:56 +08:00
6a4d8d113f
Fix missing updates of page table `Entry::pte`
...
Co-authored-by: Xungan2 <2100012996@stu.pku.edu.cn>
2025-07-21 13:42:38 +08:00
bc7515389b
Create a RISC-V boot code and data section
2025-07-21 10:01:02 +08:00
e475009fe7
Optimize the x86 binary size
2025-07-21 10:01:02 +08:00
424fcda239
Use iret instead of sysret if the context is not clean
2025-07-20 22:22:20 +08:00
6cd53fbb8a
Refactor FPU context using pre_schedule_handler
2025-07-18 11:40:16 +08:00
cdd7950d2e
Remove some variants in `ostd::Error`
2025-07-15 23:05:30 +08:00
e5c5bc7992
Clarify safety comments in `dyn_cpu_local.rs`
2025-07-11 14:10:46 +08:00
665de6bd35
Make RISC-V code compile under new exception APIs
2025-07-09 10:49:43 +08:00
7f3ca86467
Refactor x86 exception related code
2025-07-09 10:49:43 +08:00
801ab865b7
Make paths of `TrapFrame` unique
2025-07-05 18:19:26 +08:00
0fce977b40
Clean up `trapframe` items
2025-07-05 18:19:26 +08:00
6f2725419f
Always clear the need-preempt flag
2025-07-04 19:14:31 +08:00
a13297ae4c
Add fields in `/proc/*/stat` and `/proc/*/status`
2025-07-02 20:13:47 +08:00
ac0d92d878
Fix minor issues of the CPU extension module
2025-07-02 07:54:40 +08:00
49ef0e9f7a
Change the documentation website of OSTD
2025-07-01 17:07:28 +08:00
2e09957ef9
Fix documentation check errors
2025-07-01 17:07:28 +08:00
dc26e18310
Depend on int-to-c-enum instead of num crate
2025-06-30 15:48:40 +08:00
c7f489b726
Bump version to 0.15.2
2025-06-26 08:16:22 +08:00
780b35848e
Remove `SameSizeAs`
2025-06-25 15:57:23 +08:00
59e7d268d7
Tidy up the `PageTableEntryTrait` comments
2025-06-25 15:57:23 +08:00
35e0918bce
Don't race between enabling IRQs and halting CPU
2025-06-23 22:53:35 +08:00
b96c8f9ed2
Make `ostd::trap::irq` public
2025-06-23 22:53:35 +08:00
a1accf4304
Do some miscellaneous page table cleanups
2025-06-22 16:46:07 +08:00
a3c5ab8cb4
Move virtio-mmio bus outside OSTD
2025-06-19 15:10:42 +08:00
238b89da46
Create `IrqChip` abstraction
2025-06-19 15:10:42 +08:00
76377f701b
Restrict some module visibility
2025-06-19 15:10:42 +08:00
7a398167cf
ostd: update multiboot2 + use constant
2025-06-16 16:10:54 +08:00
d5b12532a8
Require `T: Send` for `CpuLocal<T, S>`
2025-06-16 12:09:13 +08:00
c2a49bca7c
Temporary fix for TDX MMIO assert issue
2025-06-13 10:31:25 +08:00
614ac85bd4
Bump the project version
2025-06-12 22:35:54 +08:00
e78927b449
Manage frame tracking outside the page table
2025-06-12 22:34:46 +08:00
2c917ba383
Unify page table template parameters
2025-06-12 22:34:46 +08:00
22ccfb1f2b
Move COW out of OSTD
2025-06-12 22:34:46 +08:00
3e32a38316
Add sys_close_range
2025-06-11 19:56:12 +08:00
492898d1d5
Fix the detection of RISC-V SSTC extension
2025-06-11 16:54:59 +08:00
bd24ed9ba7
Support RISC-V ISA extension detection
2025-06-11 16:54:59 +08:00
ead5a70444
Replace proc_macro APIs with proc_macro2 APIs in ostd_macros
2025-06-09 18:51:35 +08:00
58e4f45bb1
Add per-CPU counters and track RSS for each `Vmar`
2025-06-03 23:24:32 +08:00
dfd3042276
Add dynamically-allocated CPU-local objects
2025-06-03 23:24:32 +08:00
f24bc718fa
Use `IoMem::acquire` in the virtio-mmio bus
2025-06-03 21:01:03 +08:00
3790f616fd
Rename `PageProperty::new` to `PageProperty::new_user`
2025-06-03 18:42:53 +08:00
e669d38d2d
Clear User bits of non-leaf PTE in boot pagetable
2025-06-03 18:42:53 +08:00
3f8dbe6990
Add `unsafe` with trivial cleanups
2025-06-03 15:00:13 +08:00
3bc4424a5b
Add `unsafe` with explained comments
2025-06-03 15:00:13 +08:00
619814e652
Add `unsafe` with caller-upheld comments
2025-06-03 15:00:13 +08:00
31dbae5330
Add `unsafe` for acquring I/O memory/port
2025-06-03 15:00:13 +08:00
e1e5f9f575
Remove `transmute` in `Vm{Reader,Writer}`
2025-06-03 15:00:13 +08:00
2c21b2a3a8
Use `wrapping_add` to add userspace pointers
2025-06-03 15:00:13 +08:00
899a1424c0
Tweak RCU visiblity and safety
2025-06-03 15:00:13 +08:00
2b00fe9e45
Mark `root_paddr()` safe
2025-06-03 15:00:13 +08:00
1ed023f413
Fix the level comparison in `dfs_mark_stray_and_unlock`
2025-06-02 23:49:15 +08:00
72fb0752ae
Allow `dyn InAtomicMode` as `AsAtomicModeGuard`
2025-06-01 15:06:53 +08:00
6dc0189e43
Remove unnecssary overflow checks
2025-05-30 16:34:33 +08:00
282a0f216f
Clarify safety conditions in `tdx_guest.rs`
2025-05-30 16:34:33 +08:00
ffb4097436
Add RISC-V timer support
2025-05-29 19:51:02 +08:00
56e9824dd1
Make `current_cpu_racy` a method of `CpuId`
2025-05-29 10:33:02 +08:00
758c80c321
Pull code from `arch/*/irq.rs` to `trap/irq.rs`
2025-05-25 10:19:17 +08:00
dd9fc81a81
Add some TODOs in IOMMU initialization
2025-05-25 09:54:16 +08:00
d2ff5fc1a9
Check SAGAW before enabling DMA remapping
2025-05-25 09:54:16 +08:00
79b3f68892
Make the RCU lifetime of page tables explicit
2025-05-24 17:42:17 +08:00
ef81100958
Add `InAtomicMode: Debug`
2025-05-24 17:42:17 +08:00
3472560c55
Make TLB issuing less contended
2025-05-24 17:42:17 +08:00
54fbdcf059
Implement the stray marking in PT to ensure serializability
2025-05-24 17:42:17 +08:00
5b7637eac3
Remove the activation lock and use RCU to protect PT removal
2025-05-24 17:42:17 +08:00
d873e121ff
DFS lock protocol for the page table
2025-05-24 17:42:17 +08:00
d4afe3a035
Avoid Rust references of IRT entries
2025-05-23 10:38:57 +08:00
d4872af3c7
Refactor interrupt remapping in OSTD
2025-05-22 15:21:16 +08:00
95744692a5
Remove unnecessary #[inline] attributes
2025-05-22 12:19:21 +08:00
e81053b9dc
Remove unnecessary `_rdtsc` uses
2025-05-21 21:00:02 +08:00
a18e72b495
Implement `apic::get_or_init` using `Once`
2025-05-21 21:00:02 +08:00
0a27a1f37b
Don't treat APIC IDs as CPU IDs
2025-05-21 09:27:25 +08:00
d7cd0244ff
Use Rust types to store `PerApRawInfo`
2025-05-21 09:27:25 +08:00
ad6aa4960c
Bump the project version
2025-05-12 22:01:05 +08:00
02463ff161
Bump xmas-elf
2025-05-12 22:00:13 +08:00
690f87f311
Add `RcuDrop`
2025-05-12 16:12:01 +08:00
9cb28f8dd0
`FrameRef` for all types of frames
2025-05-11 15:42:46 +08:00
773b965767
Allow specifying orderings when loading/storing `AtomicCpuSet`s
2025-05-11 15:29:17 +08:00
d3e4f175cd
Fix the memory leak on large heap slot dealloc
2025-05-08 19:49:42 +08:00
18df0f6ec9
Fix the linear mapping size if the IO range is high
2025-05-06 23:33:05 +08:00
1da723c0de
Replace the original XArray with RCU-based XArray
2025-04-30 20:59:15 +08:00
ef898e572c
Move `tdx_guest::unprotect_gpa_range` into IoMem creation
2025-04-29 16:31:08 +08:00
04a8fccd2f
Add Framebuffer region into filter in `IoMemAllocatorBuilder`
2025-04-29 14:49:58 +08:00
9b4417e29a
Pin the unwinding crate version to 0.2.5
2025-04-29 12:33:55 +08:00
bf4950965b
Adjust `unsafe` blocks in `syscall.rs`
2025-04-22 20:52:15 +08:00
c9a7d501b2
Rewrite `trap/idt.rs`
2025-04-22 20:52:15 +08:00
8c30b4b942
Rewrite `trap/gdt.rs`
2025-04-22 20:52:15 +08:00
e06509e380
Make some `unsafe` blocks shorter
2025-04-22 20:52:15 +08:00
c3dd607777
Introduce RCU-based XArray
2025-04-19 16:48:15 +08:00
6c0827b681
Add ktest cases for vmspace
2025-04-19 14:00:21 +08:00
52e0776591
Add more page table cases
2025-04-19 13:59:43 +08:00
3aa1079ca6
Clarify the usage of ostd::arch
2025-04-18 13:26:16 +08:00
5630fa8b36
Disable RISC-V FPU by default
2025-04-18 13:26:16 +08:00
14b8c48859
Adjust RISC-V's implementation for recent changes
2025-04-18 13:26:16 +08:00
b097060c5e
Clean up RISC-V-specific boot code
2025-04-18 13:26:16 +08:00
d39ab61d68
Remove unnecessary usage of cfg_if macro
2025-04-18 13:26:16 +08:00
47ee012e6b
Make IoPort x86-specific
2025-04-18 13:26:16 +08:00
e4aa261c48
Make if_tdx_enabled macro x86-specific
2025-04-18 13:26:16 +08:00
dd67a9a175
Clean up code
2025-04-18 13:26:16 +08:00
1130933546
Remove unused `device.rs` file in mmio
2025-04-17 19:11:27 +08:00
d6e40933b8
Move the log lock to a better location
2025-04-16 21:59:24 +08:00
67e5e5a651
Remove the unused serial input
2025-04-16 21:59:24 +08:00
74ffe72cad
Refactor the initialization of `IoPortAllocator`
2025-04-16 10:09:19 +08:00
a2caedafda
Remove the system device's IO port access
2025-04-16 10:09:19 +08:00
92b7961df1
Introduce macros that allow system device driver to remove sensitive ports
...
test
test
2025-04-16 10:09:19 +08:00
a038b8401b
Rename `allocator.rs` to `io.rs`
2025-04-16 10:09:19 +08:00
d359cc44d6
Implement `IoPortAllocator`
2025-04-16 10:09:19 +08:00
f89b248f3b
Change IoPort to architecture-independent
2025-04-16 10:09:19 +08:00
9804f053f2
Add guard which disables bottom half
2025-04-15 14:54:51 +08:00
e0bda4677c
Remove `Send` trait bound from `NonNullPtr`
2025-04-15 10:10:42 +08:00
de69fd6c31
Add support for `Rcu` to store an `Either`
2025-04-15 10:10:42 +08:00
a1f81df263
Remove `ostd/src/mm/offset.rs`
2025-04-15 09:15:22 +08:00
1a1d9bfb60
Split `ostd/util.rs`
2025-04-15 09:15:22 +08:00
50924d6693
Stop sharing kernel boot PDPTs and linear boot PDPTs
2025-04-14 16:20:35 +08:00
784628e238
Add ktest cases for io interfaces
2025-04-10 15:36:58 +08:00
6aba270a9b
Enable RCU to support Weak
2025-04-10 14:42:51 +08:00
a21e895102
Enable RCU to read reference to stored pointers
2025-04-10 14:42:51 +08:00
36f6f9bcd4
Fix the AVX initialization bugs on lower-end CPUs
2025-04-10 09:52:38 +08:00
5ed5647d42
Update outdated comments near `switch_to_task`
2025-04-06 09:49:23 +08:00
d378dc51ff
Enable `IA32_EFER.NXE` earlier in AP
2025-04-05 23:50:42 +08:00
396ead6fbd
Fix safety reasoning about `get_on_cpu`
2025-04-03 10:50:22 +08:00
c17a3eaa0b
Revise safety comments in `single_instr.rs`
2025-04-03 10:50:22 +08:00
5651b93af0
Turn `GS.base` validity into a global invariant
2025-04-03 10:50:22 +08:00
b52d841ac1
Revise safety comments for booting APs
2025-04-03 10:50:22 +08:00
600f13ef78
Enforce a task not switched to multiple CPUs
2025-04-02 20:51:42 +08:00
e040dda7a4
Ignore unusable regions for `max_paddr`
2025-04-02 11:50:33 +08:00
8f72192f07
Ignore invalid APIC entries
2025-04-02 11:48:52 +08:00
Ruihan Li
Zhe Tang
Zhe Tang
Zhang Junyang
Arthur Paulino
Zejun Zhao
Chen Chengjun
Tate, Hongliang Tian
jiangjianfeng
Wang Siyuan
王英泰
Hsy-Intel
Marsman1996
YanWQ-monad
Qingsong Chen
Philipp Schuster
Cautreoxit
Yuke Peng
stuuupidcat
Fabing Li