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arch
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Make riscv64's `PageTableEntry::set_prop` recognize A/D bit
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2025-10-31 08:52:34 +08:00 |
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boot
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Use `IoMem<Sensitive>` in local APIC
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2025-10-28 09:12:02 +08:00 |
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cpu
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Implement `IdSet::iter_in`
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2025-10-25 11:23:13 +08:00 |
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io
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Use `IoMem<Sensitive>` in I/O APIC
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2025-10-28 09:12:02 +08:00 |
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irq
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Add RISC-V PLIC support
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2025-10-24 16:28:41 +08:00 |
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mm
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Mark `sync_dma_range` as `unsafe`
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2025-10-30 17:04:45 +08:00 |
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sync
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Add the `IdSet<I>` utility type
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2025-10-22 14:29:52 +08:00 |
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task
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Implement `IdSet::iter_in`
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2025-10-25 11:23:13 +08:00 |
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timer
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Make per-CPU callbacks explicit
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2025-09-20 11:50:50 +08:00 |
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util
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Implement `IdSet::iter_in`
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2025-10-25 11:23:13 +08:00 |
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bus.rs
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Extract `PciDeviceLocation` in ostd into PCI component
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2025-09-21 10:32:23 +08:00 |
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console.rs
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…
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coverage.rs
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Use official minicov and add unit test for coverage feature
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2025-07-22 10:31:56 +08:00 |
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error.rs
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Remove some variants in `ostd::Error`
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2025-07-15 23:05:30 +08:00 |
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ex_table.rs
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Use exception table to recover in RISC-V page fault handler
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2025-10-30 11:27:08 +08:00 |
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lib.rs
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Reunify the style of defining `arch` modules
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2025-10-30 17:04:45 +08:00 |
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logger.rs
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Polish the Rust doc of OSTD's logger module
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2025-08-12 10:55:24 +08:00 |
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panic.rs
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Rename ostd::trap to ostd::irq
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2025-09-19 15:05:50 +08:00 |
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prelude.rs
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Unify address and size APIs for memory objects
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2025-09-02 17:53:55 +08:00 |
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smp.rs
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Implement `IdSet::iter_in`
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2025-10-25 11:23:13 +08:00 |
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user.rs
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Drop duplicate public re-exports
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2025-09-10 12:10:40 +08:00 |
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