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Fix whitespaces.

This commit is contained in:
Ulrich Drepper 2010-06-14 17:15:33 -07:00
parent 158db12267
commit 1dc242356a
4 changed files with 37 additions and 37 deletions
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32
sysdeps/powerpc/powerpc32/power7/memcmp.S
View File

@ -68,7 +68,7 @@ EALIGN (BP_SYM(memcmp),4,0)
/* At this point we know both strings have the same alignment and the /* At this point we know both strings have the same alignment and the
compare length is at least 8 bytes. rBITDIF contains the low order compare length is at least 8 bytes. rBITDIF contains the low order
2 bits of rSTR1 and cr5 contains the result of the logical compare 2 bits of rSTR1 and cr5 contains the result of the logical compare
of rBITDIF to 0. If rBITDIF == 0 then we are already word of rBITDIF to 0. If rBITDIF == 0 then we are already word
aligned and can perform the word aligned loop. aligned and can perform the word aligned loop.
Otherwise we know the two strings have the same alignment (but not Otherwise we know the two strings have the same alignment (but not
@ -159,7 +159,7 @@ L(dP1):
(8-15 byte compare), we want to use only volatile registers. This (8-15 byte compare), we want to use only volatile registers. This
means we can avoid restoring non-volatile registers since we did not means we can avoid restoring non-volatile registers since we did not
change any on the early exit path. The key here is the non-early change any on the early exit path. The key here is the non-early
exit path only cares about the condition code (cr5), not about which exit path only cares about the condition code (cr5), not about which
register pair was used. */ register pair was used. */
lwz rWORD5,0(rSTR1) lwz rWORD5,0(rSTR1)
lwz rWORD6,0(rSTR2) lwz rWORD6,0(rSTR2)
@ -339,7 +339,7 @@ L(d24):
bne cr6,L(dLcr6) bne cr6,L(dLcr6)
L(d14): L(d14):
slwi. r12,rN,3 slwi. r12,rN,3
bne cr5,L(dLcr5) bne cr5,L(dLcr5)
L(d04): L(d04):
lwz r30,44(1) lwz r30,44(1)
lwz r31,48(1) lwz r31,48(1)
@ -348,10 +348,10 @@ L(d04):
beq L(zeroLength) beq L(zeroLength)
/* At this point we have a remainder of 1 to 3 bytes to compare. Since /* At this point we have a remainder of 1 to 3 bytes to compare. Since
we are aligned it is safe to load the whole word, and use we are aligned it is safe to load the whole word, and use
shift right to eliminate bits beyond the compare length. */ shift right to eliminate bits beyond the compare length. */
L(d00): L(d00):
lwz rWORD1,4(rSTR1) lwz rWORD1,4(rSTR1)
lwz rWORD2,4(rSTR2) lwz rWORD2,4(rSTR2)
srw rWORD1,rWORD1,rN srw rWORD1,rWORD1,rN
srw rWORD2,rWORD2,rN srw rWORD2,rWORD2,rN
cmplw rWORD1,rWORD2 cmplw rWORD1,rWORD2
@ -406,11 +406,11 @@ L(bytealigned):
mtctr rN mtctr rN
/* We need to prime this loop. This loop is swing modulo scheduled /* We need to prime this loop. This loop is swing modulo scheduled
to avoid pipe delays. The dependent instruction latencies (load to to avoid pipe delays. The dependent instruction latencies (load to
compare to conditional branch) is 2 to 3 cycles. In this loop each compare to conditional branch) is 2 to 3 cycles. In this loop each
dispatch group ends in a branch and takes 1 cycle. Effectively dispatch group ends in a branch and takes 1 cycle. Effectively
the first iteration of the loop only serves to load operands and the first iteration of the loop only serves to load operands and
branches based on compares are delayed until the next loop. branches based on compares are delayed until the next loop.
So we must precondition some registers and condition codes so that So we must precondition some registers and condition codes so that
we don't exit the loop early on the first iteration. */ we don't exit the loop early on the first iteration. */
@ -450,7 +450,7 @@ L(bLoop):
/* We speculatively loading bytes before we have tested the previous /* We speculatively loading bytes before we have tested the previous
bytes. But we must avoid overrunning the length (in the ctr) to bytes. But we must avoid overrunning the length (in the ctr) to
prevent these speculative loads from causing a segfault. In this prevent these speculative loads from causing a segfault. In this
case the loop will exit early (before the all pending bytes are case the loop will exit early (before the all pending bytes are
tested. In this case we must complete the pending operations tested. In this case we must complete the pending operations
before returning. */ before returning. */
@ -503,7 +503,7 @@ L(bx12):
sub rRTN,rWORD1,rWORD2 sub rRTN,rWORD1,rWORD2
blr blr
.align 4 .align 4
L(zeroLengthReturn): L(zeroLengthReturn):
L(zeroLength): L(zeroLength):
@ -515,9 +515,9 @@ L(zeroLength):
/* At this point we know the strings have different alignment and the /* At this point we know the strings have different alignment and the
compare length is at least 8 bytes. rBITDIF contains the low order compare length is at least 8 bytes. rBITDIF contains the low order
2 bits of rSTR1 and cr5 contains the result of the logical compare 2 bits of rSTR1 and cr5 contains the result of the logical compare
of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can of rBITDIF to 0. If rBITDIF == 0 then rStr1 is word aligned and can
perform the Wunaligned loop. perform the Wunaligned loop.
Otherwise we know that rSTR1 is not aready word aligned yet. Otherwise we know that rSTR1 is not aready word aligned yet.
So we can force the string addresses to the next lower word So we can force the string addresses to the next lower word
boundary and special case this first word using shift left to boundary and special case this first word using shift left to
@ -554,7 +554,7 @@ L(unaligned):
stw r26,28(r1) stw r26,28(r1)
cfi_offset(r26,(28-64)) cfi_offset(r26,(28-64))
/* Compute the left/right shift counts for the unalign rSTR2, /* Compute the left/right shift counts for the unalign rSTR2,
compensating for the logical (W aligned) start of rSTR1. */ compensating for the logical (W aligned) start of rSTR1. */
clrlwi rSHL,r27,30 clrlwi rSHL,r27,30
clrrwi rSTR1,rSTR1,2 clrrwi rSTR1,rSTR1,2
stw r25,24(r1) stw r25,24(r1)
@ -892,9 +892,9 @@ L(du14):
slwi. rN,rN,3 slwi. rN,rN,3
bne cr5,L(duLcr5) bne cr5,L(duLcr5)
/* At this point we have a remainder of 1 to 3 bytes to compare. We use /* At this point we have a remainder of 1 to 3 bytes to compare. We use
shift right to eliminate bits beyond the compare length. shift right to eliminate bits beyond the compare length.
However it may not be safe to load rWORD2 which may be beyond the However it may not be safe to load rWORD2 which may be beyond the
string length. So we compare the bit length of the remainder to string length. So we compare the bit length of the remainder to
the right shift count (rSHR). If the bit count is less than or equal the right shift count (rSHR). If the bit count is less than or equal
we do not need to load rWORD2 (all significant bits are already in we do not need to load rWORD2 (all significant bits are already in
@ -909,7 +909,7 @@ L(du14):
L(dutrim): L(dutrim):
lwz rWORD1,4(rSTR1) lwz rWORD1,4(rSTR1)
lwz r31,48(1) lwz r31,48(1)
subfic rN,rN,32 /* Shift count is 32 - (rN * 8). */ subfic rN,rN,32 /* Shift count is 32 - (rN * 8). */
or rWORD2,rA,rB or rWORD2,rA,rB
lwz r30,44(1) lwz r30,44(1)
lwz r29,40(r1) lwz r29,40(r1)

2
sysdeps/powerpc/powerpc32/power7/strncmp.S
View File

@ -35,7 +35,7 @@ EALIGN (BP_SYM(strncmp),4,0)
#define rSTR2 r4 /* second string arg */ #define rSTR2 r4 /* second string arg */
#define rN r5 /* max string length */ #define rN r5 /* max string length */
/* Note: The Bounded pointer support in this code is broken. This code /* Note: The Bounded pointer support in this code is broken. This code
was inherited from PPC32 and and that support was never completed. was inherited from PPC32 and and that support was never completed.
Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */ Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
#define rWORD1 r6 /* current word in s1 */ #define rWORD1 r6 /* current word in s1 */
#define rWORD2 r7 /* current word in s2 */ #define rWORD2 r7 /* current word in s2 */

38
sysdeps/powerpc/powerpc64/power7/memcmp.S
View File

@ -35,7 +35,7 @@ EALIGN (BP_SYM(memcmp),4,0)
#define rSTR2 r4 /* second string arg */ #define rSTR2 r4 /* second string arg */
#define rN r5 /* max string length */ #define rN r5 /* max string length */
/* Note: The Bounded pointer support in this code is broken. This code /* Note: The Bounded pointer support in this code is broken. This code
was inherited from PPC32 and and that support was never completed. was inherited from PPC32 and and that support was never completed.
Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */ Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
#define rWORD1 r6 /* current word in s1 */ #define rWORD1 r6 /* current word in s1 */
#define rWORD2 r7 /* current word in s2 */ #define rWORD2 r7 /* current word in s2 */
@ -67,9 +67,9 @@ EALIGN (BP_SYM(memcmp),4,0)
/* At this point we know both strings have the same alignment and the /* At this point we know both strings have the same alignment and the
compare length is at least 8 bytes. rBITDIF containes the low order compare length is at least 8 bytes. rBITDIF containes the low order
3 bits of rSTR1 and cr5 contains the result of the logical compare 3 bits of rSTR1 and cr5 contains the result of the logical compare
of rBITDIF to 0. If rBITDIF == 0 then we are already double word of rBITDIF to 0. If rBITDIF == 0 then we are already double word
aligned and can perform the DWaligned loop. aligned and can perform the DWaligned loop.
Otherwise we know the two strings have the same alignment (but not Otherwise we know the two strings have the same alignment (but not
yet DW). So we can force the string addresses to the next lower DW yet DW). So we can force the string addresses to the next lower DW
boundary and special case this first DW word using shift left to boundary and special case this first DW word using shift left to
@ -158,7 +158,7 @@ L(dP1):
(8-15 byte compare), we want to use only volitile registers. This (8-15 byte compare), we want to use only volitile registers. This
means we can avoid restoring non-volitile registers since we did not means we can avoid restoring non-volitile registers since we did not
change any on the early exit path. The key here is the non-early change any on the early exit path. The key here is the non-early
exit path only cares about the condition code (cr5), not about which exit path only cares about the condition code (cr5), not about which
register pair was used. */ register pair was used. */
ld rWORD5,0(rSTR1) ld rWORD5,0(rSTR1)
ld rWORD6,0(rSTR2) ld rWORD6,0(rSTR2)
@ -335,7 +335,7 @@ L(d24):
bne cr6,L(dLcr6) bne cr6,L(dLcr6)
L(d14): L(d14):
sldi. r12,rN,3 sldi. r12,rN,3
bne cr5,L(dLcr5) bne cr5,L(dLcr5)
L(d04): L(d04):
ld rWORD8,-8(r1) ld rWORD8,-8(r1)
ld rWORD7,-16(r1) ld rWORD7,-16(r1)
@ -343,10 +343,10 @@ L(d04):
beq L(zeroLength) beq L(zeroLength)
/* At this point we have a remainder of 1 to 7 bytes to compare. Since /* At this point we have a remainder of 1 to 7 bytes to compare. Since
we are aligned it is safe to load the whole double word, and use we are aligned it is safe to load the whole double word, and use
shift right double to elliminate bits beyond the compare length. */ shift right double to elliminate bits beyond the compare length. */
L(d00): L(d00):
ld rWORD1,8(rSTR1) ld rWORD1,8(rSTR1)
ld rWORD2,8(rSTR2) ld rWORD2,8(rSTR2)
srd rWORD1,rWORD1,rN srd rWORD1,rWORD1,rN
srd rWORD2,rWORD2,rN srd rWORD2,rWORD2,rN
cmpld cr5,rWORD1,rWORD2 cmpld cr5,rWORD1,rWORD2
@ -393,15 +393,15 @@ L(bytealigned):
beq cr6,L(zeroLength) beq cr6,L(zeroLength)
/* We need to prime this loop. This loop is swing modulo scheduled /* We need to prime this loop. This loop is swing modulo scheduled
to avoid pipe delays. The dependent instruction latencies (load to to avoid pipe delays. The dependent instruction latencies (load to
compare to conditional branch) is 2 to 3 cycles. In this loop each compare to conditional branch) is 2 to 3 cycles. In this loop each
dispatch group ends in a branch and takes 1 cycle. Effectively dispatch group ends in a branch and takes 1 cycle. Effectively
the first iteration of the loop only serves to load operands and the first iteration of the loop only serves to load operands and
branches based on compares are delayed until the next loop. branches based on compares are delayed until the next loop.
So we must precondition some registers and condition codes so that So we must precondition some registers and condition codes so that
we don't exit the loop early on the first iteration. */ we don't exit the loop early on the first iteration. */
lbz rWORD1,0(rSTR1) lbz rWORD1,0(rSTR1)
lbz rWORD2,0(rSTR2) lbz rWORD2,0(rSTR2)
bdz L(b11) bdz L(b11)
@ -438,7 +438,7 @@ L(bLoop):
/* We speculatively loading bytes before we have tested the previous /* We speculatively loading bytes before we have tested the previous
bytes. But we must avoid overrunning the length (in the ctr) to bytes. But we must avoid overrunning the length (in the ctr) to
prevent these speculative loads from causing a segfault. In this prevent these speculative loads from causing a segfault. In this
case the loop will exit early (before the all pending bytes are case the loop will exit early (before the all pending bytes are
tested. In this case we must complete the pending operations tested. In this case we must complete the pending operations
before returning. */ before returning. */
@ -489,7 +489,7 @@ L(b11):
L(bx12): L(bx12):
sub rRTN,rWORD1,rWORD2 sub rRTN,rWORD1,rWORD2
blr blr
.align 4 .align 4
L(zeroLengthReturn): L(zeroLengthReturn):
ld rWORD8,-8(r1) ld rWORD8,-8(r1)
ld rWORD7,-16(r1) ld rWORD7,-16(r1)
@ -501,9 +501,9 @@ L(zeroLength):
/* At this point we know the strings have different alignment and the /* At this point we know the strings have different alignment and the
compare length is at least 8 bytes. rBITDIF containes the low order compare length is at least 8 bytes. rBITDIF containes the low order
3 bits of rSTR1 and cr5 contains the result of the logical compare 3 bits of rSTR1 and cr5 contains the result of the logical compare
of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word of rBITDIF to 0. If rBITDIF == 0 then rStr1 is double word
aligned and can perform the DWunaligned loop. aligned and can perform the DWunaligned loop.
Otherwise we know that rSTR1 is not aready DW aligned yet. Otherwise we know that rSTR1 is not aready DW aligned yet.
So we can force the string addresses to the next lower DW So we can force the string addresses to the next lower DW
boundary and special case this first DW word using shift left to boundary and special case this first DW word using shift left to
@ -541,7 +541,7 @@ L(unaligned):
std r26,-48(r1) std r26,-48(r1)
cfi_offset(r26,-48) cfi_offset(r26,-48)
/* Compute the leaft/right shift counts for the unalign rSTR2, /* Compute the leaft/right shift counts for the unalign rSTR2,
compensating for the logical (DW aligned) start of rSTR1. */ compensating for the logical (DW aligned) start of rSTR1. */
clrldi rSHL,r27,61 clrldi rSHL,r27,61
clrrdi rSTR1,rSTR1,3 clrrdi rSTR1,rSTR1,3
std r25,-56(r1) std r25,-56(r1)
@ -879,11 +879,11 @@ L(du14):
sldi. rN,rN,3 sldi. rN,rN,3
bne cr5,L(duLcr5) bne cr5,L(duLcr5)
/* At this point we have a remainder of 1 to 7 bytes to compare. We use /* At this point we have a remainder of 1 to 7 bytes to compare. We use
shift right double to elliminate bits beyond the compare length. shift right double to elliminate bits beyond the compare length.
This allows the use of double word subtract to compute the final This allows the use of double word subtract to compute the final
result. result.
However it may not be safe to load rWORD2 which may be beyond the However it may not be safe to load rWORD2 which may be beyond the
string length. So we compare the bit length of the remainder to string length. So we compare the bit length of the remainder to
the right shift count (rSHR). If the bit count is less than or equal the right shift count (rSHR). If the bit count is less than or equal
we do not need to load rWORD2 (all significant bits are already in we do not need to load rWORD2 (all significant bits are already in
@ -898,7 +898,7 @@ L(du14):
L(dutrim): L(dutrim):
ld rWORD1,8(rSTR1) ld rWORD1,8(rSTR1)
ld rWORD8,-8(r1) ld rWORD8,-8(r1)
subfic rN,rN,64 /* Shift count is 64 - (rN * 8). */ subfic rN,rN,64 /* Shift count is 64 - (rN * 8). */
or rWORD2,rA,rB or rWORD2,rA,rB
ld rWORD7,-16(r1) ld rWORD7,-16(r1)
ld r29,-24(r1) ld r29,-24(r1)

2
sysdeps/powerpc/powerpc64/power7/strncmp.S
View File

@ -36,7 +36,7 @@ EALIGN (BP_SYM(strncmp),4,0)
#define rSTR2 r4 /* second string arg */ #define rSTR2 r4 /* second string arg */
#define rN r5 /* max string length */ #define rN r5 /* max string length */
/* Note: The Bounded pointer support in this code is broken. This code /* Note: The Bounded pointer support in this code is broken. This code
was inherited from PPC32 and and that support was never completed. was inherited from PPC32 and and that support was never completed.
Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */ Current PPC gcc does not support -fbounds-check or -fbounded-pointers. */
#define rWORD1 r6 /* current word in s1 */ #define rWORD1 r6 /* current word in s1 */
#define rWORD2 r7 /* current word in s2 */ #define rWORD2 r7 /* current word in s2 */