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PowerPC floating point little-endian [8 of 15] 

http://sourceware.org/ml/libc-alpha/2013-07/msg00199.html

Corrects floating-point environment code for little-endian.

	* sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int
	array with long long.
	* sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust.
	* sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust.
	* sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust.
	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust.
	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust.
	* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust.
	* sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust.
	* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust.
	* sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust.
	* sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust.
	* sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust.
	* sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust.
	* sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust.
This commit is contained in:
Anton Blanchard 2013-08-17 18:28:55 +09:30 committed by Alan Modra
parent 2ca85d2bbb
commit 4a28b3ca4b
15 changed files with 57 additions and 40 deletions
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18
ChangeLog
View File

@ -1,3 +1,21 @@
2013-10-04 Anton Blanchard <anton@au1.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int
array with long long.
* sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust.
* sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust.
* sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust.
* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust.
* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust.
* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust.
* sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust.
* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust.
* sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust.
* sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust.
* sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust.
* sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust.
* sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust.
2013-10-04 Anton Blanchard <anton@au1.ibm.com> 2013-10-04 Anton Blanchard <anton@au1.ibm.com>
* sysdeps/powerpc/bits/mathinline.h (__signbitf): Use builtin. * sysdeps/powerpc/bits/mathinline.h (__signbitf): Use builtin.

2
sysdeps/powerpc/fpu/e_sqrt.c
View File

@ -145,7 +145,7 @@ __slow_ieee754_sqrt (double x)
feraiseexcept (FE_INVALID_SQRT); feraiseexcept (FE_INVALID_SQRT);
fenv_union_t u = { .fenv = fegetenv_register () }; fenv_union_t u = { .fenv = fegetenv_register () };
if ((u.l[1] & FE_INVALID) == 0) if ((u.l & FE_INVALID) == 0)
#endif #endif
feraiseexcept (FE_INVALID); feraiseexcept (FE_INVALID);
x = a_nan.value; x = a_nan.value;

2
sysdeps/powerpc/fpu/e_sqrtf.c
View File

@ -121,7 +121,7 @@ __slow_ieee754_sqrtf (float x)
feraiseexcept (FE_INVALID_SQRT); feraiseexcept (FE_INVALID_SQRT);
fenv_union_t u = { .fenv = fegetenv_register () }; fenv_union_t u = { .fenv = fegetenv_register () };
if ((u.l[1] & FE_INVALID) == 0) if ((u.l & FE_INVALID) == 0)
#endif #endif
feraiseexcept (FE_INVALID); feraiseexcept (FE_INVALID);
x = a_nan.value; x = a_nan.value;

4
sysdeps/powerpc/fpu/fclrexcpt.c
View File

@ -28,8 +28,8 @@ __feclearexcept (int excepts)
u.fenv = fegetenv_register (); u.fenv = fegetenv_register ();
/* Clear the relevant bits. */ /* Clear the relevant bits. */
u.l[1] = u.l[1] & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID) u.l = u.l & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID)
| (excepts & FPSCR_STICKY_BITS)); | (excepts & FPSCR_STICKY_BITS));
/* Put the new state in effect. */ /* Put the new state in effect. */
fesetenv_register (u.fenv); fesetenv_register (u.fenv);

10
sysdeps/powerpc/fpu/fedisblxcpt.c
View File

@ -32,15 +32,15 @@ fedisableexcept (int excepts)
fe.fenv = fegetenv_register (); fe.fenv = fegetenv_register ();
if (excepts & FE_INEXACT) if (excepts & FE_INEXACT)
fe.l[1] &= ~(1 << (31 - FPSCR_XE)); fe.l &= ~(1 << (31 - FPSCR_XE));
if (excepts & FE_DIVBYZERO) if (excepts & FE_DIVBYZERO)
fe.l[1] &= ~(1 << (31 - FPSCR_ZE)); fe.l &= ~(1 << (31 - FPSCR_ZE));
if (excepts & FE_UNDERFLOW) if (excepts & FE_UNDERFLOW)
fe.l[1] &= ~(1 << (31 - FPSCR_UE)); fe.l &= ~(1 << (31 - FPSCR_UE));
if (excepts & FE_OVERFLOW) if (excepts & FE_OVERFLOW)
fe.l[1] &= ~(1 << (31 - FPSCR_OE)); fe.l &= ~(1 << (31 - FPSCR_OE));
if (excepts & FE_INVALID) if (excepts & FE_INVALID)
fe.l[1] &= ~(1 << (31 - FPSCR_VE)); fe.l &= ~(1 << (31 - FPSCR_VE));
fesetenv_register (fe.fenv); fesetenv_register (fe.fenv);
new = __fegetexcept (); new = __fegetexcept ();

10
sysdeps/powerpc/fpu/feenablxcpt.c
View File

@ -32,15 +32,15 @@ feenableexcept (int excepts)
fe.fenv = fegetenv_register (); fe.fenv = fegetenv_register ();
if (excepts & FE_INEXACT) if (excepts & FE_INEXACT)
fe.l[1] |= (1 << (31 - FPSCR_XE)); fe.l |= (1 << (31 - FPSCR_XE));
if (excepts & FE_DIVBYZERO) if (excepts & FE_DIVBYZERO)
fe.l[1] |= (1 << (31 - FPSCR_ZE)); fe.l |= (1 << (31 - FPSCR_ZE));
if (excepts & FE_UNDERFLOW) if (excepts & FE_UNDERFLOW)
fe.l[1] |= (1 << (31 - FPSCR_UE)); fe.l |= (1 << (31 - FPSCR_UE));
if (excepts & FE_OVERFLOW) if (excepts & FE_OVERFLOW)
fe.l[1] |= (1 << (31 - FPSCR_OE)); fe.l |= (1 << (31 - FPSCR_OE));
if (excepts & FE_INVALID) if (excepts & FE_INVALID)
fe.l[1] |= (1 << (31 - FPSCR_VE)); fe.l |= (1 << (31 - FPSCR_VE));
fesetenv_register (fe.fenv); fesetenv_register (fe.fenv);
new = __fegetexcept (); new = __fegetexcept ();

10
sysdeps/powerpc/fpu/fegetexcept.c
View File

@ -27,15 +27,15 @@ __fegetexcept (void)
fe.fenv = fegetenv_register (); fe.fenv = fegetenv_register ();
if (fe.l[1] & (1 << (31 - FPSCR_XE))) if (fe.l & (1 << (31 - FPSCR_XE)))
result |= FE_INEXACT; result |= FE_INEXACT;
if (fe.l[1] & (1 << (31 - FPSCR_ZE))) if (fe.l & (1 << (31 - FPSCR_ZE)))
result |= FE_DIVBYZERO; result |= FE_DIVBYZERO;
if (fe.l[1] & (1 << (31 - FPSCR_UE))) if (fe.l & (1 << (31 - FPSCR_UE)))
result |= FE_UNDERFLOW; result |= FE_UNDERFLOW;
if (fe.l[1] & (1 << (31 - FPSCR_OE))) if (fe.l & (1 << (31 - FPSCR_OE)))
result |= FE_OVERFLOW; result |= FE_OVERFLOW;
if (fe.l[1] & (1 << (31 - FPSCR_VE))) if (fe.l & (1 << (31 - FPSCR_VE)))
result |= FE_INVALID; result |= FE_INVALID;
return result; return result;

5
sysdeps/powerpc/fpu/feholdexcpt.c
View File

@ -30,13 +30,12 @@ feholdexcept (fenv_t *envp)
/* Clear everything except for the rounding modes and non-IEEE arithmetic /* Clear everything except for the rounding modes and non-IEEE arithmetic
flag. */ flag. */
new.l[1] = old.l[1] & 7; new.l = old.l & 0xffffffff00000007LL;
new.l[0] = old.l[0];
/* If the old env had any enabled exceptions, then mask SIGFPE in the /* If the old env had any enabled exceptions, then mask SIGFPE in the
MSR FE0/FE1 bits. This may allow the FPU to run faster because it MSR FE0/FE1 bits. This may allow the FPU to run faster because it
always takes the default action and can not generate SIGFPE. */ always takes the default action and can not generate SIGFPE. */
if ((old.l[1] & _FPU_MASK_ALL) != 0) if ((old.l & _FPU_MASK_ALL) != 0)
(void)__fe_mask_env (); (void)__fe_mask_env ();
/* Put the new state in effect. */ /* Put the new state in effect. */

2
sysdeps/powerpc/fpu/fenv_libc.h
View File

@ -69,7 +69,7 @@ libm_hidden_proto (__fe_nomask_env)
typedef union typedef union
{ {
fenv_t fenv; fenv_t fenv;
unsigned int l[2]; unsigned long long l;
} fenv_union_t; } fenv_union_t;

4
sysdeps/powerpc/fpu/fesetenv.c
View File

@ -34,14 +34,14 @@ __fesetenv (const fenv_t *envp)
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
hardware into "precise mode" and may cause the FPU to run slower on some hardware into "precise mode" and may cause the FPU to run slower on some
hardware. */ hardware. */
if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env (); (void)__fe_nomask_env ();
/* If the old env had any enabled exceptions and the new env has no enabled /* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not FPU to run faster because it always takes the default action and can not
generate SIGFPE. */ generate SIGFPE. */
if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env (); (void)__fe_mask_env ();
fesetenv_register (*envp); fesetenv_register (*envp);

6
sysdeps/powerpc/fpu/feupdateenv.c
View File

@ -34,20 +34,20 @@ __feupdateenv (const fenv_t *envp)
/* Restore rounding mode and exception enable from *envp and merge /* Restore rounding mode and exception enable from *envp and merge
exceptions. Leave fraction rounded/inexact and FP result/CC bits exceptions. Leave fraction rounded/inexact and FP result/CC bits
unchanged. */ unchanged. */
new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF); new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
/* If the old env has no enabled exceptions and the new env has any enabled /* If the old env has no enabled exceptions and the new env has any enabled
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
the hardware into "precise mode" and may cause the FPU to run slower on the hardware into "precise mode" and may cause the FPU to run slower on
some hardware. */ some hardware. */
if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0) if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env (); (void)__fe_nomask_env ();
/* If the old env had any enabled exceptions and the new env has no enabled /* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not FPU to run faster because it always takes the default action and can not
generate SIGFPE. */ generate SIGFPE. */
if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0) if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env (); (void)__fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */ /* Atomically enable and raise (if appropriate) exceptions set in `new'. */

2
sysdeps/powerpc/fpu/fgetexcptflg.c
View File

@ -27,7 +27,7 @@ __fegetexceptflag (fexcept_t *flagp, int excepts)
u.fenv = fegetenv_register (); u.fenv = fegetenv_register ();
/* Return (all of) it. */ /* Return (all of) it. */
*flagp = u.l[1] & excepts & FE_ALL_EXCEPT; *flagp = u.l & excepts & FE_ALL_EXCEPT;
/* Success. */ /* Success. */
return 0; return 0;

12
sysdeps/powerpc/fpu/fraiseexcpt.c
View File

@ -33,11 +33,11 @@ __feraiseexcept (int excepts)
u.fenv = fegetenv_register (); u.fenv = fegetenv_register ();
/* Add the exceptions */ /* Add the exceptions */
u.l[1] = (u.l[1] u.l = (u.l
| (excepts & FPSCR_STICKY_BITS) | (excepts & FPSCR_STICKY_BITS)
/* Turn FE_INVALID into FE_INVALID_SOFTWARE. */ /* Turn FE_INVALID into FE_INVALID_SOFTWARE. */
| (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) | (excepts >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
& FE_INVALID_SOFTWARE)); & FE_INVALID_SOFTWARE));
/* Store the new status word (along with the rest of the environment), /* Store the new status word (along with the rest of the environment),
triggering any appropriate exceptions. */ triggering any appropriate exceptions. */
@ -49,7 +49,7 @@ __feraiseexcept (int excepts)
don't have FE_INVALID_SOFTWARE implemented. Detect this don't have FE_INVALID_SOFTWARE implemented. Detect this
case and raise FE_INVALID_SNAN instead. */ case and raise FE_INVALID_SNAN instead. */
u.fenv = fegetenv_register (); u.fenv = fegetenv_register ();
if ((u.l[1] & FE_INVALID) == 0) if ((u.l & FE_INVALID) == 0)
set_fpscr_bit (FPSCR_VXSNAN); set_fpscr_bit (FPSCR_VXSNAN);
} }

8
sysdeps/powerpc/fpu/fsetexcptflg.c
View File

@ -31,10 +31,10 @@ __fesetexceptflag (const fexcept_t *flagp, int excepts)
flag = *flagp & excepts; flag = *flagp & excepts;
/* Replace the exception status */ /* Replace the exception status */
u.l[1] = ((u.l[1] & ~(FPSCR_STICKY_BITS & excepts)) u.l = ((u.l & ~(FPSCR_STICKY_BITS & excepts))
| (flag & FPSCR_STICKY_BITS) | (flag & FPSCR_STICKY_BITS)
| (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT)) | (flag >> ((31 - FPSCR_VX) - (31 - FPSCR_VXSOFT))
& FE_INVALID_SOFTWARE)); & FE_INVALID_SOFTWARE));
/* Store the new status word (along with the rest of the environment). /* Store the new status word (along with the rest of the environment).
This may cause floating-point exceptions if the restored state This may cause floating-point exceptions if the restored state

2
sysdeps/powerpc/fpu/ftestexcept.c
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@ -28,6 +28,6 @@ fetestexcept (int excepts)
/* The FE_INVALID bit is dealt with correctly by the hardware, so we can /* The FE_INVALID bit is dealt with correctly by the hardware, so we can
just: */ just: */
return u.l[1] & excepts; return u.l & excepts;
} }
libm_hidden_def (fetestexcept) libm_hidden_def (fetestexcept)