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Define __HAVE_64B_ATOMICS from compiler support 

Now that atomic builtins are used by default, we can rely on the
compiler to define when to use 64-bit atomic operations.

It allows the use of 64-bit atomic operations on some 32-bit ABIs where
they were not previously enabled due to missing pre-processor handling:
hppa, mips64n32, s390, and sparcv9.

Co-authored-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
Reviewed-by: Uros Bizjak <ubizjak@gmail.com>
Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
This commit is contained in:
Wilco Dijkstra 2025-09-11 10:49:47 -03:00 committed by Adhemerval Zanella
parent 95a0ad1ea1
commit 53807741fb
20 changed files with 72 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
config.h.in
View File

@ -222,6 +222,9 @@
/* An integer used to scale the timeout of test programs. */
#define TIMEOUTFACTOR 1
/* Set to 1 if 64 bit atomics are supported. */
#undef __HAVE_64B_ATOMICS 0
/*
*/

42
configure vendored
View File

@ -7702,6 +7702,48 @@ if test "$libc_cv_gcc_builtin_memset" = yes ; then
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for 64-bit atomic support" >&5
printf %s "checking for 64-bit atomic support... " >&6; }
if test ${libc_cv_gcc_has_64b_atomics+y}
then :
printf %s "(cached) " >&6
else case e in #(
e) cat > conftest.c <<\EOF
typedef struct { long long t; } X;
extern void has_64b_atomics(void);
void f(void)
{
X x;
/* Use address of structure with 64-bit type. This avoids incorrect
implementations which return true even if long long is not 64-bit aligned.
This works on GCC and LLVM - other cases have bugs and they disagree. */
_Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics");
}
EOF
if { ac_try='${CC-cc} -O2 -S conftest.c'
{ { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
(eval $ac_try) 2>&5
ac_status=$?
printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
test $ac_status = 0; }; };
then
libc_cv_gcc_has_64b_atomics=yes
else
libc_cv_gcc_has_64b_atomics=no
fi
rm -f conftest* ;;
esac
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $libc_cv_gcc_has_64b_atomics" >&5
printf "%s\n" "$libc_cv_gcc_has_64b_atomics" >&6; }
if test "$libc_cv_gcc_has_64b_atomics" = yes; then
printf "%s\n" "#define __HAVE_64B_ATOMICS 1" >>confdefs.h
else
printf "%s\n" "#define __HAVE_64B_ATOMICS 0" >>confdefs.h
fi
{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for redirection of built-in functions" >&5
printf %s "checking for redirection of built-in functions... " >&6; }
if test ${libc_cv_gcc_builtin_redirection+y}

27
configure.ac
View File

@ -1493,6 +1493,33 @@ if test "$libc_cv_gcc_builtin_memset" = yes ; then
AC_DEFINE(HAVE_BUILTIN_MEMSET)
fi
AC_CACHE_CHECK(for 64-bit atomic support, libc_cv_gcc_has_64b_atomics, [dnl
cat > conftest.c <<\EOF
typedef struct { long long t; } X;
extern void has_64b_atomics(void);
void f(void)
{
X x;
/* Use address of structure with 64-bit type. This avoids incorrect
implementations which return true even if long long is not 64-bit aligned.
This works on GCC and LLVM - other cases have bugs and they disagree. */
_Static_assert (__atomic_always_lock_free (sizeof (x), &x), "no_64b_atomics");
}
EOF
dnl
if AC_TRY_COMMAND([${CC-cc} -O2 -S conftest.c]);
then
libc_cv_gcc_has_64b_atomics=yes
else
libc_cv_gcc_has_64b_atomics=no
fi
rm -f conftest* ])
if test "$libc_cv_gcc_has_64b_atomics" = yes; then
AC_DEFINE(__HAVE_64B_ATOMICS, 1)
else
AC_DEFINE(__HAVE_64B_ATOMICS, 0)
fi
AC_CACHE_CHECK(for redirection of built-in functions, libc_cv_gcc_builtin_redirection, [dnl
cat > conftest.c <<\EOF
extern char *strstr (const char *, const char *) __asm ("my_strstr");

1
sysdeps/aarch64/atomic-machine.h
View File

@ -19,7 +19,6 @@
#ifndef _AARCH64_ATOMIC_MACHINE_H
#define _AARCH64_ATOMIC_MACHINE_H 1
#define __HAVE_64B_ATOMICS 1
#define ATOMIC_EXCHANGE_USES_CAS 0
#endif

2
sysdeps/alpha/atomic-machine.h
View File

@ -17,8 +17,6 @@
#include <stdint.h>
#define __HAVE_64B_ATOMICS 1
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1

2
sysdeps/arc/atomic-machine.h
View File

@ -19,8 +19,6 @@
#ifndef _ARC_BITS_ATOMIC_H
#define _ARC_BITS_ATOMIC_H 1
#define __HAVE_64B_ATOMICS 0
/* ARC does have legacy atomic EX reg, [mem] instruction but the micro-arch
is not as optimal as LLOCK/SCOND specially for SMP. */
#define ATOMIC_EXCHANGE_USES_CAS 1

1
sysdeps/arm/atomic-machine.h
View File

@ -16,5 +16,4 @@
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1

1
sysdeps/csky/atomic-machine.h
View File

@ -19,7 +19,6 @@
#ifndef __CSKY_ATOMIC_H_
#define __CSKY_ATOMIC_H_
#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1
#endif /* atomic-machine.h */

2
sysdeps/hppa/atomic-machine.h
View File

@ -18,8 +18,6 @@
#ifndef _ATOMIC_MACHINE_H
#define _ATOMIC_MACHINE_H 1
#define __HAVE_64B_ATOMICS 0
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1

1
sysdeps/loongarch/atomic-machine.h
View File

@ -19,7 +19,6 @@
#ifndef _LINUX_LOONGARCH_BITS_ATOMIC_H
#define _LINUX_LOONGARCH_BITS_ATOMIC_H 1
#define __HAVE_64B_ATOMICS (__loongarch_grlen >= 64)
#define ATOMIC_EXCHANGE_USES_CAS 0
#endif /* bits/atomic.h */

3
sysdeps/m68k/atomic-machine.h
View File

@ -19,9 +19,6 @@
#define _M68K_ATOMIC_MACHINE_H 1
#if defined __mc68020__ || defined __mcoldfire__
/* If we have just non-atomic operations, we can as well make them wide. */
# define __HAVE_64B_ATOMICS 0
/* XXX Is this actually correct? */
# define ATOMIC_EXCHANGE_USES_CAS 1
#else

2
sysdeps/microblaze/atomic-machine.h
View File

@ -18,7 +18,5 @@
#include <sysdep.h>
#define __HAVE_64B_ATOMICS 0
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1

6
sysdeps/mips/atomic-machine.h
View File

@ -27,12 +27,6 @@
#define MIPS_PUSH_MIPS2
#endif
#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
#define __HAVE_64B_ATOMICS 0
#else
#define __HAVE_64B_ATOMICS 1
#endif
/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
instruction which will be used by __atomic_exchange_n. */
#ifdef _MIPS_ARCH_XLP

1
sysdeps/or1k/atomic-machine.h
View File

@ -19,7 +19,6 @@
#ifndef __OR1K_ATOMIC_H_
#define __OR1K_ATOMIC_H_
#define __HAVE_64B_ATOMICS 0
#define ATOMIC_EXCHANGE_USES_CAS 1
#endif /* atomic-machine.h */

5
sysdeps/powerpc/atomic-machine.h
View File

@ -19,11 +19,6 @@
#ifndef _POWERPC_ATOMIC_MACHINE_H
#define _POWERPC_ATOMIC_MACHINE_H 1
#if __WORDSIZE == 64
# define __HAVE_64B_ATOMICS 1
#else
# define __HAVE_64B_ATOMICS 0
#endif
#define ATOMIC_EXCHANGE_USES_CAS 1
/* Used on pthread_spin_{try}lock. */

1
sysdeps/riscv/atomic-machine.h
View File

@ -21,7 +21,6 @@
#ifdef __riscv_atomic
# define __HAVE_64B_ATOMICS (__riscv_xlen >= 64)
# define ATOMIC_EXCHANGE_USES_CAS 0
/* Miscellaneous. */

6
sysdeps/s390/atomic-machine.h
View File

@ -15,10 +15,4 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#ifdef __s390x__
# define __HAVE_64B_ATOMICS 1
#else
# define __HAVE_64B_ATOMICS 0
#endif
#define ATOMIC_EXCHANGE_USES_CAS 1

2
sysdeps/sh/atomic-machine.h
View File

@ -16,7 +16,5 @@
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
#define __HAVE_64B_ATOMICS 0
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS 1

6
sysdeps/sparc/atomic-machine.h
View File

@ -19,12 +19,6 @@
#ifndef _ATOMIC_MACHINE_H
#define _ATOMIC_MACHINE_H 1
#ifdef __arch64__
# define __HAVE_64B_ATOMICS 1
#else
# define __HAVE_64B_ATOMICS 0
#endif
/* XXX Is this actually correct? */
#define ATOMIC_EXCHANGE_USES_CAS __HAVE_64B_ATOMICS

10
sysdeps/x86/atomic-machine.h
View File

@ -19,16 +19,6 @@
#ifndef _X86_ATOMIC_MACHINE_H
#define _X86_ATOMIC_MACHINE_H 1
#ifdef __x86_64__
# define __HAVE_64B_ATOMICS 1
#else
/* Since the Pentium, i386 CPUs have supported 64-bit atomics, but the
i386 psABI supplement provides only 4-byte alignment for uint64_t
inside structs, so it is currently not possible to use 64-bit
atomics on this platform. */
# define __HAVE_64B_ATOMICS 0
#endif
#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_spin_nop() __asm ("pause")