mirror of git://sourceware.org/git/glibc.git
atomic: Switch microblaze to builtin atomics
Switch microblaze to builtin atomics. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
This commit is contained in:
Wilco Dijkstra
parent
30108f8b6c
commit
666c26c243
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@ -19,234 +19,7 @@
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#include <sysdep.h>
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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/* XXX Is this actually correct? */
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#define ATOMIC_EXCHANGE_USES_CAS 1
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/* Microblaze does not have byte and halfword forms of load and reserve and
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store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
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#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
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(abort (), 0)
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#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" cmp %1, %0, %4;" \
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" bnei %1, 2f;" \
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" swx %5, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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"2:" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (__memp), \
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"r" (oldval), \
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"r" (newval) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_exchange_32_acq(mem, value) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" swx %3, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (value), \
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"r" (__memp) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_64_acq(mem, newval) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_exchange_acq(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_32_acq (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_64_acq (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_exchange_rel(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_32_acq (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_64_acq (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_exchange_and_add_32(mem, value) \
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({ \
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__typeof (*(mem)) __tmp; \
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__typeof (mem) __memp = (mem); \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" add %1, %3, %0;" \
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" swx %1, %4, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__tmp), \
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"=&r" (test), \
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"=m" (*__memp) \
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: "r" (value), \
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"r" (__memp) \
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: "cc", "memory"); \
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__tmp; \
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})
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#define __arch_atomic_exchange_and_add_64(mem, value) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_exchange_and_add(mem, value) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*mem) == 4) \
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__result = __arch_atomic_exchange_and_add_32 (mem, value); \
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else if (sizeof (*mem) == 8) \
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__result = __arch_atomic_exchange_and_add_64 (mem, value); \
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else \
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abort (); \
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__result; \
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})
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#define __arch_atomic_increment_val_32(mem) \
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({ \
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__typeof (*(mem)) __val; \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" addi %0, %0, 1;" \
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" swx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__val), \
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"=&r" (test), \
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"=m" (*mem) \
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: "r" (mem), \
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"m" (*mem) \
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: "cc", "memory"); \
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__val; \
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})
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#define __arch_atomic_increment_val_64(mem) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_increment_val(mem) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*(mem)) == 4) \
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__result = __arch_atomic_increment_val_32 (mem); \
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else if (sizeof (*(mem)) == 8) \
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__result = __arch_atomic_increment_val_64 (mem); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
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#define __arch_atomic_decrement_val_32(mem) \
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({ \
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__typeof (*(mem)) __val; \
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int test; \
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__asm __volatile ( \
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" addc r0, r0, r0;" \
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"1: lwx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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" rsubi %0, %0, 1;" \
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" swx %0, %3, r0;" \
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" addic %1, r0, 0;" \
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" bnei %1, 1b;" \
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: "=&r" (__val), \
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"=&r" (test), \
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"=m" (*mem) \
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: "r" (mem), \
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"m" (*mem) \
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: "cc", "memory"); \
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__val; \
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})
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#define __arch_atomic_decrement_val_64(mem) \
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(abort (), (__typeof (*mem)) 0)
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#define atomic_decrement_val(mem) \
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({ \
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__typeof (*(mem)) __result; \
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if (sizeof (*(mem)) == 4) \
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__result = __arch_atomic_decrement_val_32 (mem); \
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else if (sizeof (*(mem)) == 8) \
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__result = __arch_atomic_decrement_val_64 (mem); \
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else \
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abort (); \
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__result; \
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})
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#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })
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