glibc/sysdeps/powerpc
Paul A. Clarke 0b3c9e57a4 [powerpc] fegetenv_status: simplify instruction generation
fegetenv_status() wants to use the lighter weight instruction 'mffsl'
for reading the Floating-Point Status and Control Register (FPSCR).
It currently will use it directly if compiled '-mcpu=power9', and will
perform a runtime check (cpu_supports("arch_3_00")) otherwise.

Nicely, it turns out that the 'mffsl' instruction will decode to
'mffs' on architectures older than "arch_3_00" because the additional
bits set for 'mffsl' are "don't care" for 'mffs'.  'mffs' is a superset
of 'mffsl'.

So, just generate 'mffsl'.
2019-08-28 13:53:09 -05:00
..
bits Declare most TS 18661-1 interfaces for C2X. 2019-08-13 11:28:51 +00:00
fpu [powerpc] fegetenv_status: simplify instruction generation 2019-08-28 13:53:09 -05:00
nofpu
nptl
power4
power6
powerpc32 powerpc: refactor logb{f,l} 2019-07-08 17:22:22 -03:00
powerpc64 powerpc: Cleanup: use actual power8 assembly mnemonics 2019-08-01 15:57:50 -03:00
sys/platform
Makefile
Versions
abort-instr.h
atomic-machine.h
cpu-features.c
cpu-features.h
dl-procinfo.c
dl-procinfo.h
dl-tls.c
dl-tls.h
dl-tunables.list
ffs.c
fpu_control.h powerpc: Use faster means to access FPSCR when possible in some cases 2019-06-30 08:40:44 -03:00
gccframe.h
hwcapinfo.c
hwcapinfo.h
ifunc-sel.h
jmpbuf-offsets.h
jmpbuf-unwind.h
ldsodefs.h
libc-tls.c
locale-defines.sym
longjmp.c
machine-gmon.h
math-tests-snan-cast.h
memusage.h
mod-tlsopt-powerpc.c
mp_clz_tab.c
novmx-longjmp.c
novmx-sigjmp.c
novmxsetjmp.h
preconfigure
rtld-global-offsets.sym
sched_cpucount.c
sigjmp.c
sotruss-lib.c
stackinfo.h
sysdep.h
test-arith.c
test-arithf.c
test-get_hwcap-static.c
test-get_hwcap.c
test-gettimebase.c
tls-macros.h
tst-set_ppr.c
tst-stack-align.h
tst-tlsifunc-static.c
tst-tlsifunc.c
tst-tlsopt-powerpc.c