glibc/sysdeps/riscv
Julian Zhu 4c966c0780 RISC-V: Use builtin for ffs and ffsll while supported extension available
Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`.

Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
2025-04-28 09:51:59 -03:00
..
bits
multiarch
nofpu math: Refactor how to use libm-test-ulps 2025-03-12 13:40:07 -03:00
nptl
rv32
rv64
rvd math: Refactor how to use libm-test-ulps 2025-03-12 13:40:07 -03:00
rvf
sys
Implies
Makefile
__longjmp.S
bsd-_setjmp.c
bsd-setjmp.c
configure
configure.ac
dl-irel.h
dl-link.sym
dl-machine.h RISC-V: Fix IFUNC resolver cannot access gp pointer 2025-02-25 13:08:53 +01:00
dl-relocate-ld.h
dl-tls.h
dl-trampoline.S
e_sqrtl.c
fpu_control.h
gccframe.h
jmpbuf-offsets.h
jmpbuf-unwind.h
ldsodefs.h
libc-tls.c
linkmap.h
machine-gmon.h
math-tests-snan-payload.h
math-tests-trap.h
math-use-builtins-ffs.h RISC-V: Use builtin for ffs and ffsll while supported extension available 2025-04-28 09:51:59 -03:00
preconfigure
preconfigure.ac
riscv-ifunc.h
setjmp.S
sfp-machine.h
sotruss-lib.c
start.S
string-fza.h
string-fzi.h
thread_pointer.h
tininess.h
tst-audit.h
utmp-size.h