mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing
commitfd779eac2d
upstream. Having setup time 0 violates tAR, tCLR of some chips, for instance TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of 98 dc 90 15 76 ...). Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation [1], but it looks more appropriate to just calculate setup time properly. [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf Cc: stable@vger.kernel.org Fixes:f9ce2eddf1
("mtd: nand: atmel: Add ->setup_data_interface() hooks") Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Tested-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1377,14 +1377,24 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
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if (ret)
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return ret;
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/*
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* Read setup timing depends on the operation done on the NAND:
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*
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* NRD_SETUP = max(tAR, tCLR)
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*/
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timeps = max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min);
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ncycles = DIV_ROUND_UP(timeps, mckperiodps);
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totalcycles += ncycles;
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ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles);
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if (ret)
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return ret;
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/*
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* The read cycle timing is directly matching tRC, but is also
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* dependent on the setup and hold timings we calculated earlier,
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* which gives:
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*
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* NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
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*
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* NRD_SETUP is always 0.
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* NRD_CYCLE = max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD)
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
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ncycles = max(totalcycles, ncycles);
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