dt-bindings: PCI: Convert marvell,armada8k-pcie to schema
Convert the marvell,armada8k-pcie binding to DT schema. The binding uses different names for reg, clocks, and phys which have to be added to the common Synopsys DWC binding. The "marvell,reset-gpio" property was not documented. Mark it deprecated as the "reset-gpios" property can be used instead. The "msi-parent" property was also not documented. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250414214135.1680076-1-robh@kernel.org
This commit is contained in:
Rob Herring (Arm)
Manivannan Sadhasivam
parent
0c983d3544
commit
096d05bf3e
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 7K/8K PCIe interface
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maintainers:
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- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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description:
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
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select:
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properties:
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compatible:
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contains:
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enum:
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- marvell,armada8k-pcie
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required:
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- compatible
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allOf:
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- $ref: snps,dw-pcie.yaml#
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properties:
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compatible:
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items:
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- enum:
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- marvell,armada8k-pcie
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- const: snps,dw-pcie
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: ctrl
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- const: config
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: reg
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interrupts:
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maxItems: 1
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msi-parent:
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maxItems: 1
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phys:
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minItems: 1
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maxItems: 4
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phy-names:
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minItems: 1
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maxItems: 4
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marvell,reset-gpio:
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maxItems: 1
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deprecated: true
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required:
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- interrupt-map
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- clocks
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- msi-parent
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */
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<0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 13>;
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};
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...
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@ -1,48 +0,0 @@
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* Marvell Armada 7K/8K PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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Required properties:
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- compatible: "marvell,armada8k-pcie"
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- reg: must contain two register regions
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- the control register region
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- the config space region
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- reg-names:
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- "ctrl" for the control register region
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- "config" for the config space region
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- interrupts: Interrupt specifier for the PCIe controller
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- clocks: reference to the PCIe controller clocks
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Optional properties:
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- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
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Either 1, 2 or 4 PHYs might be needed depending on the number of
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PCIe lanes.
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- phy-names: names of the PHYs corresponding to the number of lanes.
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Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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2 PHYs.
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Example:
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pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
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0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 13>;
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};
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@ -115,7 +115,7 @@ properties:
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above for new bindings.
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oneOf:
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- description: See native 'dbi' clock for details
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enum: [ pcie, pcie_apb_sys, aclk_dbi ]
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enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]
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- description: See native 'mstr/slv' clock for details
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enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
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- description: See native 'pipe' clock for details
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@ -201,6 +201,7 @@ properties:
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oneOf:
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- pattern: '^pcie(-?phy[0-9]*)?$'
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- pattern: '^p2u-[0-7]$'
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- pattern: '^cp[01]-pcie[0-2]-x[124](-lane[0-3])?-phy$' # marvell,armada8k-pcie
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reset-gpio:
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deprecated: true
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@ -105,6 +105,8 @@ properties:
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Vendor-specific CSR names. Consider using the generic names above
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for new bindings.
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oneOf:
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- description: See native 'dbi' CSR region for details.
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enum: [ ctrl ]
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- description: See native 'elbi/app' CSR region for details.
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enum: [ apb, mgmt, link, ulreg, appl ]
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- description: See native 'atu' CSR region for details.
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@ -117,7 +119,7 @@ properties:
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const: slcr
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allOf:
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- contains:
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const: dbi
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enum: [ dbi, ctrl ]
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- contains:
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const: config
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@ -18411,7 +18411,7 @@ M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: Documentation/devicetree/bindings/pci/pci-armada8k.txt
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F: Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml
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F: drivers/pci/controller/dwc/pcie-armada8k.c
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PCI DRIVER FOR CADENCE PCIE IP
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