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phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers 

Zeroing out registers does not happen in the downstream kernel, and will
"tune" the repeater in surely unexpected ways since most registers don't
have a reset value of 0x0.

Stop doing that and instead just set the registers that are in the init
sequence (though long term I don't think there's actually PMIC-specific
init sequences, there's board specific tuning, but that's a story for
another day).

Fixes: 99a517a582 ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20250617-eusb2-repeater-tuning-v2-2-ed6c484f18ee@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Luca Weiss 2025-06-17 10:26:36 +02:00 committed by Vinod Koul
parent db9f3e3ff9
commit 31bc94de76
1 changed files with 30 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
View File

@ -37,32 +37,13 @@
#define EUSB2_TUNE_EUSB_EQU 0x5A
#define EUSB2_TUNE_EUSB_HS_COMP_CUR 0x5B
enum eusb2_reg_layout {
TUNE_EUSB_HS_COMP_CUR,
TUNE_EUSB_EQU,
TUNE_EUSB_SLEW,
TUNE_USB2_HS_COMP_CUR,
TUNE_USB2_PREEM,
TUNE_USB2_EQU,
TUNE_USB2_SLEW,
TUNE_SQUELCH_U,
TUNE_HSDISC,
TUNE_RES_FSDIF,
TUNE_IUSB2,
TUNE_USB2_CROSSOVER,
NUM_TUNE_FIELDS,
FORCE_VAL_5 = NUM_TUNE_FIELDS,
FORCE_EN_5,
EN_CTL1,
RPTR_STATUS,
LAYOUT_SIZE,
struct eusb2_repeater_init_tbl_reg {
unsigned int reg;
unsigned int value;
};
struct eusb2_repeater_cfg {
const u32 *init_tbl;
const struct eusb2_repeater_init_tbl_reg *init_tbl;
int init_tbl_num;
const char * const *vreg_list;
int num_vregs;
@ -82,16 +63,16 @@ static const char * const pm8550b_vreg_l[] = {
"vdd18", "vdd3",
};
static const u32 pm8550b_init_tbl[NUM_TUNE_FIELDS] = {
[TUNE_IUSB2] = 0x8,
[TUNE_SQUELCH_U] = 0x3,
[TUNE_USB2_PREEM] = 0x5,
static const struct eusb2_repeater_init_tbl_reg pm8550b_init_tbl[] = {
{ EUSB2_TUNE_IUSB2, 0x8 },
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
{ EUSB2_TUNE_USB2_PREEM, 0x5 },
};
static const u32 smb2360_init_tbl[NUM_TUNE_FIELDS] = {
[TUNE_IUSB2] = 0x5,
[TUNE_SQUELCH_U] = 0x3,
[TUNE_USB2_PREEM] = 0x2,
static const struct eusb2_repeater_init_tbl_reg smb2360_init_tbl[] = {
{ EUSB2_TUNE_IUSB2, 0x5 },
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
{ EUSB2_TUNE_USB2_PREEM, 0x2 },
};
static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
@ -129,17 +110,10 @@ static int eusb2_repeater_init(struct phy *phy)
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
struct device_node *np = rptr->dev->of_node;
struct regmap *regmap = rptr->regmap;
const u32 *init_tbl = rptr->cfg->init_tbl;
u8 tune_usb2_preem = init_tbl[TUNE_USB2_PREEM];
u8 tune_hsdisc = init_tbl[TUNE_HSDISC];
u8 tune_iusb2 = init_tbl[TUNE_IUSB2];
u32 base = rptr->base;
u32 val;
u32 poll_val;
int ret;
of_property_read_u8(np, "qcom,tune-usb2-amplitude", &tune_iusb2);
of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &tune_hsdisc);
of_property_read_u8(np, "qcom,tune-usb2-preem", &tune_usb2_preem);
u8 val;
ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
if (ret)
@ -147,21 +121,24 @@ static int eusb2_repeater_init(struct phy *phy)
regmap_write(regmap, base + EUSB2_EN_CTL1, EUSB2_RPTR_EN);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_HS_COMP_CUR, init_tbl[TUNE_EUSB_HS_COMP_CUR]);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_EQU, init_tbl[TUNE_EUSB_EQU]);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_SLEW, init_tbl[TUNE_EUSB_SLEW]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_HS_COMP_CUR, init_tbl[TUNE_USB2_HS_COMP_CUR]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_EQU, init_tbl[TUNE_USB2_EQU]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_SLEW, init_tbl[TUNE_USB2_SLEW]);
regmap_write(regmap, base + EUSB2_TUNE_SQUELCH_U, init_tbl[TUNE_SQUELCH_U]);
regmap_write(regmap, base + EUSB2_TUNE_RES_FSDIF, init_tbl[TUNE_RES_FSDIF]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_CROSSOVER, init_tbl[TUNE_USB2_CROSSOVER]);
/* Write registers from init table */
for (int i = 0; i < rptr->cfg->init_tbl_num; i++)
regmap_write(regmap, base + rptr->cfg->init_tbl[i].reg,
rptr->cfg->init_tbl[i].value);
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, tune_usb2_preem);
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, tune_hsdisc);
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, tune_iusb2);
/* Override registers from devicetree values */
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val))
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val);
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, val, val & RPTR_OK, 10, 5);
if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val))
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val);
if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val))
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val);
/* Wait for status OK */
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, poll_val,
poll_val & RPTR_OK, 10, 5);
if (ret)
dev_err(rptr->dev, "initialization timed-out\n");