drm/amdgpu: VCN v5_0_1 to prevent FW checking RB during DPG pause
Add a protection to ensure programming are all complete prior VCPU
starting. This is a WA for an unintended VCPU running.
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c29521b529
)
Cc: stable@vger.kernel.org
This commit is contained in:
parent
caade9d69f
commit
46e15197b5
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@ -669,6 +669,9 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
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if (indirect)
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amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
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/* resetting ring, fw should not check RB ring */
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fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
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/* Pause dpg */
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vcn_v5_0_1_pause_dpg_mode(vinst, &state);
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@ -681,7 +684,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
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WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
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@ -692,6 +695,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
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tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
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tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
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/* resetting done, fw can check RB ring */
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fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
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WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,
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