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phy: exynos5-usbdrd: fix clock prepare imbalance 

Commit f4fb9c4d7f ("phy: exynos5-usbdrd: allow DWC3 runtime suspend
with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the
inverse of clk_bulk_prepare_enable() while it should have of course
used clk_bulk_disable_unprepare(). This means incorrect reference
counts to the CMU driver remain.

Update the code accordingly.

Fixes: f4fb9c4d7f ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)")
CC: stable@vger.kernel.org
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251006-gs101-usb-phy-clk-imbalance-v1-1-205b206126cf@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
André Draszik 2025-10-06 09:07:12 +01:00 committed by Vinod Koul
parent 356d1924b9
commit 5e428e45bf
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/samsung/phy-exynos5-usbdrd.c
View File

@ -1823,7 +1823,7 @@ static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw,
phy_drd->orientation = orientation;
}
clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks);
clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks);
return 0;
}