arm64 fixes for -rc3

- Suppress KASAN false positive in stack unwinding code.
 
 - Drop redundant reset of the GCS state on exec().
 
 - Don't try to descend into a !present PMD when creating a huge vmap()
   entry at the PUD level.
 
 - Fix a small typo in the arm64 booting Documentation.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCgAuFiEEPxTL6PPUbjXGY88ct6xw3ITBYzQFAmhUDbUQHHdpbGxAa2Vy
 bmVsLm9yZwAKCRC3rHDchMFjNHmfB/9jJazW5qioi/pAQ2tOFilRBB8miRHmXjUt
 iaChiFa7cPSuqiv4IVRaY66CPkqgp22kTMb4y0Vc4E7WEdzUG21e5F52yhhZlwBB
 CuH0NSOclJ6vnqACyDOLYn7WWgiP+jachcvJlvMp+XiB2dE0z1UyQkwk59j7I/oT
 MHJLfNeIXpUb2k/LkJXAIWEGuNcg4pOREzKlbyl8iGwxvtC7+MjAfYuWSrKTIfLX
 0ixyaqfUY2wFrRsFLowJH/unIDW3Iv1HItCWEtz+j2n3Hh1sJaIo3YcWfG3/AVaO
 eg1atu7ZUYEr9sLaBqJH9JY8lN8UnsnkZ+iUQzciSUTwPJxSARXv
 =L3s/
 -----END PGP SIGNATURE-----

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
 "There's nothing major (even the vmalloc one is just suppressing a
  potential warning) but all worth having, nonetheless.

   - Suppress KASAN false positive in stack unwinding code

   - Drop redundant reset of the GCS state on exec()

   - Don't try to descend into a !present PMD when creating a huge
     vmap() entry at the PUD level

   - Fix a small typo in the arm64 booting Documentation"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/ptrace: Fix stack-out-of-bounds read in regs_get_kernel_stack_nth()
  arm64/gcs: Don't call gcs_free() during flush_gcs()
  arm64: Restrict pagetable teardown to avoid false warning
  docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst
This commit is contained in:
Linus Torvalds 2025-06-20 09:54:24 -07:00
commit d41fef1ce2
4 changed files with 7 additions and 4 deletions

View File

@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met:
- If the kernel is entered at EL1:
- ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
- ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
- ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
- The DT or ACPI tables must describe a GICv3 interrupt controller.

View File

@ -288,7 +288,9 @@ static void flush_gcs(void)
if (!system_supports_gcs())
return;
gcs_free(current);
current->thread.gcspr_el0 = 0;
current->thread.gcs_base = 0;
current->thread.gcs_size = 0;
current->thread.gcs_el0_mode = 0;
write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1);
write_sysreg_s(0, SYS_GCSPR_EL0);

View File

@ -141,7 +141,7 @@ unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
addr += n;
if (regs_within_kernel_stack(regs, (unsigned long)addr))
return *addr;
return READ_ONCE_NOCHECK(*addr);
else
return 0;
}

View File

@ -1305,7 +1305,8 @@ int pud_free_pmd_page(pud_t *pudp, unsigned long addr)
next = addr;
end = addr + PUD_SIZE;
do {
pmd_free_pte_page(pmdp, next);
if (pmd_present(pmdp_get(pmdp)))
pmd_free_pte_page(pmdp, next);
} while (pmdp++, next += PMD_SIZE, next != end);
pud_clear(pudp);