* clk-fixes:
clk: clk-loongson2: Fix the number count of clk provider
clk: mmp2: call pm_genpd_init() only after genpd.name is set
clk: sunxi-ng: a100: enable MMC clock reparenting
clk: clk-imx8mp-audiomix: fix function signature
clk: thead: Fix TH1520 emmc and shdci clock rate
In wrpll_configure_for_rate() we try to determine the best PLL
configuration for a target rate. However, in the loop where we try
values of R, we should compare the derived `vco` with `target_vco_rate`.
However, we were in fact comparing it with `target_rate`, which is
actually after Q shift. This is incorrect, and sometimes can result in
suboptimal clock rates. Fix it.
Fixes: 7b9487a9a5 ("clk: analogbits: add Wide-Range PLL library")
Signed-off-by: Bo Gan <ganboing@gmail.com>
Link: https://lore.kernel.org/r/20240830061639.2316-1-ganboing@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
BCM2712 has an extra clock exposed by the firmware called DISP, and used
by (at least) the HVS. Let's add it to the list of clocks to register in
Linux.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-5-10bc92ffbf41@raspberrypi.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The RaspberryPi firmware clocks driver uses in several instances a
container_of to retrieve the struct raspberrypi_clk_data from a pointer
to struct clk_hw. Let's create a small function to avoid duplicating it
all over the place.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-4-10bc92ffbf41@raspberrypi.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There isn't a reason not to minimise the clocks, and it saves
some power.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-3-10bc92ffbf41@raspberrypi.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
For performance/power it is beneficial to adjust gpu clocks with arm clock.
This is how the downstream cpufreq driver works
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-2-10bc92ffbf41@raspberrypi.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The ISP clock can be controlled by the driver, so register it
with the clock subsystem.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20250116-bcm2712-clk-updates-v1-1-10bc92ffbf41@raspberrypi.com
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Support spread spectrum clock generation for the main PLL, the only one
for which this functionality is available.
Tested on the STM32F469I-DISCO board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20250114182021.670435-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The addition of DT bindings for enabling and tuning spread spectrum
clocking generation is available only for the main PLL of stm32f{4,7}
platforms.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250114182021.670435-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.
The patch also fixes the files referencing to the old st,stm32-rcc.txt.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Replace ternary (condition ? "enable" : "disable") syntax with helpers
from string_choices.h because:
1. Simple function call with one argument is easier to read. Ternary
operator has three arguments and with wrapping might lead to quite
long code.
2. Is slightly shorter thus also easier to read.
3. It brings uniformity in the text - same string.
4. Allows deduping by the linker, which results in a smaller binary
file.
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250114190612.846696-1-krzysztof.kozlowski@linaro.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit 02fb4f0084 ("clk: clk-loongson2: Fix potential buffer
overflow in flexible-array member access"), the clk provider register is
failed.
The count of `clks_num` is shown below:
for (p = data; p->name; p++)
clks_num++;
In fact, `clks_num` represents the number of SoC clocks and should be
expressed as the maximum value of the clock binding id in use (p->id + 1).
Now we fix it to avoid the following error when trying to register a clk
provider:
[ 13.409595] of_clk_hw_onecell_get: invalid index 17
Cc: stable@vger.kernel.org
Cc: Gustavo A. R. Silva <gustavoars@kernel.org>
Fixes: 02fb4f0084 ("clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access")
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/82e43d89a9a6791129cf8ea14f4eeb666cd87be4.1736856470.git.zhoubinbin@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit 706ae64464 ("clk: fixed-rate: add
devm_clk_hw_register_fixed_rate_parent_data()"), we can use the
devm_clk_hw_register_fixed_rate_parent_data() helper and from then on
there is no need to manually unregister the fixed rate hw.
Since clk_hw_unregister_fixed_rate() was not called before, we also fix
the memory leak that was present.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/8733a7485619bdb791de25201a3d7984d1849c9f.1736856470.git.zhoubinbin@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Introduce num_reg to store the number of clocks, this helps to make
_clk_get become a common helper function which called jh71x0_clk_get().
With this, it helps to simplify the code and extend the code in the
future.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Link: https://lore.kernel.org/r/20250114081300.36600-1-changhuang.liang@starfivetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
peripheral is connected to) on rk3588 using pm-clocks, allowing us to
stop marking them as critical and one more rk3588 critical clock, that
the kernel cannot handle otherise right now.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmeGZkMQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgY6oCACuzXo4lF9jXEbymagalV2bCL70R402zs6g
sgSotsXHYbMxfKZMMRdtOBFSLANDcefUM5tqtc5tNPiZUVmCk5SSZAAtI8dAWfAM
Oa+/5xWzEgc0Drfa6Nh8D68bfEgu92RaJp6mkb/zl2yXjh3G+ia1pp/k6CYoe4x+
vCDQPpkJRRCW0TQ7lsOBxRbmql3BgJVlxpczwLeZrXFLwLm+vw8qJ8C/pxua+nQR
wnqrDM25kVsNXEIWFvZ+lcwL6ZXa5bCYw//UssicbNpwSVfZXRKuSshS0GVyOlkW
3pGf2ryS4cHQGxDJPLElMQQueHdb7UNCRxktztgV5u3Fl+Mb4D5m
=ZsYT
-----END PGP SIGNATURE-----
Merge tag 'v6.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
Real handling of the linked clocks (clocks of the interconnect port a
peripheral is connected to) on rk3588 using pm-clocks, allowing us to
stop marking them as critical and one more rk3588 critical clock, that
the kernel cannot handle otherwise right now.
* tag 'v6.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3588: make refclko25m_ethX critical
clk: rockchip: rk3588: drop RK3588_LINKED_CLK
clk: rockchip: implement linked gate clock support
clk: rockchip: expose rockchip_clk_set_lookup
clk: rockchip: rk3588: register GATE_LINK later
clk: rockchip: support clocks registered late
Add clock for eMMC for EN7581. This is used to give info of the current
eMMC source clock and to switch it from 200MHz or 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20250113231030.6735-5-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add ID for eMMC for EN7581. This is to control clock selection of eMMC
between 200MHz and 150MHz.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Drop NUM_CLOCKS define for EN7581 include. This is not a binding and
should not be placed here. Value is derived internally in the user
driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Airoha EN7581 SoC have additional clock compared to EN7523 but current
driver permits to only support up to EN7523 clock numbers.
To handle this, rework the clock handling and permit to declare the
clocks number in match_data and alloca clk_data based on the compatible
match_data.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
cpu2vp_clk is a gate but was mistakenly in th1520_div_clks[] instead
of th1520_gate_clks[].
Fixes: ae81b69fd2 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/r/20241228034802.1573554-1-dfustini@tenstorrent.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the CLK_IGNORE_UNUSED flag to apb_pclk, cpu2peri_x2h_clk,
perisys_apb2_hclk and perisys_apb3_hclk.
Without this flag, the boot hangs after "clk: Disabling unused clocks"
unless clk_ignore_unused is in the kernel cmdline.
Fixes: ae81b69fd2 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/r/20250113-th1520-clk_ignore_unused-v1-2-0b08fb813438@tenstorrent.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Modify the call to devm_clk_hw_register_gate_parent_data() to actually
pass the clk flags from hw.init instead of just 0. This is necessary to
allow individual clk gates to specify their own clk flags.
Fixes: ae81b69fd2 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Link: https://lore.kernel.org/r/20250113-th1520-clk_ignore_unused-v1-1-0b08fb813438@tenstorrent.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
need to redefine it again in fixed clocks section. Hence, remove the duplicate
one from there.
Fixes: d34db686a3 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Don't populate the read-only const arrays pll2_p and dclk_div_adj
on the stack at run time, instead make them static.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20240912134707.590224-1-colin.i.king@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The H616 user manual recommends to re-parent the CPU clock during
frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs
at 600 MHz. Also it asks to disable and then re-enable the PLL lock bit,
after the factor changes have been applied.
Add clock notifiers for the PLL and the CPU mux clock, using the existing
notifier callbacks, and tell them to use mux 4 (the PLL_PERI0(1X) source),
and bit 29 (the LOCK_ENABLE) bit. The existing code already follows the
correct algorithms.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20241025105620.1891596-1-andre.przywara@arm.com
Tested-by: Evgeny Boger <boger@wirenboard.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Introduce support for IPQ CMN PLL, SM6115 LPASS clock controller, SM750
global, tcsr, rpmh, and display clock controllers. GPU clock controller
for X Plus, global and rpmh clock controller for QCS615. RPM clocks are
added for MSM8937 and MSM8940.
Support for Pongo and Taycan Alpha PLLs are added, together with a few
fixes to the existing support. X Elite Titan GDSCs relationship is
described.
SM8550 and SM8650 PCIe GDSCs and X Elite USB GDSC are marked at
retention/on.
SDM845 general purpose clock is improved to allow more arbitrary
frequencies.
IPQ5424 introduces interconnects for NoC-related clocks.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmeCthQVHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FtUQQAME2Fq0hI+UCMR8um1+n2aITRZyg
EgVJTAigOj7AvdGRzAGljypy6th5ED7NNR+/1PcUYY8xye9BnF/GzpSkdPsArUih
yr2IMk6GDwtvc8OfLwbojNWFLV6+kF4ddhRPh5Pjgo+7PURVDhKsGEPE0Akr3n7N
TBKwMxRXPVrRoMvtE2lOWlnTx3ewUtoJfJMTq4F1SySweQcxyLrKRRQu2wzDEyDb
k530Krm7sEAXaImqaxWa4f4XE9NSdz/ZSoELEGUMKXwo+roi0tcvVXvjTXCcWoiy
Ulp2INbAC58H0rwgPcTWBzT5ut0/o+xQS4Hu8JlHpfJGVrYVvqijr9GyuJvvKJrg
A7x47pKzdIRJCcIR5X32B7bitAGLmlUYpHw1oMuk5fDVkZReqHdC7SiXRTzW56Ue
XYXLtVS/Bwc/Dgfi1+cNqRSLAuiRcb1vdBN+Onw56mhAfQFuScLUMS2Rg7sRX8cS
1BrFFNkGrWGwoYoCcpCXKAwKwx//fy5CUFHXASSFnGnVHUeIuRHPxtwddTycixE7
VWEqVdR/S6902eBbKVnLSPgRxKBTs5QaBsX7S6+Tqr7eoLVfmd6lJDwKlTwmR+gs
X3ZA7knJFa/Leq/9Mh0IbMxli2tbYq/eQzRGGXYUoMaHfRuRmqWk28tIRfUE+Jqw
QMheHzVRDy4VaCso
=f311
-----END PGP SIGNATURE-----
Merge tag 'qcom-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
- Support for various Qualcomm clk controllers: IPQ CMN PLL, SM6115
LPASS, SM750 global, tcsr, rpmh, and display. X Plus GPU and global.
QCS615 rpmh and MSM8937 and MSM8940 RPM.
- Support for Qualcomm Pongo and Taycan Alpha PLLs
- Describe Qualcomm X Elite Titan GDSC relationships
- Mark Qualcomm SM8550 and SM8650 PCIe GDSCs and X Elite USB GDSC as
retention/on
- Allow Qualcomm SDM845 general purpose clk to have arbitrary
frequencies
- Add Qualcomm IPQ5424 NoC-related interconnect clks
* tag 'qcom-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (63 commits)
clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
clk: qcom: smd-rpm: Add clocks for MSM8940
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
clk: qcom: smd-rpm: Add clocks for MSM8937
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
dt-bindings: interconnect: Add Qualcomm IPQ5424 support
clk: qcom: Add SM6115 LPASSCC
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
clk: qcom: gcc-sdm845: Add general purpose clock ops
clk: qcom: clk-rcg2: split __clk_rcg2_configure function
clk: qcom: clk-rcg2: document calc_rate function
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
clk: qcom: ipq5424: add gcc_xo_clk
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
clk: qcom: ipq5424: remove apss_dbg clock
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
Ethernet phys normally need a 25MHz refclk input. On a lot of boards
this is done with a dedicated 25MHz crystal. But the rk3588 CRU also
provides a means for that via the refclko25m_ethX clock outputs that
can be used for that function.
The mdio bus normally probes devices on the bus at runtime, by reading
specific phy registers. This requires the phy to be running and thus
also being supplied by its reference clock.
While there exist the possibility and dt-binding to declare these
input clocks for each phy in the phy-dt-node, this is only relevant
_after_ the phy has been detected and during the drivers probe-run.
This results in a chicken-and-egg-problem. The refclks in the CRU are
running on boot of course, but phy-probing can very well happen after
clk_disable_unused has run.
In the past I tried to make clock-handling part of the mdio bus code [0]
but that wasn't very well received, due to it being specific to OF and
clocks with the consensus being that resources needed for detection
need to be enabled before.
So to make probing ethernet phys using the internal refclks possible,
make those 2 clocks critical.
[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
With the proper GATE_LINK support, we no longer need to keep the
linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL
flag for them.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These clock
gates will only have a running output clock when all of the following
conditions are met:
1. the parent clock is enabled
2. the enable bit is set correctly
3. the linked clock is enabled
To handle them this code registers them as a normal gate type clock,
which takes care of condition 1 + 2. The linked clock is handled by
using runtime PM clocks. Handling it via runtime PM requires setting
up a struct device for each of these clocks with a driver attached
to use the correct runtime PM operations. Thus the complete handling
of these clocks has been moved into its own driver.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Move rockchip_clk_add_lookup to clk.h, so that it can be used
by sub-devices with their own driver. These might also have to
do a lookup, so rename the function to rockchip_clk_set_lookup
and add a matching rockchip_clk_get_lookup.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20241211165957.94922-4-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The proper GATE_LINK implementation will use runtime PM to handle the
linked gate clocks, which requires device context. Currently all clocks
are registered early via CLK_OF_DECLARE, which is before the kernel
knows about devices.
Moving the full clocks registration to the probe routine does not work,
since the clocks needed for timers must be registered early.
To work around this issue, most of the clock tree is registered early,
but GATE_LINK clocks are handled in the probe routine. Since the resets
are not needed early either, they have also been moved to the probe
routine.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20241211165957.94922-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
When some clocks are registered late and some clocks are registered
early we need to make sure the late registered clocks report probe defer
until the final registration has happened.
But we do not want to keep reporting probe defer after the late
registration has happened. Also not all Rockchip SoCs have late
registered clocks and may not need to report probe defer at all.
This restructures code a bit, so that there is a new function
rockchip_clk_init_early(), which should be used for initializing the CRU
structure on SoCs making use of late initialization in addition to the
early init. These platforms should call rockchip_clk_finalize()
once all clocks have been registered.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
[added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function]
Link: https://lore.kernel.org/r/20241211165957.94922-2-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Fix the i.MX8MP clkout1/2 support by using sys_plln_out instead of
sys_plln as parents
- Add 208 MHz and 416 MHz entries to the PLL1416x
- Fix the i.MX93 provider by adding the SPDIF IPG clock
- Fix the i.MX93 xcvr DT node clocks by using SPDIF IRP clock instead of
BUS_WAKEUP
- Filter out LVDS, MIPI DSI, PXP, FLEXIO and MU clocks to i.MX93 only
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEETvPuEU56jyrKp9G4G19EyQCVFVYFAmd+atEACgkQG19EyQCV
FVaxwhAAwRoaD8VVbzZBHfzk3QEGmCCOgDaaUwDShaV60rUsiijCFPeql9nSuT6q
qYqw+sJh/JlNF5wEG4b6Kq9dK6ZT5rVsayHqs2FkDmnKrVbPtEyEtDyNk5xTydGk
qqI8wipaswI1Z92CjHIMUBvtFdmAZQDM9Z/pCnOhVF1Dns/CN2bloy/XRI/ZRcra
qAciuDe2J8DLm4ZX8rmw2ZnAHHlMjDMzvokjayfykiMo2KnkLrJFwyFoXbqZvkzx
NzmVWoiwB1Xw2xzPX56T1omkGtshHV/51+HlmIf3NvDjce0tbBlelg2E0HesuyzG
0a/sKtHxTqGGCgYHwNcTLMCiUi0MHhnWxnw+1wc+69vuL4XPZvzId5ZRols4TFYM
0cKSHiBpqfd2f3fKgYgTDnlTm6+ltjEvbD/IyXhqZN2pkJbI3hxdR2VYcOsQctgZ
iD5MT8H6KZyvKLdk5cQCFtm7vwDMmOqyOdyI75ADPPbqCBNyBHQuMnn3ApusoXL8
lBVcbMXtCKD6k2e6O5/gE3dfhSeeAA4FLrGzT7D1lMRZ6yASVIEBESFEo2mmO68k
Q6nv3RW1mnXf19oAdRe+14mzrpyR7yly2tG5/Knpy2piYC68PAIBXVByhoToyPvM
rbyqjs3p/n9n83kThwx184tZmpy0ffAflewSj2elyDTN7yCYTgw=
=WXxL
-----END PGP SIGNATURE-----
Merge tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Fix the i.MX8MP clkout1/2 support by using sys_plln_out instead of
sys_plln as parents
- Add 208 MHz and 416 MHz entries to the PLL1416x
- Fix the i.MX93 provider by adding the SPDIF IPG clock
- Fix the i.MX93 xcvr DT node clocks by using SPDIF IRP clock instead of
BUS_WAKEUP
- Filter out LVDS, MIPI DSI, PXP, FLEXIO and MU clocks to i.MX93 only
* tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx: Apply some clks only for i.MX93
arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
dt-bindings: clock: imx93: Add SPDIF IPG clk
clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
clk: imx8mp: Fix clkout1/2 support
Instead of forcing a particular clock parent for TCON0 on the A64,
the decision is left to the device tree. Which clock parent gets
assigned depends on which display output is used. If the wrong
parent is assigned, the display doesn't work.
Patches include adding the clock parents to the DT binding (which
is shared with the DT tree), removing the now redundant macros from
the clock driver, and stop forcing a particular clock parent in the
driver.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmd+isYOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDAXoxAAo4/JUjUed6u0CT1bbwyR+SarMGu95Mu9BwRJ
fv4NhgvNP+/Ld8MxqKgCCOLwm1avkmAO29aaA/btAN9fjiL0StOOCdZlJWGkh2np
llxIsz7FUNQya00d+CMYPUxoSfGoykNy9d2us7f44gCxWCCEgj1offzk98OnnbS9
pFEF7EPj1eva8uSRpjguDYM+XimE+0v4EnKYhnM9bfNH/UXcrIfsDMFukJLksgRp
6RHow+GpMut+HMlRwZgqAPpwQjR8Mq28z5ISG8pNoUNw5sBcy0VQyut5BQ1muBlW
25U4LaXu7Pgem2LsaIrtrebYUrEwjRRRUxdofTxk/toG/G3vS+gcYsFALfgeK4SV
SNE+22fU1ooadJ55sfSA99UMSWxaWuslr+l+YrtL9fwr12CWYM2e68rg0NubqKSx
JHLEAUXiPf64SRFhrAV3y7O4oqlILaEOUHoivIE0sTm994W2rL+KPPgahy8N3+UC
oq01sQ/Rmyc9KICQ2CvRPE+RzNZKo5KKhZpNWdQWqXc2RHeyZVldIDNAWYze6DQY
lJIXnXQ/GoWOvcURhdr59bKC124LLrcW0t1uvzHNd2oqNC+TPhMxpKTMPDev8vd5
1gbi0Olv2gTb7uGDuRJVGAJFV+nbFJ6q7Z7UKZakG4NEi6X06uVDUYZvjck0c1On
7qtu/y4=
=lnby
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai:
Instead of forcing a particular clock parent for TCON0 on the A64,
the decision is left to the device tree. Which clock parent gets
assigned depends on which display output is used. If the wrong
parent is assigned, the display doesn't work.
Patches include adding the clock parents to the DT binding (which
is shared with the DT tree), removing the now redundant macros from
the clock driver, and stop forcing a particular clock parent in the
driver.
* tag 'sunxi-clk-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
Only one patch, accidentally left out of the 6.13 pull request.
The patch enables automatic clk reparenting for MMC clocks on A100,
thereby fixing MMC support.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmd+ifkOHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDCeYQ/+NHBPCEPSWzDqyY4yoCMVUjiiYYYPGSYPpcxI
UV2py1Uu+qjAQV+xR7ffDtnF7v0hHWNjULx+CqtSDnE9guuRazQJXgnUfY8P0TUf
JWIjRG8aHFrXVjKazv6IQrj8+8fEKTw5GsuZUclnxmvpzcZoVNp62Wg67XbyrnTY
P99/o3Pfg/c3wifo7Xhgq0iu2XzhWkpEqA2/lYLj5KwstQ/2wQUXHnHjSK0HA3eA
hdI6RKKX9EQHDni8MEmzgFbdWU5aH2UwMwknO+jVRToGz82jBlXVfYVdEfnJ0hap
nliavVt2JFVQIT0V5OTSaudrkdDX9YbchpwStk6ua7uAc1WDUpcK316gX5QmCoja
jVvSecX9oZ/DCnMwWQq3Fcxblo+bTZ2+KvIeuT2uvgDchxmhRjCWdDdPD387nC8H
638jgL9CgiwJ/uP2HwoVOxQjHM0BkvgxT9Ie/o5ZQ8KWELeL2ncN5QGeB6qATQdj
4rLExfmbkhmtkk0mkOwdWMZszfApuyNcOnQvU8fqGR0t2TeMWLBo4KC/mfcVTnvP
yz/cIPVH+WIQPZEC1Kv7hZJ66EdFc70/YDBW1E4PmEFYyFQ+jc2HRPt9mkGWqjCJ
wUeSN9JavVmTeAwaJUHkUUODsWNMW1xEOLyjOZIRjMCpu8uRf6xn+GFF5es9yRsh
Tqbg980=
=5Aso
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-fixes-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull an Allwinner clk driver fix from Chen-Yu Tsai:
Only one patch, accidentally left out of the 6.13 pull request.
The patch enables automatic clk reparenting for MMC clocks on A100,
thereby fixing MMC support.
* tag 'sunxi-clk-fixes-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a100: enable MMC clock reparenting
Setting the genpd's struct device's name with dev_set_name() is
happening within pm_genpd_init(). If it remains NULL, things can blow up
later, such as when crafting the devfs hierarchy for the power domain:
Unable to handle kernel NULL pointer dereference at virtual address 00000000 when read
...
Call trace:
strlen from start_creating+0x90/0x138
start_creating from debugfs_create_dir+0x20/0x178
debugfs_create_dir from genpd_debug_add.part.0+0x4c/0x144
genpd_debug_add.part.0 from genpd_debug_init+0x74/0x90
genpd_debug_init from do_one_initcall+0x5c/0x244
do_one_initcall from kernel_init_freeable+0x19c/0x1f4
kernel_init_freeable from kernel_init+0x1c/0x12c
kernel_init from ret_from_fork+0x14/0x28
Bisecting tracks this crash back to commit 899f44531f ("pmdomain: core:
Add GENPD_FLAG_DEV_NAME_FW flag"), which exchanges use of genpd->name
with dev_name(&genpd->dev) in genpd_debug_add.part().
Fixes: 899f44531f ("pmdomain: core: Add GENPD_FLAG_DEV_NAME_FW flag")
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Cc: stable@vger.kernel.org # v6.12+
Link: https://lore.kernel.org/r/20241231190336.423172-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit 99c21c7ca6 ("clk: qcom: Add X1P42100 GPUCC driver") adds the
config definition CLK_X1P42100_GPUCC. This config definition selects the
non-existing config CLK_X1E8010_GCC. Note that the config for the X1E80100
Global Clock Controller is CLK_X1E80100_GCC.
Assuming this was just a minor typo in the number, i.e., 8010 instead of
80100, change the definition to select the existing config
CLK_X1E80100_GCC, similarly to the definitions for three configs
CLK_X1E80100_{CAMCC,DISPCC,GPUCC}.
Fixes: 99c21c7ca6 ("clk: qcom: Add X1P42100 GPUCC driver")
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@redhat.com>
Link: https://lore.kernel.org/r/20250107104728.23098-1-lukas.bulwahn@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add an x1e80100 camcc binding. x1e80100 has two power-domain parents unlike
other similar camcc controllers.
Differentiate the new structure into a unique camcc definition. Other
similar camcc controller setups can then be easily added to this one.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-2-cb66d55d20cc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
MSM8937 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and
IPA_CLK.
Signed-off-by: Daniil Titov <daniilt971@gmail.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241231-rpmcc-v1-2-1212df9b2042@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Use the icc-clk framework to enable few clocks to be able to
create paths and use the peripherals connected on those NoCs.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241213105808.674620-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add master/slave ids for Qualcomm IPQ5424 Network-On-Chip
interfaces. This will be used by the gcc-ipq5424 driver
for providing interconnect services using the icc-clk framework.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241213105808.674620-1-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.
Add the required code to support them.
[alexey.klimov] fixed compilation errors after rebase,
slightly changed the commit message
Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241212002551.2902954-3-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephen Boyd
Bo Gan
Maxime Ripard
Dom Cobley
Dario Binacchi
Krzysztof Kozlowski
Binbin Zhou
Changhuang Liang
Christian Marangi
Drew Fustini
Sergio Paracuellos
Colin Ian King
Andre Przywara
Heiko Stuebner
Sebastian Reichel
Lubomir Rintel
Lukas Bulwahn
Bryan O'Donoghue
Daniil Titov
Varadarajan Narayanan
Konrad Dybcio