Carolina Jubran ff97bc38be net/mlx5: Add RS FEC histogram infrastructure ... Define the Ports Phy Histogram Configuration Register (PPHCR) to expose RS-FEC histogram bin ranges, and expose a new counter group in the Ports Performance Counters Register (PPCNT) to report the corresponding histogram values. Co-developed-by: Yael Chemla <ychemla@nvidia.com> Signed-off-by: Yael Chemla <ychemla@nvidia.com> Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1756884600-520195-1-git-send-email-tariqt@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org>		2025-09-09 04:18:19 -04:00
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acpi	mailbox/pcc: support mailbox management of the shared buffer	2025-08-07 23:49:56 -05:00
asm-generic	…
clocksource	…
crypto	This push fixes a regression that breaks hmac(sha3-224-s390).	2025-08-09 07:26:19 +03:00
cxl	…
drm	…
dt-bindings	…
hyperv	…
keys	…
kunit	…
kvm	…
linux	net/mlx5: Add RS FEC histogram infrastructure	2025-09-09 04:18:19 -04:00
math-emu	…
media	…
memory	…
misc	…
net	Previous releases - regressions:	2025-08-08 07:03:25 +03:00
pcmcia	…
ras	…
rdma	…
rv	…
scsi	…
soc	…
sound	ASoC: Fixes for v6.17	2025-08-06 20:20:25 +02:00
target	…
trace	…
uapi	TTY revert fix for 6.16-rc1	2025-08-09 18:12:23 +03:00
ufs	…
vdso	…
video	…
xen	Significant patch series in this pull request:	2025-08-03 16:23:09 -07:00
Kbuild	…