ff97bc38be
Define the Ports Phy Histogram Configuration Register (PPHCR) to expose RS-FEC histogram bin ranges, and expose a new counter group in the Ports Performance Counters Register (PPCNT) to report the corresponding histogram values. Co-developed-by: Yael Chemla <ychemla@nvidia.com> Signed-off-by: Yael Chemla <ychemla@nvidia.com> Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1756884600-520195-1-git-send-email-tariqt@nvidia.com Signed-off-by: Leon Romanovsky <leon@kernel.org> |
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| .. | ||
| cq.h | ||
| device.h | ||
| doorbell.h | ||
| driver.h | ||
| eq.h | ||
| eswitch.h | ||
| fs.h | ||
| fs_helpers.h | ||
| macsec.h | ||
| mlx5_ifc.h | ||
| mlx5_ifc_fpga.h | ||
| mlx5_ifc_vdpa.h | ||
| mpfs.h | ||
| port.h | ||
| qp.h | ||
| rsc_dump.h | ||
| transobj.h | ||
| vport.h | ||