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Add missing 64 bit shift operations to the X64 macro assembler 

Change-Id: I1e593e5ed0bb24ed3a158d98495209945c8bb309
Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
This commit is contained in:
Lars Knoll 2017-02-08 14:18:42 +01:00
parent 3e80f3bef9
commit 7fa8393aac
2 changed files with 73 additions and 20 deletions
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51
src/3rdparty/masm/assembler/MacroAssemblerX86_64.h vendored
View File

@ -327,14 +327,61 @@ public:
m_assembler.xorq_ir(imm.m_value, srcDest); m_assembler.xorq_ir(imm.m_value, srcDest);
} }
void lshift64(TrustedImm32 imm, RegisterID dest)
{
m_assembler.shlq_i8r(imm.m_value, dest);
}
void lshift64(RegisterID src, RegisterID dest)
{
if (src == X86Registers::ecx)
m_assembler.shlq_CLr(dest);
else {
ASSERT(src != dest);
// Can only shift by ecx, so we do some swapping if we see anything else.
swap(src, X86Registers::ecx);
m_assembler.shlq_CLr(dest == X86Registers::ecx ? src : dest);
swap(src, X86Registers::ecx);
}
}
void rshift64(TrustedImm32 imm, RegisterID dest)
{
m_assembler.sarq_i8r(imm.m_value, dest);
}
void rshift64(RegisterID src, RegisterID dest)
{
if (src == X86Registers::ecx)
m_assembler.sarq_CLr(dest);
else {
ASSERT(src != dest);
// Can only shift by ecx, so we do some swapping if we see anything else.
swap(src, X86Registers::ecx);
m_assembler.sarq_CLr(dest == X86Registers::ecx ? src : dest);
swap(src, X86Registers::ecx);
}
}
void urshift64(TrustedImm32 imm, RegisterID dest) void urshift64(TrustedImm32 imm, RegisterID dest)
{ {
m_assembler.shrq_i8r(imm.m_value, dest); m_assembler.shrq_i8r(imm.m_value, dest);
} }
void lshift64(TrustedImm32 imm, RegisterID dest) void urshift64(RegisterID src, RegisterID dest)
{ {
m_assembler.shlq_i8r(imm.m_value, dest); if (src == X86Registers::ecx)
m_assembler.shrq_CLr(dest);
else {
ASSERT(src != dest);
// Can only shift by ecx, so we do some swapping if we see anything else.
swap(src, X86Registers::ecx);
m_assembler.shrq_CLr(dest == X86Registers::ecx ? src : dest);
swap(src, X86Registers::ecx);
}
} }
void load64(ImplicitAddress address, RegisterID dest) void load64(ImplicitAddress address, RegisterID dest)

42
src/3rdparty/masm/assembler/X86Assembler.h vendored
View File

@ -723,6 +723,21 @@ public:
} }
} }
void sarq_CLr(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);
}
void sarq_i8r(int imm, RegisterID dst)
{
if (imm == 1)
m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);
else {
m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);
m_formatter.immediate8(imm);
}
}
void shrq_i8r(int imm, RegisterID dst) void shrq_i8r(int imm, RegisterID dst)
{ {
// ### doesn't work when removing the "0 &&" // ### doesn't work when removing the "0 &&"
@ -734,6 +749,11 @@ public:
} }
} }
void shrq_CLr(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SHR, dst);
}
void shlq_i8r(int imm, RegisterID dst) void shlq_i8r(int imm, RegisterID dst)
{ {
// ### doesn't work when removing the "0 &&" // ### doesn't work when removing the "0 &&"
@ -745,7 +765,10 @@ public:
} }
} }
void shlq_CLr(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst);
}
#endif #endif
void sarl_i8r(int imm, RegisterID dst) void sarl_i8r(int imm, RegisterID dst)
@ -793,23 +816,6 @@ public:
m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst); m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst);
} }
#if CPU(X86_64)
void sarq_CLr(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);
}
void sarq_i8r(int imm, RegisterID dst)
{
if (imm == 1)
m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);
else {
m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);
m_formatter.immediate8(imm);
}
}
#endif
void imull_rr(RegisterID src, RegisterID dst) void imull_rr(RegisterID src, RegisterID dst)
{ {
m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, src); m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, src);