The APLL_CFG3/DDAC_SR_LMT0/DTOP_DIGEN_CLKE should be correct with different sample rates and clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Change-Id: I766879750e640ef8ab31c2ab6776fe96ac65e063 (cherry picked from commit 23830a21b3eedd92818a6a2af9d7c882d73081e2) |
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ac97 | ||
aoa | ||
arm | ||
atmel | ||
core | ||
drivers | ||
firewire | ||
hda | ||
i2c | ||
isa | ||
mips | ||
oss | ||
parisc | ||
pci | ||
pcmcia | ||
ppc | ||
sh | ||
soc | ||
sparc | ||
spi | ||
synth | ||
usb | ||
x86 | ||
xen | ||
Kconfig | ||
Makefile | ||
ac97_bus.c | ||
last.c | ||
sound_core.c |