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clk: rockchip: rk3308: print arm enter and init rate 

Change-Id: I6df66d7b5dda643dba49ee87c2a2c0544ddbcded
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-01-22 16:47:04 +08:00 committed by Jianhong Chen
parent f7913bc128
commit 093fdd9f5d
2 changed files with 28 additions and 8 deletions
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5
arch/arm/include/asm/arch-rockchip/cru_rk3308.h
View File

@ -51,7 +51,10 @@ struct rk3308_clk_priv {
ulong dpll_hz; ulong dpll_hz;
ulong vpll0_hz; ulong vpll0_hz;
ulong vpll1_hz; ulong vpll1_hz;
bool is_assigned; ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
}; };
struct rk3308_cru { struct rk3308_cru {

31
drivers/clk/rockchip/clk_rk3308.c
View File

@ -851,7 +851,7 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)
priv->cru, DPLL); priv->cru, DPLL);
break; break;
case ARMCLK: case ARMCLK:
if (priv->is_assigned) if (priv->armclk_hz)
rk3308_armclk_set_clk(priv, rate); rk3308_armclk_set_clk(priv, rate);
priv->armclk_hz = rate; priv->armclk_hz = rate;
break; break;
@ -1071,13 +1071,23 @@ static int rk3308_clk_probe(struct udevice *dev)
struct rk3308_clk_priv *priv = dev_get_priv(dev); struct rk3308_clk_priv *priv = dev_get_priv(dev);
int ret; int ret;
priv->sync_kernel = false;
if (!priv->armclk_enter_hz)
priv->armclk_enter_hz =
rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
priv->cru, APLL);
rk3308_clk_init(dev); rk3308_clk_init(dev);
if (!priv->armclk_init_hz)
priv->armclk_init_hz =
rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
priv->cru, APLL);
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
ret = clk_set_defaults(dev); ret = clk_set_defaults(dev);
if (ret) if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret); debug("%s clk_set_defaults failed %d\n", __func__, ret);
priv->is_assigned = true; else
priv->sync_kernel = true;
return 0; return 0;
} }
@ -1152,6 +1162,7 @@ U_BOOT_DRIVER(rockchip_rk3308_cru) = {
int soc_clk_dump(void) int soc_clk_dump(void)
{ {
struct udevice *cru_dev; struct udevice *cru_dev;
struct rk3308_clk_priv *priv;
const struct rk3308_clk_info *clk_dump; const struct rk3308_clk_info *clk_dump;
struct clk clk; struct clk clk;
unsigned long clk_count = ARRAY_SIZE(clks_dump); unsigned long clk_count = ARRAY_SIZE(clks_dump);
@ -1166,7 +1177,13 @@ int soc_clk_dump(void)
return ret; return ret;
} }
printf("CLK:\n"); priv = dev_get_priv(cru_dev);
printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
priv->sync_kernel ? "sync kernel" : "uboot",
priv->armclk_enter_hz / 1000,
priv->armclk_init_hz / 1000,
priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
priv->set_armclk_rate ? " KHz" : "N/A");
for (i = 0; i < clk_count; i++) { for (i = 0; i < clk_count; i++) {
clk_dump = &clks_dump[i]; clk_dump = &clks_dump[i];
if (clk_dump->name) { if (clk_dump->name) {
@ -1179,17 +1196,17 @@ int soc_clk_dump(void)
clk_free(&clk); clk_free(&clk);
if (i == 0) { if (i == 0) {
if (rate < 0) if (rate < 0)
printf("%s %s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%s %lu KHz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000); rate / 1000);
} else { } else {
if (rate < 0) if (rate < 0)
printf("%s %s\n", clk_dump->name, printf(" %s %s\n", clk_dump->name,
"unknown"); "unknown");
else else
printf("%s %lu KHz\n", clk_dump->name, printf(" %s %lu KHz\n", clk_dump->name,
rate / 1000); rate / 1000);
} }
} }