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clk: rockchip: rv1126: Fix gpll_hz is zero when set gpll clk 

Change-Id: Iecd64e83d2a841b711c80528a245d2e9bda11265
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2020-03-03 14:51:59 +08:00
parent ffe82b3398
commit 0945879144
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk_rv1126.c
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@ -1651,6 +1651,7 @@ static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate)
return ret;
}
pmu_priv = dev_get_priv(pmucru_dev);
priv->gpll_hz = pmu_priv->gpll_hz;
if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) {
printf("%s: failed to set gpll rate %lu\n", __func__, rate);