mmc: add default_phase
Add default sample clock phase and it can be used when run mmc_send_tuning. The function mmc_send_tuning will use default_phase directly to set the sample clock phase, and this can improve tuning's efficiency. If use default_phase to run mmc_send_tuning fail, it will change to tune 0&45...&270 phase. Change-Id: I747f7820a7d2a67ffb9152794acec31b15e97e2b Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
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@ -282,6 +282,8 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
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dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
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dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
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if (dev_read_bool(dev, "mmc-hs200-1_8v"))
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if (dev_read_bool(dev, "mmc-hs200-1_8v"))
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plat->cfg.host_caps |= MMC_MODE_HS200;
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plat->cfg.host_caps |= MMC_MODE_HS200;
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plat->mmc.default_phase =
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dev_read_u32_default(dev, "default-sample-phase", 0);
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host->mmc = &plat->mmc;
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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host->mmc->priv = &priv->host;
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host->mmc->dev = dev;
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host->mmc->dev = dev;
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@ -566,6 +566,7 @@ struct mmc {
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uint write_bl_len;
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uint write_bl_len;
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uint erase_grp_size; /* in 512-byte sectors */
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uint erase_grp_size; /* in 512-byte sectors */
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uint hc_wp_grp_size; /* in 512-byte sectors */
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uint hc_wp_grp_size; /* in 512-byte sectors */
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int default_phase; /* set the default sample clock phase */
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struct sd_ssr ssr; /* SD status register */
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struct sd_ssr ssr; /* SD status register */
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struct emmc_esr esr; /* emmc status register */
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struct emmc_esr esr; /* emmc status register */
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u64 capacity;
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u64 capacity;
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