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video/drm: lvds: default bypass rgb data sync on px30 

Change-Id: Ic1a8590da16dcc68fe457a9bc011e40e64298c75
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi 2018-05-17 14:30:01 +08:00 committed by Jianhong Chen
parent f3f5bcc0a3
commit 154ef77707
2 changed files with 3 additions and 1 deletions
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2
drivers/video/drm/rockchip_lvds.c
View File

@ -220,7 +220,7 @@ static void px30_output_ttl(struct display_state *state)
u32 val = 0;
/* enable lvds mode */
val = PX30_LVDS_PHY_MODE(0) | PX30_DPHY_FORCERXMODE(1);
val = PX30_RGB_SYNC_BYPASS(1) | PX30_DPHY_FORCERXMODE(1);
writel(val, lvds->grf + PX30_GRF_PD_VO_CON1);
/* enable lane */

2
drivers/video/drm/rockchip_lvds.h
View File

@ -118,6 +118,8 @@
#define PX30_LVDS_PHY_MODE(x) (BITS_MASK(x, 0x1, 12) | BITS_EN(0x1, 12))
#define PX30_LVDS_MSBSEL(x) (BITS_MASK(x, 0x1, 11) | BITS_EN(0x1, 11))
#define PX30_DPHY_FORCERXMODE(x) (BITS_MASK(x, 0x1, 6) | BITS_EN(0x1, 6))
#define PX30_LCDC_DCLK_INV(x) (BITS_MASK(x, 0x1, 4) | BITS_EN(0x1, 4))
#define PX30_RGB_SYNC_BYPASS(x) (BITS_MASK(x, 0x1, 3) | BITS_EN(0x1, 3))
#define PX30_RGB_VOP_SEL(x) (BITS_MASK(x, 0x1, 2) | BITS_EN(0x1, 2))
#define PX30_LVDS_VOP_SEL(x) (BITS_MASK(x, 0x1, 1) | BITS_EN(0x1, 1))