rockchip: dts: rv1126: add gmac support
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I19edafc1fc9402d6f9a4123c935e8a0881071960
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11a331d232
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1619e70322
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@ -143,3 +143,102 @@
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&gpio3 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&gmac {
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u-boot,dm-pre-reloc;
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>;
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assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
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assigned-clock-rates = <125000000>, <0>, <25000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
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tx_delay = <0x2a>;
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rx_delay = <0x1a>;
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phy-handle = <&phy>;
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status = "okay";
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};
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&mdio {
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u-boot,dm-pre-reloc;
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status = "okay";
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phy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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u-boot,dm-pre-reloc;
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reg = <0x0>;
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clocks = <&cru CLK_GMAC_ETHERNET_OUT>;
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};
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};
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&stmmac_axi_setup {
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u-boot,dm-pre-reloc;
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status = "okay";
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queue0 {
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u-boot,dm-pre-reloc;
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};
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};
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&mtl_rx_setup {
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u-boot,dm-pre-reloc;
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status = "okay";
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queue0 {
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u-boot,dm-pre-reloc;
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};
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};
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&mtl_tx_setup {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&gmac_clkin_m0 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&gmac_clkini_m1 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&rgmiim1_pins {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&clk_out_ethernetm1_pins{
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pcfg_pull_none {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&pcfg_pull_none_drv_level_12 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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