qiurui
/
rv1126-uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

clk: rockchip: rk1808: fix up the dclk_raw/lite set rate error 

Change-Id: I0b8c7d0e15501c7ecc3c5acb0e0844e722ad18ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-10-10 09:03:18 +08:00
parent 25098c06f4
commit 1ae6d6e5c8
2 changed files with 18 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/include/asm/arch-rockchip/cru_rk1808.h
View File

@ -122,9 +122,9 @@ enum {
HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT,
/* CRU_CLK_SEL5_CON */
DCLK_VOPRAW_SEL_VOPRAW = 1,
DCLK_VOPRAW_SEL_VOPRAW_FRAC = 2,
DCLK_VOPRAW_SEL_XIN24M = 3,
DCLK_VOPRAW_SEL_VOPRAW = 0,
DCLK_VOPRAW_SEL_VOPRAW_FRAC = 1,
DCLK_VOPRAW_SEL_XIN24M = 2,
DCLK_VOPRAW_SEL_SHIFT = 14,
DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT,
DCLK_VOPRAW_PLL_SEL_CPLL = 0,
@ -133,12 +133,12 @@ enum {
DCLK_VOPRAW_PLL_SEL_SHIFT = 10,
DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT,
DCLK_VOPRAW_DIV_CON_SHIFT = 0,
DCLK_VOPRAW_DIV_CON_MASK = 0xf << DCLK_VOPRAW_DIV_CON_SHIFT,
DCLK_VOPRAW_DIV_CON_MASK = 0xff << DCLK_VOPRAW_DIV_CON_SHIFT,
/* CRU_CLK_SEL7_CON */
DCLK_VOPLITE_SEL_VOPRAW = 1,
DCLK_VOPLITE_SEL_VOPRAW_FRAC = 2,
DCLK_VOPLITE_SEL_XIN24M = 3,
DCLK_VOPLITE_SEL_VOPRAW = 0,
DCLK_VOPLITE_SEL_VOPRAW_FRAC = 1,
DCLK_VOPLITE_SEL_XIN24M = 2,
DCLK_VOPLITE_SEL_SHIFT = 14,
DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT,
DCLK_VOPLITE_PLL_SEL_CPLL = 0,
@ -147,7 +147,7 @@ enum {
DCLK_VOPLITE_PLL_SEL_SHIFT = 10,
DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT,
DCLK_VOPLITE_DIV_CON_SHIFT = 0,
DCLK_VOPLITE_DIV_CON_MASK = 0xf << DCLK_VOPLITE_DIV_CON_SHIFT,
DCLK_VOPLITE_DIV_CON_MASK = 0xff << DCLK_VOPLITE_DIV_CON_SHIFT,
/* CRU_CLK_SEL19_CON */
CLK_PERI_PLL_SEL_GPLL = 0,

16
drivers/clk/rockchip/clk_rk1808.c
View File

@ -84,7 +84,7 @@ static struct rockchip_pll_clock rk1808_pll_clks[] = {
RK1808_MODE_CON, 4, 10, 0, rk1808_pll_rates),
[GPLL] = PLL(pll_rk3036, PLL_GPLL, RK1808_PLL_CON(24),
RK1808_MODE_CON, 6, 10, 0, rk1808_pll_rates),
[NPLL] = PLL(pll_rk3036, PLL_NPLL, RK1808_PLL_CON(24),
[NPLL] = PLL(pll_rk3036, PLL_NPLL, RK1808_PLL_CON(32),
RK1808_MODE_CON, 8, 10, 0, rk1808_pll_rates),
[PPLL] = PLL(pll_rk3036, PLL_PPLL, RK1808_PMU_PLL_CON(0),
RK1808_PMU_MODE_CON, 0, 10, 0, rk1808_pll_rates),
@ -517,8 +517,6 @@ static ulong rk1808_vop_set_clk(struct rk1808_clk_priv *priv,
* vopb dclk source from npll, and equals to
*/
src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ, hz);
rockchip_pll_set_rate(&rk1808_pll_clks[NPLL],
priv->cru, NPLL, src_clk_div * hz);
rk_clrsetreg(&cru->clksel_con[5],
DCLK_VOPRAW_SEL_MASK |
DCLK_VOPRAW_PLL_SEL_MASK |
@ -528,6 +526,9 @@ static ulong rk1808_vop_set_clk(struct rk1808_clk_priv *priv,
DCLK_VOPRAW_PLL_SEL_NPLL <<
DCLK_VOPRAW_PLL_SEL_SHIFT |
(src_clk_div - 1) << DCLK_VOPRAW_DIV_CON_SHIFT);
rockchip_pll_set_rate(&rk1808_pll_clks[NPLL],
priv->cru, NPLL, src_clk_div * hz);
break;
case DCLK_VOPLITE:
/*
@ -546,9 +547,10 @@ static ulong rk1808_vop_set_clk(struct rk1808_clk_priv *priv,
rk_clrsetreg(&cru->clksel_con[7],
DCLK_VOPLITE_SEL_MASK | DCLK_VOPLITE_PLL_SEL_MASK |
DCLK_VOPLITE_DIV_CON_MASK,
DCLK_VOPLITE_SEL_VOPRAW << DCLK_VOPLITE_SEL_SHIFT |
parent << DCLK_VOPLITE_PLL_SEL_SHIFT |
(src_clk_div - 1) << DCLK_VOPLITE_DIV_CON_SHIFT);
(DCLK_VOPLITE_SEL_VOPRAW <<
DCLK_VOPLITE_SEL_SHIFT) |
(parent << DCLK_VOPLITE_PLL_SEL_SHIFT) |
((src_clk_div - 1) << DCLK_VOPLITE_DIV_CON_SHIFT));
break;
default:
printf("do not support this vop freq\n");
@ -1076,6 +1078,8 @@ static int rk1808_clk_probe(struct udevice *dev)
priv->cru, CPLL);
priv->gpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[GPLL],
priv->cru, GPLL);
priv->npll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[NPLL],
priv->cru, NPLL);
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
ret = clk_set_defaults(dev);