video/drm: dsi: fix pll clock setting for synopsys phy
Change-Id: Ib2cfdf413e3c4da039a16971fcc00baaab3b101c Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> (sync from rk/kernel:develop-4.4:331690a183f536fe8a791ceed4231f7e484f8fb7)
This commit is contained in:
Wyon Bi
Jianhong Chen
parent
cef5be6b54
commit
1c3c799444
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@ -229,6 +229,7 @@ struct mipi_dphy {
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};
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struct dw_mipi_dsi {
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struct udevice *dev;
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void *base;
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void *grf;
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const void *blob;
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@ -468,6 +469,9 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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mipi_dphy_rstz_deassert(dsi);
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mdelay(2);
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if (dsi->dphy.phy)
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rockchip_phy_power_on(dsi->dphy.phy);
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ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
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val, val & PHY_LOCK,
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1000, PHY_STATUS_TIMEOUT_US);
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@ -537,76 +541,106 @@ static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5));
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}
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static unsigned long dw_mipi_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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static unsigned long dw_mipi_dsi_get_lane_rate(struct dw_mipi_dsi *dsi)
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{
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int bpp;
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unsigned long mpclk, tmp;
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unsigned long target_mbps = 1000;
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unsigned int max_mbps;
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int lanes;
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int rate;
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const struct drm_display_mode *mode = dsi->mode;
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unsigned long max_lane_rate = dsi->pdata->max_bit_rate_per_lane;
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unsigned long lane_rate;
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unsigned int value;
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int bpp, lanes;
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u64 tmp;
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/* optional override of the desired bandwidth */
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rate = ofnode_read_u32_default(dsi->node, "rockchip,lane-rate", -1);
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if (rate > 0) {
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return rate;
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}
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max_mbps = dsi->pdata->max_bit_rate_per_lane / USEC_PER_SEC;
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value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0);
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if (value > 0)
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return value * USEC_PER_SEC;
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bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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if (bpp < 0) {
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printf("failed to get bpp for pixel format %d\n",
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dsi->format);
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if (bpp < 0)
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bpp = 24;
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}
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lanes = dsi->slave ? dsi->lanes * 2 : dsi->lanes;
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tmp = (u64)mode->clock * 1000 * bpp;
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do_div(tmp, lanes);
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mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
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if (mpclk) {
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/* take 1 / 0.9, since mbps must big than bandwidth of RGB */
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tmp = mpclk * (bpp / lanes) * 10 / 9;
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if (tmp < max_mbps)
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target_mbps = tmp;
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else
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printf("DPHY clock frequency is out of range\n");
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}
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/* take 1 / 0.9, since mbps must big than bandwidth of RGB */
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tmp *= 10;
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do_div(tmp, 9);
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return target_mbps;
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if (tmp > max_lane_rate)
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lane_rate = max_lane_rate;
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else
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lane_rate = tmp;
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return lane_rate;
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}
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static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_set_pll(struct dw_mipi_dsi *dsi, unsigned long rate)
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{
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unsigned int i, pre;
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unsigned long pllref, tmp;
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unsigned int m = 1, n = 1;
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unsigned long target_mbps;
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unsigned long fin, fout;
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unsigned long fvco_min, fvco_max, best_freq = 984000000;
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u8 min_prediv, max_prediv;
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u8 _prediv, best_prediv = 2;
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u16 _fbdiv, best_fbdiv = 82;
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u32 min_delta = ~0U;
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if (dsi->master)
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return 0;
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fin = 24000000;
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fout = rate;
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target_mbps = dw_mipi_dsi_calc_bandwidth(dsi);
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/* 5Mhz < Fref / N < 40MHz, 80MHz < Fvco < 1500Mhz */
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min_prediv = DIV_ROUND_UP(fin, 40000000);
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max_prediv = fin / 5000000;
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fvco_min = 80000000;
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fvco_max = 1500000000;
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/* ref clk : 24MHz*/
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pllref = 24;
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tmp = pllref;
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for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
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u64 tmp, _fout;
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u32 delta;
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for (i = 1; i < 6; i++) {
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pre = pllref / i;
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if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
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tmp = target_mbps % pre;
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n = i;
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m = target_mbps / pre;
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}
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if (tmp == 0)
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/* Fvco = Fref * M / N */
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tmp = (u64)fout * _prediv;
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do_div(tmp, fin);
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_fbdiv = tmp;
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/*
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* Due to the use of a "by 2 pre-scaler," the range of the
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* feedback multiplication value M is limited to even division
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* numbers, and m must be greater than 12, less than 1000.
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*/
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if (_fbdiv <= 12 || _fbdiv >= 1000)
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continue;
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if (_fbdiv % 2)
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++_fbdiv;
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_fout = (u64)_fbdiv * fin;
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do_div(_fout, _prediv);
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if (_fout < fvco_min || _fout > fvco_max)
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continue;
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delta = abs(fout - _fout);
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if (!delta) {
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best_prediv = _prediv;
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best_fbdiv = _fbdiv;
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best_freq = _fout;
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break;
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} else if (delta < min_delta) {
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best_prediv = _prediv;
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best_fbdiv = _fbdiv;
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best_freq = _fout;
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min_delta = delta;
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}
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}
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dsi->lane_mbps = pllref / n * m;
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dsi->dphy.input_div = n;
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dsi->dphy.feedback_div = m;
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return 0;
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dsi->lane_mbps = best_freq / USEC_PER_SEC;
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dsi->dphy.input_div = best_prediv;
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dsi->dphy.feedback_div = best_fbdiv;
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if (dsi->slave) {
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dsi->slave->lane_mbps = dsi->lane_mbps;
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dsi->slave->dphy.input_div = dsi->dphy.input_div;
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dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div;
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}
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}
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static int dw_mipi_dsi_read_from_fifo(struct dw_mipi_dsi *dsi,
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@ -1108,16 +1142,11 @@ static int dw_mipi_dsi_connector_init(struct display_state *state)
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const struct rockchip_connector *connector = conn_state->connector;
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const struct dw_mipi_dsi_plat_data *pdata = connector->data;
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ofnode mipi_node = conn_state->node;
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struct dw_mipi_dsi *dsi;
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struct dw_mipi_dsi *dsi = dev_get_priv(conn_state->dev);
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ofnode panel;
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int id;
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int ret;
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dsi = malloc(sizeof(*dsi));
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if (!dsi)
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return -ENOMEM;
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memset(dsi, 0, sizeof(*dsi));
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dsi->base = dev_read_addr_ptr(conn_state->dev);
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dsi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (dsi->grf <= 0) {
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@ -1169,29 +1198,10 @@ static int dw_mipi_dsi_connector_init(struct display_state *state)
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return 0;
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}
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static void dw_mipi_dsi_pre_init(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_set_hs_clk(struct dw_mipi_dsi *dsi, unsigned long rate)
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{
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unsigned long bw, rate;
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if (dsi->dphy.phy) {
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bw = dw_mipi_dsi_calc_bandwidth(dsi);
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rate = rockchip_phy_set_pll(dsi->dphy.phy, bw * USEC_PER_SEC);
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dsi->lane_mbps = rate / USEC_PER_SEC;
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rockchip_phy_set_mode(dsi->dphy.phy, PHY_MODE_VIDEO_MIPI);
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rockchip_phy_power_on(dsi->dphy.phy);
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} else {
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dw_mipi_dsi_get_lane_bps(dsi);
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}
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if (dsi->slave) {
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dsi->slave->mode = dsi->mode;
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dsi->slave->lane_mbps = dsi->lane_mbps;
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dsi->slave->dphy.input_div = dsi->dphy.input_div;
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dsi->slave->dphy.feedback_div = dsi->dphy.feedback_div;
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}
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printf("final DSI-Link bandwidth: %u Mbps x %d\n",
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dsi->lane_mbps, dsi->lanes);
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rate = rockchip_phy_set_pll(dsi->dphy.phy, rate);
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dsi->lane_mbps = rate / USEC_PER_SEC;
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}
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static void dw_mipi_dsi_host_init(struct dw_mipi_dsi *dsi)
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@ -1270,11 +1280,22 @@ static int dw_mipi_dsi_connector_prepare(struct display_state *state)
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struct connector_state *conn_state = &state->conn_state;
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struct crtc_state *crtc_state = &state->crtc_state;
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struct dw_mipi_dsi *dsi = conn_state->private;
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unsigned long lane_rate;
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dsi->mode = &conn_state->mode;
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if (dsi->slave)
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dsi->slave->mode = dsi->mode;
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lane_rate = dw_mipi_dsi_get_lane_rate(dsi);
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if (dsi->dphy.phy)
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dw_mipi_dsi_set_hs_clk(dsi, lane_rate);
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else
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dw_mipi_dsi_set_pll(dsi, lane_rate);
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printf("final DSI-Link bandwidth: %u Mbps x %d\n",
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dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);
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dw_mipi_dsi_vop_routing(dsi, crtc_state->crtc_id);
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dw_mipi_dsi_pre_init(dsi);
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dw_mipi_dsi_pre_enable(dsi);
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return 0;
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@ -1519,6 +1540,10 @@ static const struct udevice_id dw_mipi_dsi_ids[] = {
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static int dw_mipi_dsi_probe(struct udevice *dev)
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{
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struct dw_mipi_dsi *dsi = dev_get_priv(dev);
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dsi->dev = dev;
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return 0;
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}
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