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clk: rockchip: rk3308: support pclk_wdt get rate 

Change-Id: I001cfef774c9657b6286467dc4ef841771841895
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-04-09 17:37:45 +08:00
parent ced960d2b6
commit 221585fb35
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk_rk3308.c
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@ -576,6 +576,7 @@ static ulong rk3308_bus_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT;
break;
case PCLK_BUS:
case PCLK_WDT:
con = readl(&cru->clksel_con[6]);
div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
break;
@ -858,6 +859,7 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
case ACLK_BUS:
case HCLK_BUS:
case PCLK_BUS:
case PCLK_WDT:
rate = rk3308_bus_get_clk(priv, clk->id);
break;
case ACLK_PERI: