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video/drm: combo_phy: Add support RK356X LVDS 

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ieb7cf88e00201540388599b063e9c77dd019d8e8
This commit is contained in:
Sandy Huang 2021-02-08 10:50:44 +08:00 committed by Jianhong Chen
parent 5f0cde7958
commit 22dd40273d
1 changed files with 19 additions and 2 deletions
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21
drivers/video/drm/inno_video_combo_phy.c
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@ -83,6 +83,14 @@
#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
#define LOWFRE_EN_MASK BIT(5)
#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
/* Analog Register Part: reg1e */
#define PLL_MODE_SEL_MASK GENMASK(6, 5)
#define PLL_MODE_SEL_LVDS_MODE 0
#define PLL_MODE_SEL_MIPI_MODE BIT(5)
/* Digital Register Part: reg00 */
#define REG_DIG_RSTN_MASK BIT(0)
#define REG_DIG_RSTN_NORMAL BIT(0)
@ -433,8 +441,9 @@ static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
/* Sample clock reverse direction */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
SAMPLE_CLOCK_DIRECTION_MASK,
SAMPLE_CLOCK_DIRECTION_REVERSE);
SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
SAMPLE_CLOCK_DIRECTION_REVERSE |
PLL_OUTPUT_FREQUENCY_DIV_BY_1);
/* Select LVDS mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
@ -456,6 +465,10 @@ static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
if (ret)
dev_err(phy->dev, "PLL is not lock\n");
/* Select PLL mode */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
/* Reset LVDS digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
@ -707,6 +720,10 @@ static const struct udevice_id inno_video_phy_ids[] = {
.compatible = "rockchip,rk3368-video-phy",
.data = (ulong)&inno_video_phy_driver_data,
},
{
.compatible = "rockchip,rk3568-video-phy",
.data = (ulong)&inno_video_phy_driver_data,
},
{}
};