video/drm: dsi: Don't hardcode/bypass phy default parameters
Change-Id: If8670bee99c1397647323b34acd3e3da028549c3 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> (sync from rk/kernel:develop-4.4:bd920c36fc56d00a24d3688510c84c62d7921c6a)
This commit is contained in:
Wyon Bi
Jianhong Chen
parent
374e75505b
commit
2612c8202d
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@ -188,68 +188,13 @@
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#define PHY_STATUS_TIMEOUT_US 10000
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#define PHY_STATUS_TIMEOUT_US 10000
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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#define BYPASS_VCO_RANGE BIT(7)
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/* Test Code: 0x44 (HS RX Control of Lane 0) */
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#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
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#define HSFREQRANGE(x) UPDATE(x, 6, 1)
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#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
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/* Test Code: 0x17 (PLL Input Divider Ratio) */
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#define VCO_IN_CAP_CON_LOW (0x1 << 1)
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#define INPUT_DIV(x) UPDATE(x, 6, 0)
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#define VCO_IN_CAP_CON_HIGH (0x2 << 1)
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/* Test Code: 0x18 (PLL Loop Divider Ratio) */
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#define REF_BIAS_CUR_SEL BIT(0)
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#define FEEDBACK_DIV_LO(x) UPDATE(x, 4, 0)
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#define FEEDBACK_DIV_HI(x) (BIT(7) | UPDATE(x, 3, 0))
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#define CP_CURRENT_3MA BIT(3)
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#define CP_PROGRAM_EN BIT(7)
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#define LPF_PROGRAM_EN BIT(6)
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#define LPF_RESISTORS_20_KOHM 0
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#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
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#define INPUT_DIVIDER(val) ((val - 1) & 0x7f)
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#define LOW_PROGRAM_EN 0
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#define HIGH_PROGRAM_EN BIT(7)
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#define LOOP_DIV_LOW_SEL(val) ((val - 1) & 0x1f)
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#define LOOP_DIV_HIGH_SEL(val) (((val - 1) >> 5) & 0x1f)
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#define PLL_LOOP_DIV_EN BIT(5)
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#define PLL_INPUT_DIV_EN BIT(4)
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#define POWER_CONTROL BIT(6)
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#define INTERNAL_REG_CURRENT BIT(3)
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#define BIAS_BLOCK_ON BIT(2)
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#define BANDGAP_ON BIT(0)
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#define TER_RESISTOR_HIGH BIT(7)
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#define TER_RESISTOR_LOW 0
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#define LEVEL_SHIFTERS_ON BIT(6)
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#define TER_CAL_DONE BIT(5)
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#define SETRD_MAX (0x7 << 2)
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#define POWER_MANAGE BIT(1)
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#define TER_RESISTORS_ON BIT(0)
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#define BIASEXTR_SEL(val) ((val) & 0x7)
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#define BANDGAP_SEL(val) ((val) & 0x7)
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#define TLP_PROGRAM_EN BIT(7)
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#define THS_PRE_PROGRAM_EN BIT(7)
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#define THS_ZERO_PROGRAM_EN BIT(6)
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enum {
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BANDGAP_97_07,
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BANDGAP_98_05,
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BANDGAP_99_02,
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BANDGAP_100_00,
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BANDGAP_93_17,
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BANDGAP_94_15,
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BANDGAP_95_12,
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BANDGAP_96_10,
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};
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enum {
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BIASEXTR_87_1,
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BIASEXTR_91_5,
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BIASEXTR_95_9,
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BIASEXTR_100,
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BIASEXTR_105_94,
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BIASEXTR_111_88,
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BIASEXTR_118_8,
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BIASEXTR_127_7,
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};
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#define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb))
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#define GRF_REG_FIELD(reg, lsb, msb) ((reg << 16) | (lsb << 8) | (msb))
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@ -305,36 +250,6 @@ struct dw_mipi_dsi {
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const struct dw_mipi_dsi_plat_data *pdata;
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const struct dw_mipi_dsi_plat_data *pdata;
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};
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};
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struct dphy_pll_testdin_map {
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unsigned int max_mbps;
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u8 testdin;
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};
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/* The table is based on 27MHz DPHY pll reference clock. */
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static const struct dphy_pll_testdin_map dptdin_map[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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static int max_mbps_to_testdin(unsigned int max_mbps)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
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if (dptdin_map[i].max_mbps > max_mbps)
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return dptdin_map[i].testdin;
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return -EINVAL;
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}
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static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
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static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
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{
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{
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writel(val, dsi->base + reg);
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writel(val, dsi->base + reg);
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@ -577,45 +492,44 @@ static int mipi_dphy_power_on(struct dw_mipi_dsi *dsi)
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return 0;
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return 0;
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}
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}
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static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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static void dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
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{
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{
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int testdin, vco, val;
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/* Table 5-1 Frequency Ranges */
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const struct {
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unsigned long max_lane_mbps;
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u8 hsfreqrange;
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} hsfreqrange_table[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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u8 hsfreqrange;
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unsigned int index;
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u16 n, m;
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vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (dsi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
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break;
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testdin = max_mbps_to_testdin(dsi->lane_mbps);
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if (index == ARRAY_SIZE(hsfreqrange_table))
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if (testdin < 0) {
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--index;
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printf("failed to get testdin for %dmbps lane clock\n",
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dsi->lane_mbps);
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return testdin;
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}
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testif_write(dsi, 0x10, BYPASS_VCO_RANGE | VCO_RANGE_CON_SEL(vco) |
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hsfreqrange = hsfreqrange_table[index].hsfreqrange;
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VCO_IN_CAP_CON_LOW | REF_BIAS_CUR_SEL);
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testif_write(dsi, 0x44, HSFREQRANGE(hsfreqrange));
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testif_write(dsi, 0x11, CP_CURRENT_3MA);
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testif_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN |
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LPF_RESISTORS_20_KOHM);
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testif_write(dsi, 0x44, HSFREQRANGE_SEL(testdin));
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testif_write(dsi, 0x17, INPUT_DIVIDER(dsi->dphy.input_div));
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val = LOOP_DIV_LOW_SEL(dsi->dphy.feedback_div) | LOW_PROGRAM_EN;
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testif_write(dsi, 0x18, val);
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testif_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
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val = LOOP_DIV_HIGH_SEL(dsi->dphy.feedback_div) | HIGH_PROGRAM_EN;
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testif_write(dsi, 0x18, val);
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testif_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
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testif_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT |
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BIAS_BLOCK_ON | BANDGAP_ON);
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testif_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE |
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SETRD_MAX | TER_RESISTORS_ON);
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testif_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
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SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON);
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testif_write(dsi, 0x22, LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
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testif_write(dsi, 0x22, HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
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testif_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf);
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testif_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x2d);
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testif_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa);
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return 0;
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n = dsi->dphy.input_div - 1;
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m = dsi->dphy.feedback_div - 1;
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testif_write(dsi, 0x19, 0x30);
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testif_write(dsi, 0x17, INPUT_DIV(n));
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testif_write(dsi, 0x18, FEEDBACK_DIV_LO(m));
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testif_write(dsi, 0x18, FEEDBACK_DIV_HI(m >> 5));
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}
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}
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static unsigned long dw_mipi_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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static unsigned long dw_mipi_dsi_calc_bandwidth(struct dw_mipi_dsi *dsi)
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