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irq: gicv3: use cpu interface system registers for gicc read/write 

RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e49ee61afe57560dcc4eba6233f2aca3f2
This commit is contained in:
Joseph Chen 2020-10-26 10:14:45 +08:00
parent 3582f7fa15
commit 275a49e3fb
1 changed files with 25 additions and 2 deletions
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27
drivers/irq/irq-gic.c
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@ -230,15 +230,24 @@ static int gic_irq_get(void)
static int gic_irq_suspend(void)
{
int irq_nr, i, irq;
#ifndef CONFIG_GICV2
u32 reg;
#endif
/* irq nr */
irq_nr = ((gicd_readl(GICD_TYPER) & 0x1f) + 1) * 32;
if (irq_nr > 1020)
irq_nr = 1020;
/* GICC save */
#ifdef CONFIG_GICV2
gicc_save.ctlr = gicc_readl(GICC_CTLR);
gicc_save.pmr = gicc_readl(GICC_PMR);
#else
asm volatile("mrs %0, " __stringify(ICC_CTLR_EL1) : "=r" (reg));
gicc_save.ctlr = reg;
asm volatile("mrs %0, " __stringify(ICC_PMR_EL1) : "=r" (reg));
gicc_save.pmr = reg;
#endif
/* GICD save */
gicd_save.ctlr = gicd_readl(GICD_CTLR);
@ -275,13 +284,20 @@ static int gic_irq_suspend(void)
static int gic_irq_resume(void)
{
int irq_nr, i, irq;
#ifndef CONFIG_GICV2
u32 reg;
#endif
irq_nr = ((gicd_readl(GICD_TYPER) & 0x1f) + 1) * 32;
if (irq_nr > 1020)
irq_nr = 1020;
/* Disable ctrl register */
#ifdef CONFIG_GICV2
gicc_writel(0, GICC_CTLR);
#else
reg = 0;
asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (reg));
#endif
gicd_writel(0, GICD_CTLR);
dsb();
@ -315,8 +331,15 @@ static int gic_irq_resume(void)
GICD_ISPENDRn + IRQ_REG_X32(irq));
dsb();
#ifdef CONFIG_GICV2
gicc_writel(gicc_save.pmr, GICC_PMR);
gicc_writel(gicc_save.ctlr, GICC_CTLR);
#else
reg = gicc_save.pmr;
asm volatile("msr " __stringify(ICC_PMR_EL1) ", %0" : : "r" (reg));
reg = gicc_save.ctlr;
asm volatile("msr " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (reg));
#endif
gicd_writel(gicd_save.ctlr, GICD_CTLR);
dsb();