video/drm: inno_mipi_phy: Add support for rk1808
Change-Id: I79d7b33f8458502ed8015d38a4b79a24a7bf7328 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
This commit is contained in:
Nickey Yang
Jianhong Chen
parent
f8841d3b05
commit
27d50ce711
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@ -26,63 +26,79 @@
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#define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
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/* Innosilicon MIPI D-PHY registers */
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#define INNO_PHY_LANE_CTRL 0x00000
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#define MIPI_BGPD BIT(7)
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#define CLK_LANE_EN_MASK BIT(6)
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#define DATA_LANE_3_EN_MASK BIT(5)
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#define DATA_LANE_2_EN_MASK BIT(4)
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#define DATA_LANE_1_EN_MASK BIT(3)
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#define DATA_LANE_0_EN_MASK BIT(2)
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#define CLK_LANE_EN BIT(6)
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#define DATA_LANE_3_EN BIT(5)
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#define DATA_LANE_2_EN BIT(4)
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#define DATA_LANE_1_EN BIT(3)
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#define DATA_LANE_0_EN BIT(2)
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#define PWROK_BP BIT(1)
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#define PWROK BIT(0)
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#define INNO_PHY_POWER_CTRL 0x00004
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#define ANALOG_RESET_MASK BIT(2)
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#define ANALOG_RESET BIT(2)
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#define ANALOG_NORMAL 0
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#define LDO_POWER_MASK BIT(1)
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#define LDO_POWER_DOWN BIT(1)
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#define LDO_POWER_ON 0
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#define PLL_POWER_MASK BIT(0)
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#define PLL_POWER_DOWN BIT(0)
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#define PLL_POWER_ON 0
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#define INNO_PHY_PLL_CTRL_0 0x0000c
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#define FBDIV_HI_MASK BIT(5)
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#define FBDIV_HI(x) UPDATE(x, 5, 5)
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#define PREDIV_MASK GENMASK(4, 0)
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#define PREDIV(x) UPDATE(x, 4, 0)
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#define INNO_PHY_PLL_CTRL_1 0x00010
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#define FBDIV_LO_MASK GENMASK(7, 0)
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#define FBDIV_LO(x) UPDATE(x, 7, 0)
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#define INNO_PHY_DIG_CTRL 0x00080
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#define DIGITAL_RESET_MASK BIT(0)
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#define DIGITAL_NORMAL BIT(0)
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#define DIGITAL_RESET 0
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#define INNO_PHY_LVDS_CTRL 0x003ac
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#define LVDS_BGPD BIT(0)
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#define INNO_PHY_LANE_CTRL 0x0000
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#define MIPI_BGPD BIT(7)
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#define CLK_LANE_EN_MASK BIT(6)
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#define DATA_LANE_3_EN_MASK BIT(5)
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#define DATA_LANE_2_EN_MASK BIT(4)
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#define DATA_LANE_1_EN_MASK BIT(3)
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#define DATA_LANE_0_EN_MASK BIT(2)
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#define CLK_LANE_EN BIT(6)
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#define DATA_LANE_3_EN BIT(5)
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#define DATA_LANE_2_EN BIT(4)
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#define DATA_LANE_1_EN BIT(3)
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#define DATA_LANE_0_EN BIT(2)
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#define PWROK_BP BIT(1)
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#define PWROK BIT(0)
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#define INNO_PHY_POWER_CTRL 0x0004
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#define ANALOG_RESET_MASK BIT(2)
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#define ANALOG_RESET BIT(2)
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#define ANALOG_NORMAL 0
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#define LDO_POWER_MASK BIT(1)
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#define LDO_POWER_DOWN BIT(1)
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#define LDO_POWER_ON 0
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#define PLL_POWER_MASK BIT(0)
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#define PLL_POWER_DOWN BIT(0)
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#define PLL_POWER_ON 0
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#define INNO_PHY_PLL_CTRL_0 0x000c
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#define FBDIV_HI_MASK BIT(5)
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#define FBDIV_HI(x) UPDATE(x, 5, 5)
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#define PREDIV_MASK GENMASK(4, 0)
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#define PREDIV(x) UPDATE(x, 4, 0)
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#define INNO_PHY_PLL_CTRL_1 0x0010
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#define FBDIV_LO_MASK GENMASK(7, 0)
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#define FBDIV_LO(x) UPDATE(x, 7, 0)
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#define ANALOG_REG_08 0x0020
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#define PRE_EMPHASIS_ENABLE_MASK BIT(7)
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#define PRE_EMPHASIS_ENABLE BIT(7)
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#define PRE_EMPHASIS_DISABLE 0
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#define PLL_POST_DIV_ENABLE_MASK BIT(5)
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#define PLL_POST_DIV_ENABLE BIT(5)
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#define PLL_POST_DIV_DISABLE 0
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#define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
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#define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
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#define ANALOG_REG_0B 0x002c
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#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
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#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
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#define VOD_MIN_RANGE 0x1
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#define VOD_MID_RANGE 0x3
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#define VOD_BIG_RANGE 0x7
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#define VOD_MAX_RANGE 0xf
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#define INNO_PHY_DIG_CTRL 0x0080
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#define DIGITAL_RESET_MASK BIT(0)
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#define DIGITAL_NORMAL BIT(0)
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#define DIGITAL_RESET 0
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#define INNO_PHY_LVDS_CTRL 0x03ac
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#define LVDS_BGPD BIT(0)
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#define INNO_CLOCK_LANE_REG_BASE 0x00100
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#define INNO_DATA_LANE_0_REG_BASE 0x00180
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#define INNO_DATA_LANE_1_REG_BASE 0x00200
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#define INNO_DATA_LANE_2_REG_BASE 0x00280
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#define INNO_DATA_LANE_3_REG_BASE 0x00300
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#define INNO_CLOCK_LANE_REG_BASE 0x0100
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#define INNO_DATA_LANE_0_REG_BASE 0x0180
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#define INNO_DATA_LANE_1_REG_BASE 0x0200
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#define INNO_DATA_LANE_2_REG_BASE 0x0280
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#define INNO_DATA_LANE_3_REG_BASE 0x0300
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#define T_LPX_OFFSET 0x00014
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#define T_HS_PREPARE_OFFSET 0x00018
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#define T_HS_ZERO_OFFSET 0x0001c
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#define T_HS_TRAIL_OFFSET 0x00020
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#define T_HS_EXIT_OFFSET 0x00024
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#define T_CLK_POST_OFFSET 0x00028
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#define T_WAKUP_H_OFFSET 0x00030
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#define T_WAKUP_L_OFFSET 0x00034
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#define T_CLK_PRE_OFFSET 0x00038
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#define T_TA_GO_OFFSET 0x00040
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#define T_TA_SURE_OFFSET 0x00044
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#define T_TA_WAIT_OFFSET 0x00048
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#define T_LPX_OFFSET 0x0014
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#define T_HS_PREPARE_OFFSET 0x0018
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#define T_HS_ZERO_OFFSET 0x001c
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#define T_HS_TRAIL_OFFSET 0x0020
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#define T_HS_EXIT_OFFSET 0x0024
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#define T_CLK_POST_OFFSET 0x0028
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#define T_WAKUP_H_OFFSET 0x0030
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#define T_WAKUP_L_OFFSET 0x0034
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#define T_CLK_PRE_OFFSET 0x0038
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#define T_TA_GO_OFFSET 0x0040
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#define T_TA_SURE_OFFSET 0x0044
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#define T_TA_WAIT_OFFSET 0x0048
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#define T_LPX_MASK GENMASK(5, 0)
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#define T_LPX(x) UPDATE(x, 5, 0)
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@ -109,6 +125,11 @@
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#define T_TA_WAIT_MASK GENMASK(5, 0)
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#define T_TA_WAIT(x) UPDATE(x, 5, 0)
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enum soc_type {
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RV1108_MIPI_DPHY,
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RK1808_MIPI_DPHY,
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};
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enum lane_type {
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CLOCK_LANE,
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DATA_LANE_0,
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@ -198,19 +219,37 @@ struct fixed_param {
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};
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static const struct fixed_param fixed_param_table[] = {
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FIXED_PARAM( 110, 0x20, 0x16, 0x02, 0x22),
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FIXED_PARAM( 150, 0x06, 0x16, 0x03, 0x45),
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FIXED_PARAM( 200, 0x18, 0x17, 0x04, 0x0b),
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FIXED_PARAM( 250, 0x05, 0x17, 0x05, 0x16),
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FIXED_PARAM( 300, 0x51, 0x18, 0x06, 0x2c),
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FIXED_PARAM( 400, 0x64, 0x19, 0x07, 0x33),
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FIXED_PARAM( 500, 0x20, 0x1b, 0x07, 0x4e),
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FIXED_PARAM( 600, 0x6a, 0x1d, 0x08, 0x3a),
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FIXED_PARAM( 700, 0x3e, 0x1e, 0x08, 0x6a),
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FIXED_PARAM( 800, 0x21, 0x1f, 0x09, 0x29),
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FIXED_PARAM(110, 0x20, 0x16, 0x02, 0x22),
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FIXED_PARAM(150, 0x06, 0x16, 0x03, 0x45),
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FIXED_PARAM(200, 0x18, 0x17, 0x04, 0x0b),
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FIXED_PARAM(250, 0x05, 0x17, 0x05, 0x16),
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FIXED_PARAM(300, 0x51, 0x18, 0x06, 0x2c),
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FIXED_PARAM(400, 0x64, 0x19, 0x07, 0x33),
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FIXED_PARAM(500, 0x20, 0x1b, 0x07, 0x4e),
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FIXED_PARAM(600, 0x6a, 0x1d, 0x08, 0x3a),
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FIXED_PARAM(700, 0x3e, 0x1e, 0x08, 0x6a),
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FIXED_PARAM(800, 0x21, 0x1f, 0x09, 0x29),
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FIXED_PARAM(1000, 0x09, 0x20, 0x09, 0x27)
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};
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static const struct fixed_param rk1808_fixed_param_table[] = {
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FIXED_PARAM(110, 0x7f, 0x16, 0x02, 0x02),
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FIXED_PARAM(150, 0x7f, 0x16, 0x03, 0x02),
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FIXED_PARAM(200, 0x7f, 0x17, 0x04, 0x02),
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FIXED_PARAM(250, 0x7f, 0x17, 0x05, 0x04),
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FIXED_PARAM(300, 0x7f, 0x18, 0x06, 0x04),
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FIXED_PARAM(400, 0x7e, 0x19, 0x07, 0x04),
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FIXED_PARAM(500, 0x7c, 0x1b, 0x07, 0x08),
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FIXED_PARAM(600, 0x70, 0x1d, 0x08, 0x10),
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FIXED_PARAM(700, 0x40, 0x1e, 0x08, 0x30),
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FIXED_PARAM(800, 0x02, 0x1f, 0x09, 0x30),
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FIXED_PARAM(1000, 0x08, 0x20, 0x09, 0x30),
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FIXED_PARAM(1400, 0x03, 0x32, 0x14, 0x0f),
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FIXED_PARAM(1600, 0x42, 0x36, 0x0e, 0x0f),
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FIXED_PARAM(1800, 0x47, 0x7a, 0x0e, 0x0f),
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FIXED_PARAM(2000, 0x64, 0x7a, 0x0e, 0x0b),
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};
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static inline void inno_write(struct inno_mipi_dphy *inno, u32 reg, u32 val)
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{
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writel(val, inno->regs + reg);
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@ -320,19 +359,28 @@ static void inno_mipi_dphy_timing_update(struct inno_mipi_dphy *inno,
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static void inno_mipi_dphy_get_fixed_param(struct inno_mipi_dphy_timing *t,
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unsigned int freq,
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enum soc_type soc_type,
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enum lane_type lane_type)
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{
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const struct fixed_param *param;
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int i;
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const struct fixed_param *param, *param_table;
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int i, param_num;
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for (i = 0; i < ARRAY_SIZE(fixed_param_table); i++)
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if (freq <= fixed_param_table[i].max_freq)
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if (soc_type == RK1808_MIPI_DPHY) {
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param_table = rk1808_fixed_param_table;
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param_num = ARRAY_SIZE(rk1808_fixed_param_table);
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} else {
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param_table = fixed_param_table;
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param_num = ARRAY_SIZE(fixed_param_table);
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}
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for (i = 0; i < param_num; i++)
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if (freq <= param_table[i].max_freq)
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break;
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if (i == ARRAY_SIZE(fixed_param_table))
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if (i == param_num)
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--i;
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param = &fixed_param_table[i];
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param = ¶m_table[i];
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if (lane_type == CLOCK_LANE)
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t->hs_zero = param->clk_lane.hs_zero;
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@ -346,6 +394,8 @@ static void inno_mipi_dphy_get_fixed_param(struct inno_mipi_dphy_timing *t,
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static void inno_mipi_dphy_lane_timing_init(struct inno_mipi_dphy *inno,
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enum lane_type lane_type)
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{
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struct rockchip_phy *phy =
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(struct rockchip_phy *)dev_get_driver_data(inno->dev);
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struct mipi_dphy_timing timing;
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struct inno_mipi_dphy_timing data;
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unsigned long txbyteclk, txclkesc, UI;
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@ -363,7 +413,8 @@ static void inno_mipi_dphy_lane_timing_init(struct inno_mipi_dphy *inno,
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txbyteclk, txclkesc, esc_clk_div, UI);
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mipi_dphy_timing_get_default(&timing, UI);
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inno_mipi_dphy_get_fixed_param(&data, inno->lane_mbps, lane_type);
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inno_mipi_dphy_get_fixed_param(&data, inno->lane_mbps,
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phy->soc_type, lane_type);
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/*
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* Ttxbyteclk * val >= Ths-exit
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@ -599,6 +650,14 @@ static unsigned long inno_mipi_dphy_set_pll(struct rockchip_phy *phy,
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v = FBDIV_LO(fbdiv);
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inno_update_bits(inno, INNO_PHY_PLL_CTRL_1, m, v);
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if (phy->soc_type == RK1808_MIPI_DPHY) {
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inno_update_bits(inno, ANALOG_REG_08,
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PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
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inno_update_bits(inno, ANALOG_REG_0B,
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CLOCK_LANE_VOD_RANGE_SET_MASK,
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CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
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}
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inno->lane_mbps = fout / USEC_PER_SEC;
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return fout;
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@ -637,7 +696,13 @@ static const struct rockchip_phy_funcs inno_mipi_dphy_funcs = {
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};
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static struct rockchip_phy inno_mipi_dphy_driver_data = {
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.funcs = &inno_mipi_dphy_funcs,
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.soc_type = RV1108_MIPI_DPHY,
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};
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static struct rockchip_phy rk1808_inno_mipi_dphy_driver_data = {
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.funcs = &inno_mipi_dphy_funcs,
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.soc_type = RK1808_MIPI_DPHY,
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};
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static const struct udevice_id inno_mipi_dphy_ids[] = {
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@ -645,6 +710,10 @@ static const struct udevice_id inno_mipi_dphy_ids[] = {
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.compatible = "rockchip,rv1108-mipi-dphy",
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.data = (ulong)&inno_mipi_dphy_driver_data,
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},
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{
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.compatible = "rockchip,rk1808-mipi-dphy",
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.data = (ulong)&rk1808_inno_mipi_dphy_driver_data,
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},
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{}
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};
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@ -30,6 +30,7 @@ struct rockchip_phy {
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struct udevice *dev;
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const struct rockchip_phy_funcs *funcs;
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const void *data;
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int soc_type;
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};
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int rockchip_phy_init(struct rockchip_phy *phy);
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