From 2bff5c680e0d1241f405cf0295f97fd85b8a785d Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 22 Dec 2020 09:20:30 +0800 Subject: [PATCH] clk: rockchip: rv1126: Only change APLL rate to 1008MHz for tb fixes: (c1bad47 clk: rockchip: rv1126: Change APLL rate to 1008MHz) Change-Id: If0c284af8c5710b43d353fdf6b12b226c288ae07 Signed-off-by: Finley Xiao --- arch/arm/include/asm/arch-rockchip/cru_rv1126.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h index 7ab80900c9..c304fce0d2 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -13,7 +13,11 @@ #define KHz 1000 #define OSC_HZ (24 * MHz) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) #define APLL_HZ (1008 * MHz) +#else +#define APLL_HZ (816 * MHz) +#endif #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (500 * MHz) #define HPLL_HZ (1400 * MHz)