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clk: rockchip: rv1126: Only change APLL rate to 1008MHz for tb 

fixes: (c1bad47 clk: rockchip: rv1126: Change APLL rate to 1008MHz)

Change-Id: If0c284af8c5710b43d353fdf6b12b226c288ae07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2020-12-22 09:20:30 +08:00 committed by Jianhong Chen
parent 3a5404aff4
commit 2bff5c680e
1 changed files with 4 additions and 0 deletions
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4
arch/arm/include/asm/arch-rockchip/cru_rv1126.h
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@ -13,7 +13,11 @@
#define KHz 1000 #define KHz 1000
#define OSC_HZ (24 * MHz) #define OSC_HZ (24 * MHz)
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
#define APLL_HZ (1008 * MHz) #define APLL_HZ (1008 * MHz)
#else
#define APLL_HZ (816 * MHz)
#endif
#define GPLL_HZ (1188 * MHz) #define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (500 * MHz) #define CPLL_HZ (500 * MHz)
#define HPLL_HZ (1400 * MHz) #define HPLL_HZ (1400 * MHz)