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drivers: ram: rv1126: use read preamble training mode for ddr4 

Change-Id: I8128352f9727a502c029c08eb57e486a9835c405
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
This commit is contained in:
Tang Yun ping 2020-06-19 11:46:51 +08:00
parent 4298c19d4f
commit 2c5208e273
1 changed files with 2 additions and 15 deletions
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17
drivers/ram/rockchip/sdram_rv1126.c
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@ -1457,7 +1457,6 @@ static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype)
u32 dis_auto_zq = 0;
u32 odt_val_up, odt_val_dn;
u32 i, j;
u32 weak_pull;
odt_val_dn = readl(PHY_REG(phy_base, 0x110));
odt_val_up = readl(PHY_REG(phy_base, 0x111));
@ -1475,13 +1474,8 @@ static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype)
/* use normal read mode for data training */
clrbits_le32(PHY_REG(phy_base, 0xc), BIT(1));
if (dramtype == DDR4) {
weak_pull = readl(PHY_REG(phy_base, 0x114));
writel(weak_pull & ~(0x3), PHY_REG(phy_base, 0x114));
writel(weak_pull & ~(0x3), PHY_REG(phy_base, 0x124));
writel(weak_pull & ~(0x3), PHY_REG(phy_base, 0x134));
writel(weak_pull & ~(0x3), PHY_REG(phy_base, 0x144));
}
if (dramtype == DDR4)
setbits_le32(PHY_REG(phy_base, 0xc), BIT(1));
/* choose training cs */
clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
@ -1494,13 +1488,6 @@ static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype)
clrbits_le32(PHY_REG(phy_base, 2), 0x30);
pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
if (dramtype == DDR4) {
writel(weak_pull, PHY_REG(phy_base, 0x114));
writel(weak_pull, PHY_REG(phy_base, 0x124));
writel(weak_pull, PHY_REG(phy_base, 0x134));
writel(weak_pull, PHY_REG(phy_base, 0x144));
}
if (ret & 0x20)
ret = -1;
else